JP2593639B2 - Insulated gate field effect semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an insulated gate field effect semiconductor device.

[Conventional technology]

FIG. 1 is a longitudinal sectional view of a conventional insulated gate field effect semiconductor device. That is, a conventional insulated gate field effect semiconductor device using an amorphous semiconductor includes an insulating substrate (1), gate electrodes (3) and (13) formed on the insulating substrate (1), and the gate electrode ( 3) and (1)
3) A gate insulating film (11) formed thereon, and channel forming regions (5) and (5) arranged so as to face the gate electrodes (3) and (13) via the gate insulating film (11). 10) and the channel forming regions (5) and (10)
And source regions (6) and (9) and drain regions (7) and (8) formed so as to sandwich them.

The insulating substrate (1) is made of, for example, a heat-resistant material, for example, molybdenum.

The gate insulating film (11) is made of, for example, silicon by a CVD method.
It is provided with a thickness of 0.1 μm to 0.5 μm.

Next, an amorphous semiconductor is formed on the upper surface of the gate insulating film (11), and channel formation regions (5) and (10) are formed by selective etching at corresponding positions on the gate electrodes (3) and (13). It is formed.

Further, the N-channel insulated gate field effect semiconductor device (12) has a source region (6) composed of an N-type semiconductor layer,
A drain region (7) is selectively formed using a photo-etching method. The P-channel insulated-gate field-effect semiconductor device (2) is formed, for example, by forming an aluminum film by a vacuum deposition method and then performing selective etching to form a source region (9) and a drain region (8). Shown in the figure
The C / MOS FET has been completed.

Further, a semi-amorphous silicon semiconductor having microcrystallinity of 5 to 200 mm provided on an insulating substrate is disclosed in the following document of the present applicant. For example, Japanese Patent Application No. 55-120322, Japanese Patent Application Laid-Open No. 55-151329, Japanese Patent Application No. 56-65826, Appl. Phys. Lett. 38 [3] p.
81-2-1).

When a semi-amorphous semiconductor gives light energy whose electric-photoconductivity is AMI (100 mw / cm ² ),
1 × 10 ⁻³ (Ωcm) ⁻¹ to 8 × 10 ⁻² (Ωcm) ⁻¹ ,
It has been experimentally found that these values have extremely excellent characteristics of 1/2 to 1/10 that of a single crystal silicon semiconductor.

[Problems to be solved by the invention]

In the insulated gate field effect semiconductor device shown in FIG. 1, the gate insulating film (11) is formed by the CVD method, so that the gate insulating film (11) does not have a high density. As a result, the gate electrode (3) and the channel forming region (5) are not formed. But it is easy to short. Therefore, the gate insulating film (1) of the conventional insulated gate type field effect semiconductor device is
In 1), the thickness had to be increased to 0.3 μm or more.

As a result, a gate voltage for driving the insulated gate field-effect semiconductor device needs to be as high as 20 V to 60 V, and it has been impossible to set a so-called low voltage of about 1.5 V to 5 V.

In addition, the insulated gate field effect semiconductor device has both ends of the gate electrode (15) and both ends of the channel formation region (5),
It is necessary to precisely align one end of the source region (6) and one end of the drain region (7).

However, when there is unevenness on the insulating substrate (1), 1 μm
The above high-precision positioning was impossible.

As a result, a tolerance of 20 μm to 30 μm has been created for positioning the insulated gate field effect semiconductor device in the conventional example. Therefore, the drain voltage in the insulated gate field effect semiconductor device is 50 V to 7
Since the voltage becomes as high as 0 V, it was impossible to perform low-voltage driving of about 1.5 V to 10 V.

Further, on a surface (17) in contact with a so-called channel forming region (5) having structure sensitivity, a semiconductor doped with a large amount of P-type or N-type conductivity type impurities as much as 0.5% to 2% is adhered. I have. Therefore, unless the semiconductor containing the impurity is completely removed by etching on the surface (17) of the channel forming region (5), the source region (6) and the drain region (7) are short-circuited at this portion.

However, since the semiconductor containing the impurity has the same main component as that of the channel forming region (5) under the semiconductor, selective etching is extremely difficult.

1, the gate electrode (3), the source region (6) and the drain region (7) are made of different materials, and are formed on the insulating substrate (1). If a lead wiring is to be made of a metal having a low resistance, a further photomask is required on the upper surface, and there is a disadvantage that only a single-layer wiring can be formed despite a total of six times.

A semi-amorphous semiconductor, when applied to a conventionally known thin-film insulated gate field-effect semiconductor device, that is, a structure having a longitudinal section shown in FIG. Satisfactory characteristics could not be obtained.

An object of the present invention is to solve the above-described problems, and an object of the present invention is to provide an insulated gate field effect semiconductor device in which a gate insulating film can be thinned and driven at a low voltage.

[Means for solving the problem]

In order to achieve the above object, the present applicant uses a semi-amorphous silicon semiconductor having microcrystallinity of 5 ° to 200 ° provided on an insulating substrate for a channel formation region under a gate electrode, It has also been found that a thin-film insulated gate field-effect semiconductor device has the same characteristics as a single crystal semiconductor.

That is, the insulated gate type field effect semiconductor device of the present invention comprises a substrate (1) having a flat insulating surface, and 0.01 mol of a halogen element such as hydrogen or fluorine for neutralizing a recombination center on the substrate (1). A channel forming region (19) formed by forming a semi-amorphous semiconductor (20) having an intrinsic or substantially intrinsic conductivity type having microcrystallinity added in an amount of from 5% to 5% by mole, and the semi-amorphous semiconductor ( 20) A gate insulating film made of silicon oxide or silicon nitride having a thickness of 300 to 2000 mm in close contact with the gate insulating film (33)
A gate electrode (35) formed on the gate insulating film (33) and a pair of high-concentration adjacent to the semi-amorphous semiconductor (20) with the gate insulating film (33) interposed therebetween. Other than the source region (29) and the drain region (30) made of the added impurity region, and the gate insulating film (33), the source region (29) and the drain region (30) in contact with the semi-amorphous semiconductor (20). And an insulating film (31) covering a portion of the gate electrode.
It operates by applying a driving voltage of 10V.

[Action]

The present invention provides a semiconductor device having a thickness of 300 to 2000 mm, which is one digit thinner than the conventional example, on a channel forming region made of semi-amorphous.
And a source region and a drain region composed of a pair of heavily doped impurity regions sandwiching the gate insulating film.

Therefore, the channel formation region made of semi-amorphous and the source region and the drain region made of the impurity region added at a high concentration have higher electric conductivity than the conventional one.

That is, in the insulated gate type field effect semiconductor device, the channel formation region is made semi-amorphous, or the source region and the drain region are doped with a higher concentration of impurities, so that the voltage is 1.5 V higher than that of the conventional device.
The current in the channel forming region is made easier to flow at a gate voltage as low as 10 V or 10 V.

As a result, the gate insulation of the insulated gate field effect semiconductor device can be made thinner by the reduced gate voltage. In particular, since the channel formation region is a semi-amorphous semiconductor, carrier mobility is also 10 ² to 10 ⁴
It was twice as fast.

As a result, an operating frequency of 10 KHz or higher could not be expected, but in the present invention, operation at a high frequency of 1 MHz or higher was enabled.

In particular, a P-channel insulated gate field effect semiconductor device can be manufactured by forming a channel formation region of an intrinsic or substantially intrinsic conductive semi-amorphous semiconductor.

In particular, when only the conventional amorphous silicon was used for the channel formation region, only an N-channel TFT could be formed, but the present invention has made it possible for the first time to form a C / TFT (complementary).

As a result, there are many effects such as energy saving, high-speed operation, and being able to be mounted on the same substrate as a peripheral circuit of a liquid crystal display.

In addition, according to the present invention, the gate insulating film can be made one digit thinner than the conventional one, so that the insulated gate field effect semiconductor device can be driven by a lower voltage than the conventional one.

In addition, the present invention provides a semi-amorphous semiconductor formed by a plasma CVD method on a substrate that makes ohmic contact with a substrate, particularly a substrate that does not react with the semiconductor on the upper surface thereof, for example, a glass or ceramic substrate or a conductive substrate. The characteristics of semiconductors have been positively used in insulated gate field effect semiconductor devices.

Further, in the present invention, a semi-amorphous semiconductor is used for a channel formation region, and the lower side, the upper side, and all the side portions are covered with an insulator or a semiconductor having a high impurity concentration.
The gate electrode can be controlled by utilizing the structure sensitivity as a semiconductor.

For this reason, the driving voltage is not limited to the conventional 40V to 80V, but both the gate voltage and the drain voltage are 5V to 10V.
, And it is possible to set the voltage to 1.5V.

In addition to the above effects, the present invention can be easily integrated as a semiconductor device, and can be easily integrated with other important elements such as a resistor and a capacitor.

Further, the present invention is advantageous in that a channel formation region is made of a semi-amorphous semiconductor and also when it is manufactured as a device.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. FIG. 2 is a longitudinal sectional view showing a manufacturing process of the insulated gate field effect semiconductor device of the present invention.

In FIG. 2 (A), a substrate (1) is made of glass which is an insulating and translucent substrate or stainless steel which is a conductive substrate, on which a semi-amorphous semiconductor (20) is 0.1 μm thick. It was formed by a plasma gas phase method to a thickness of 1 to 1 μm.

This semi-amorphous semiconductor (20) is obtained by diluting silane (monosilane or polysilane) or silicon fluoride with helium or hydrogen, introducing the diluted solution into a reactor having a pressure of 0.01 to 10 torr, for example, 0.3 torr, and then heating it to a temperature of 10 to 400 ° C., for example, 300 to 300. Direct current, high frequency (500 KHZ to 50 MHZ, for example, 13.56 MHZ) is applied to the reactive gas on the substrate (1) heated to
Z) or microwave (1GHZ to 10GHZ, eg 2.45
GHZ) magnetic field energy of 20 W to 200 W is applied to perform glow discharge or arc discharge, and these reactive gases and carrier gas are converted into plasma, decomposed and reacted, and microcrystallinity is formed on the substrate (1). To form an intrinsic or substantially intrinsic semi-amorphous semiconductor (20).

This semi-amorphous semiconductor (20) has a crystallinity in the order of 5 to 200 mm in the short-range order as determined by an X-ray analysis image, as well as hydrogen and fluorine that neutralize dangling bonds of silicon. 0.01 mol% to 5 mol% is added to the recombination center neutralizing agent by the halogen element.

Furthermore, unpaired bonds of this semi-amorphous semiconductor (20) that cannot be offset by these neutralizing agents are 10 ¹³ cm ^-3 to 10
^To neutralize to a concentration of ¹⁵ cm ^-3, an alkali metal such as lithium, sodium or calcium may be at a concentration of 10 ¹⁴ cm ^-3 to 10 ¹⁷ cm ^-3 .

This semi-amorphous semiconductor (20) has a dark conductivity of 1 ×
10 ⁻⁵ (Ωcm) ⁻¹ to 3 × 10 ⁻³ (Ωcm) ⁻¹ , and 10 ⁻⁹ (Ωcm) ⁻¹ to 10 ⁻⁶ (Ωcm) ^{−1 of} amorphous semiconductor
10 ² to 10 ⁴ times larger than 1 × 10 ^-3 (Ωcm) ^-1 to 8 × 10 ^-2 (Ωcm) under the condition that the photoconductivity is AM1
^-1 experimentally, especially 10 ^-6 (Ω
cm) ^-1 to 3 × 10 ^-4 (Ωcm) ^-10 to 10 ³ compared to ^-1
Twice as large.

Therefore, the electron mobility flowing semi-amorphous semiconductor (20) is also the mobility of holes is also larger 10 ⁴ times to 10 ^{2 to} amorphous semiconductor, the semi-amorphous semiconductor (20) an insulated gate field effect semiconductor device Use as a semiconductor for a channel formation region is extremely important for manufacturing a semiconductor device for high-speed response.

In FIG. 2A, a mask (21) is selectively formed to a thickness of 1 μm to 5 μm, and a first photomask is used here. This may be silicon oxide or a polyimide resin film (PIQ) which is a heat-resistant organic resin by a low pressure plasma gas phase method.

In FIG. 2, the region (22) of the insulated gate field effect semiconductor device includes a source region (26) and a drain region (2).
7) and a channel forming region (24).

Thereafter, a semiconductor layer (25) of an amorphous semiconductor or a semi-amorphous semiconductor was formed on this upper surface again in a thickness of 0.1 μm to 1 μm in the same manner as the semi-amorphous semiconductor (20).

At this time, in order to form an N-channel or P-channel insulated gate field effect semiconductor device, phosphorus, which is a pentavalent impurity, and boron, which is a trivalent impurity, are added to each of the N-type or P-type semiconductor layers. % To 2%. Thus, a coating structure shown in FIG. 2 (A) was obtained.

FIG. 2 (B) shows a mask (2) in the structure of FIG. 2 (A).
1) was slightly immersed in an etching solution by applying ultrasonic waves to elute. Then, a pair of the source region (26) and the drain region (27) is formed, and the semiconductor layers (29) and (30) of one conductivity type are formed as a source and a drain. Further, a field insulating film (31) is formed on the upper surface with a silicon oxide or polyimide resin film to a thickness of 0.1 μm to 1 μm to form a second
Figure (B) is obtained.

Next, the field insulating film (3) of the portion corresponding to the channel formation region (24) and the opening (32) for the electrode contact is formed.
1) was selectively removed by a second photomask.

Thereafter, the gate insulating film (33) was formed to a thickness of 300 to 2000 mm by a plasma oxidation method. That is, oxygen or oxidizing gas is converted to 2.45 GHZ (output 100 W to 5
The substrate is placed at a temperature of 300 ° C. to 500 ° C. in the activated oxidizing gas, and an oxide, particularly a semi-amorphous semiconductor (20), is made of silicon on the surface of the substrate. When there was, a silicon oxide film was formed.

Instead of the oxidizing gas, a nitriding gas such as ammonia may be used. Of course, an insulating film of silicon oxide, silicon nitride, or the like may be formed to a thickness of 300 to 2000 mm by a plasma vapor method.

Further, in order to form a non-volatile memory, it is effective to form a cluster or thin film of a semiconductor or a metal in the gate insulating film and use it as a charge trapping center.

Also, an MNOS structure may be used. There is a degree of freedom determined by applying these insulated gate field effect semiconductor devices.

Thus, after the opening (32) is provided in the source region (29) or the drain region (30) by the third photomask having the gate insulating film (33) formed thereon, the gate electrode (35) and the drain electrode (34) A lead (36) was formed by selectively using a metal film with a fourth photomask.

For these electrodes and lead wires, it is effective to use a vacuum deposition method of aluminum or the like and a photo etching method.

In order to prevent such metals from seeping into the underlying insulating film or semiconductor layer for reliability, a method combining a lift-off method and an electroless plating method was preferred.

That is, in FIG. 2D, the gate electrode (3
5), a mask resist is provided on a portion where the lead (36) is not provided in the same manner as in FIG. 2 (A), and only the metal is selectively removed and removed on this upper surface and the entire solar cell. is there.

As described above, an insulated gate field effect semiconductor device having the structure of the vertical cross section shown in FIG. 2D was obtained. At this time, the pair of impurity regions functions as a source region (29) and a drain region (30), and the channel formation region (1
9) has a channel length of 0.3 μm to 20 μm, particularly 2 μm.
μm to 3 μm, and a frequency response as high as 10 ³ to 10 ⁶ times higher than that of the structure of FIG. 1 using a conventional amorphous semiconductor could be obtained.

In addition, the drive voltage is 1.5V to 10V, typically 5V
Or 10V, and could be reduced to 1/2 or 1/5 of the conventional level.

As apparent from FIG. 2, the channel forming region (19)
Is covered with a gate insulating film (33), and is formed on a thin substrate (1) having a lower electrode. In particular, the channel formation region (19) is covered with an insulating film or a semiconductor on all surfaces, and does not deteriorate due to exposure to the air.

In the present invention, the semi-amorphous semiconductor is
A material that is extremely structurally sensitive compared to amorphous semiconductors, and that does not react with semi-amorphous semiconductors such as flat glass substrates, rather than having any convex parts on the substrate, especially metal electrodes. Is formed on.

In addition, a semiconductor layer (25) to which an impurity is added is stacked on the channel forming region made of the semi-amorphous semiconductor, and there is no problem that the impurity is doped and a leak does not occur. Have.

Although the present invention has shown only one insulated gate type field effect semiconductor device, it is easy to provide a plurality of insulated gate type field effect semiconductor devices on the same substrate, and furthermore, the lead (36) It is also easy to provide an interlayer insulator thereon and to arrange the second leads in a multilayer arrangement.

When the substrate (1) is made of translucent glass, light can be emitted from the lower layer to function as a phototransistor for detecting the presence or absence of the light. In addition, the phototransistor can be used as an imaging semiconductor device by being integrated.

Although the present invention has been described with a focus on silicon, SiC ₁₆ (0 <X
<1), Si ₃ N _4-X (1 <X <4), or germanium or a 3- to 5-valent compound.

〔The invention's effect〕

According to the present invention, the channel forming region in the insulated gate field effect semiconductor device is made of a semi-amorphous semiconductor, and the source region and the drain region are doped with high concentration impurities, so that the source region, the channel forming region,
In addition, the mobility of electrons and holes in the drain region is large, and the channel formation region and the gate insulating film are not short-circuited even if the gate insulating film is thinned by one digit compared to the related art.

Therefore, the insulated gate type field effect semiconductor device of the present invention has a gate insulating film which is one digit thinner than the conventional one, so that the gate insulating film is 1.5 V or less.
It has become possible to drive at a low voltage of 10V. Further, since the mobility of electrons and holes is large, the response speed of the insulated gate field effect semiconductor device is increased.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a conventional semiconductor device. FIG. 2 is a longitudinal sectional view showing a manufacturing process of the insulated gate field effect semiconductor device of the present invention. 1 ... substrate 19 (24) ... channel formation region 20 ... semi-amorphous semiconductor 21 ... mask 22 ... region of insulated gate field effect semiconductor device 25 ... semiconductor layer 26 (29) ... source region 27 ( 30) Drain region 31 Field insulating film 32 Hole 33 Gate insulating film 34 Electrode 35 Gate electrode 36 Lead

Claims (1)

(57) [Claims] 1. A substrate having a flat insulating surface, and microcrystallinity wherein 0.01 mol% to 5 mol% of a halogen element such as hydrogen or fluorine is added on the substrate for neutralizing a recombination center. A channel forming region formed by forming a semi-amorphous semiconductor having an intrinsic or substantially intrinsic conductivity type; and
A gate insulating film made of silicon oxide or silicon nitride having a thickness of 000 mm; a gate electrode formed on the gate insulating film; and a pair of adjacent semi-amorphous semiconductors sandwiching the gate insulating film. A source region and a drain region formed of a highly doped impurity region; a gate insulating film in contact with the semi-amorphous semiconductor; and an insulating film covering a portion other than the source region and the drain region. An insulated gate field effect semiconductor device, which operates by applying a driving voltage of 1.5 V to 10 V to the device.