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JP2509592B2 - Stacked solid-state imaging device - Google Patents

Stacked solid-state imaging device

Info

Publication number
JP2509592B2
JP2509592B2 JP61308282A JP30828286A JP2509592B2 JP 2509592 B2 JP2509592 B2 JP 2509592B2 JP 61308282 A JP61308282 A JP 61308282A JP 30828286 A JP30828286 A JP 30828286A JP 2509592 B2 JP2509592 B2 JP 2509592B2
Authority
JP
Japan
Prior art keywords
pixel
electrode
imaging device
state imaging
solid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61308282A
Other languages
Japanese (ja)
Other versions
JPS63164270A (en
Inventor
良平 宮川
誠之 松長
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP61308282A priority Critical patent/JP2509592B2/en
Publication of JPS63164270A publication Critical patent/JPS63164270A/en
Application granted granted Critical
Publication of JP2509592B2 publication Critical patent/JP2509592B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/191Photoconductor image sensors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80Constructional details of image sensors
    • H10F39/803Pixels having integrated switching, control, storage or amplification elements

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、固体撮像素子チップに光導体膜を積層して
構成される積層型固体撮像装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a stacked solid-state imaging device configured by stacking a photoconductor film on a solid-state imaging device chip.

(従来の技術) 固体撮像素子チップに光導電体膜を積層した2階建て
構造の固体撮像装置は、感光部の開口面積を広くするこ
とができるため、高感度且つ低スミアという優れた特性
を有する。このためこの固体撮像装置は各種監視用TVや
高品位TVなどのカメラとして有望視されている。この種
の固体撮像装置の光電変換部は画素電極の配列の上に光
導電体膜を積層し、その上全面に透光性のある材料によ
り透明電極を形成するという構造となっている。したが
って各画素の感光部の領域を決定しているのは画素電極
の面積である。ところが透明電極と光導電体膜は画素電
極の配列をおおう様に全面に形成されているため、画素
電極の配列の外側に入射した光によって生成された電荷
担体の一部が、端部の画素電極上部より外側に広がって
いる光導電体膜中の電界によって走向し端部の画素電極
に流れ込む。従って画素の配列の端部の画素の感光部の
領域は他の部分の画素に比べて実質的に大きくなる。こ
れは画像で考えると画像の端部が明るくなってしまう。
また特に入射光の照度の大きな場合には画素電極の配列
の外側に発生した多量の電荷担体が画素配列の端部の数
画素の画素電極に流れ込む事によりブルーミングを生じ
る。従って画素配列の端部の数画素からの出力信号を映
像信号として用いる事が出来ない。
(Prior Art) A solid-state image pickup device having a two-story structure in which a photoconductor film is laminated on a solid-state image pickup element chip can widen the opening area of the photosensitive portion, and therefore has excellent characteristics of high sensitivity and low smear. Have. For this reason, this solid-state imaging device is regarded as a promising camera for various surveillance TVs and high-definition TVs. The photoelectric conversion unit of this type of solid-state imaging device has a structure in which a photoconductor film is laminated on an array of pixel electrodes, and a transparent electrode is formed on the entire surface of the photoconductor film with a light-transmitting material. Therefore, it is the area of the pixel electrode that determines the photosensitive area of each pixel. However, since the transparent electrode and the photoconductive film are formed on the entire surface so as to cover the array of pixel electrodes, a part of the charge carriers generated by the light incident on the outside of the array of pixel electrodes may be part of the pixel at the edge. The electric field in the photoconductive film spreading outward from the upper part of the electrode strikes and flows into the pixel electrode at the end. Therefore, the area of the photosensitive portion of the pixel at the end of the pixel array is substantially larger than that of the pixels in other portions. Considering this as an image, the edge of the image becomes bright.
In particular, when the illuminance of incident light is high, a large amount of charge carriers generated outside the array of pixel electrodes flow into the pixel electrodes of several pixels at the end of the pixel array, which causes blooming. Therefore, the output signals from several pixels at the end of the pixel array cannot be used as a video signal.

(発明が解決しようとする問題点) 以上述べてきたように従来の積層型固体撮像装置で
は、画素配列の外側で発生した電荷担体が画素配列の端
部に流れ込むために画素配列の端部の数画素からの出力
信号を映像信号として用いる事ができないという欠点が
あった。本発明は、上記の点に鑑み、端部の画素からの
出力信号を有効に映像信号として利用する積層型固体撮
像装置を提供する事を目的とする。
(Problems to be Solved by the Invention) As described above, in the conventional stacked-type solid-state imaging device, charge carriers generated outside the pixel array flow into the edge part of the pixel array, so There is a drawback that output signals from several pixels cannot be used as video signals. In view of the above points, an object of the present invention is to provide a stacked solid-state imaging device that effectively uses an output signal from a pixel at an end as a video signal.

〔発明の構成〕[Structure of Invention]

(問題点を解決するための手段) 本発明による積層型固体撮像装置は撮像素子チップ上
の画素配列の端部の画素の画素電極に隣接してダミー電
極を形成した事を特徴とする。このダミー電極には直接
あるいは半導体基板に形成されたドレイン部を通して、
一定の電圧が印加される。
(Means for Solving the Problems) The stacked solid-state imaging device according to the present invention is characterized in that the dummy electrode is formed adjacent to the pixel electrode of the pixel at the end of the pixel array on the imaging element chip. This dummy electrode, directly or through the drain portion formed on the semiconductor substrate,
A constant voltage is applied.

(作用) 積層型固体撮像装置では画素電極の配列上を光導電膜
及び透明電極が画素電極をおおっているために、画素配
列の端部の画素の感光部領域が他の部分の画素に比べて
大きくなる。この端部の画素の画素電極に隣接してダミ
ー電極を形成し、このダミー電極に画素電極に印加され
る電圧と同程度の電圧を印加する事で、この端部の画素
の感光部領域が実質的に大きくなる効果を消失させる事
ができる。すなわちダミー電極がない場合には画素配列
の外側に入射した光が吸収されて、生成した電荷担体の
一部が画素配列の端部の画素の画素電極に流れ込むがダ
ミー電極を形成してダミー電極と透明電極間に適当な電
圧を印加する事で、この画素配列の外側に生成した電荷
担体をダミー電極に流し込み、画素電極に流れ込む事を
防ぐ事ができる。従って、端部の画素電極に余計な電荷
担体が流れ込む事がなくなるために端部の画素でも他の
部分の画素と同じ一定の光感度が得られる。
(Function) Since the photoconductive film and the transparent electrode cover the pixel electrodes on the array of pixel electrodes in the stacked type solid-state imaging device, the photosensitive area of the pixel at the end of the pixel array is larger than that of the pixel in other areas. Grows. By forming a dummy electrode adjacent to the pixel electrode of the pixel at this end and applying a voltage similar to the voltage applied to the pixel electrode to this dummy electrode, the photosensitive region of the pixel at this end is It is possible to eliminate the effect of substantially increasing. That is, when there is no dummy electrode, the light incident on the outside of the pixel array is absorbed and a part of the generated charge carriers flows into the pixel electrode of the pixel at the end of the pixel array. By applying an appropriate voltage between the transparent electrode and the transparent electrode, it is possible to prevent the charge carriers generated outside the pixel array from flowing into the dummy electrode and from flowing into the pixel electrode. Therefore, since unnecessary charge carriers do not flow into the pixel electrodes at the ends, the pixels at the ends can have the same constant photosensitivity as the pixels at other parts.

また画素配列の端部でのブルーミングも抑制できる。 In addition, blooming at the edge of the pixel array can be suppressed.

(実施例) 以下、本発明の実施例を図面を参照して詳細に説明す
る。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図は一実施例による積層型固体撮像装置の画素配
列の端部の2画素を含む部分の断面構造である。p+型Si
基板11にpウエル12が形成されたウェーハを用いて、イ
ンターライン転送型CCD撮像素子チップ1が構成されて
いる。即ち信号電荷を蓄積する蓄積ダイオード13がマト
リクス状に形成され、蓄積ダイオード13の列に隣接して
n+型の埋め込みチャンネルCCDからなる垂直CCD14が形成
されている。15はチャンネルストッパとしてのp+型層で
あり、これにより分離されて同様の構成の蓄積ダイオー
ド列と垂直CCDの組が繰り返し配列形成される。161,162
は垂直CCD14の転送ゲート電極であり、その一部は蓄積
ダイオード13からCCDチャンネルへの電荷転送ゲート電
極を兼ねている。転送ゲート電極161,162が形成された
基板上は層間絶縁膜181,182に覆われ、且つ蓄積ダイオ
ード13に接続される多結晶シリコン電極17が形成され
て、平担化されている。第1の層間絶縁膜181は例えばC
VD法により形成されるSiO2膜であり、第2の層間絶縁膜
182は例えばプラズマCVD法により形成されるBPSG膜であ
る。この構造は、第1の層間絶縁膜181に開口形成後、
多結晶シリコン膜電極17を各蓄積ダイオード13上に形成
した後、BPSG膜182を被着してこれを溶融し、反応性イ
オンエッチング法でBPSG膜をエッチングして多結晶シリ
コン電極17の表面を露出させることで得られる。
FIG. 1 is a sectional structure of a portion including two pixels at an end portion of a pixel array of a stacked solid-state imaging device according to an embodiment. p + type Si
The interline transfer CCD image pickup device chip 1 is constructed by using a wafer in which the p-well 12 is formed on the substrate 11. That is, the storage diodes 13 that store the signal charges are formed in a matrix and adjacent to the column of the storage diodes 13.
A vertical CCD 14 composed of an n + type buried channel CCD is formed. Reference numeral 15 denotes a p + -type layer as a channel stopper, which is separated and a set of storage diode rows and vertical CCDs having the same structure is repeatedly arranged. 16 1, 16 2
Is a transfer gate electrode of the vertical CCD 14, and a part thereof also serves as a charge transfer gate electrode from the storage diode 13 to the CCD channel. The substrate on which the transfer gate electrodes 16 1 and 16 2 are formed is covered with the interlayer insulating films 18 1 and 18 2 and the polycrystalline silicon electrode 17 connected to the storage diode 13 is formed and flattened. There is. The first interlayer insulating film 18 1 is, for example, C
A second interlayer insulating film, which is a SiO 2 film formed by the VD method
18 2 is, for example, a BPSG film formed by the plasma CVD method. In this structure, after forming an opening in the first interlayer insulating film 18 1 ,
After the polycrystalline silicon film electrode 17 is formed on each storage diode 13, the BPSG film 18 2 is deposited and melted, and the BPSG film is etched by the reactive ion etching method to form the surface of the polycrystalline silicon electrode 17. It is obtained by exposing.

このように表面が平担化されたCCD撮像素子チップ1
上に各多結晶シリコン電極17に接続される画素電極19と
ダミー電極20が形成されている。ダミー電極は端部の画
素電極19に隣接して、垂直方向に垂直CCD14と平行して
伸びている。画素電極19とダミー電極20はスパッター法
によりCrを1000Å程度被着し、反応性イオンエッチング
法によりエッチングして所定の形状に形成される。ダミ
ー電極20と端部の画素電極19の距離aは各画素電極19の
間の距離bが等しくなるように形成されている。
CCD image sensor chip 1 with a flat surface in this way
A pixel electrode 19 and a dummy electrode 20 connected to each polycrystalline silicon electrode 17 are formed on the top. The dummy electrode is adjacent to the pixel electrode 19 at the end and extends in the vertical direction in parallel with the vertical CCD 14. The pixel electrode 19 and the dummy electrode 20 are formed into a predetermined shape by depositing Cr by about 1000Å by a sputtering method and etching by a reactive ion etching method. The distance a between the dummy electrode 20 and the pixel electrode 19 at the end is formed so that the distance b between the pixel electrodes 19 is equal.

こうして画素電極19及びダミー電極20が形成されたチ
ップ基板上に光導電体膜2が積層形成されている。光導
電体膜2は、正孔注入阻止層としてのi型のa-SiC:H
(水素化アモルファスシリコン・カーバイド)膜21、主
として光電変換が行なわれる高抵抗のa-Si:H膜22、およ
び電子注入阻止層となるp型a-SiC:H膜23の3層構造か
らなる。これらの膜はSiH4ガスを主成分とするガスのグ
ロー放電分解法により形成される。a-SiC:H膜21は室温
での暗導電率σ〜10-14(Ωcm)-1で厚さは100Å程度
とする。高抵抗a-Si:H膜22はσ〜10-12(Ωcm)-1
光電変換に必要な十分な厚さとする。可視光に十分な光
感度を持つためには0.5μm以上の膜厚が必要である。
p型a-SiC:H膜23は約200Å程度とする。この様に形成さ
れた光導電体膜2上に透明電極24が例えばITO(Indium
Tin Oxide)により形成されている。第1図には示して
いないがダミー電極20上の光導電体膜2及び透明電極24
の一部がエッチングにより除去されダミー電極露出部を
通して外部よりダミー電極20に所望の電圧が印加され
る。
Thus, the photoconductor film 2 is laminated on the chip substrate on which the pixel electrode 19 and the dummy electrode 20 are formed. The photoconductor film 2 is an i-type a-SiC: H as a hole injection blocking layer.
(Hydrogenated amorphous silicon carbide) film 21, mainly consisting of a high resistance a-Si: H film 22 that undergoes photoelectric conversion, and a p-type a-SiC: H film 23 that serves as an electron injection blocking layer. . These films are formed by the glow discharge decomposition method of a gas containing SiH 4 gas as a main component. The a-SiC: H film 21 has a dark conductivity σ D -10 −14 (Ωcm) −1 at room temperature and a thickness of about 100 Å. The high-resistance a-Si: H film 22 has σ D ˜10 −12 (Ωcm) −1 and has a sufficient thickness necessary for photoelectric conversion. To have sufficient photosensitivity to visible light, a film thickness of 0.5 μm or more is required.
The p-type a-SiC: H film 23 has a thickness of about 200Å. The transparent electrode 24 is formed on the photoconductive film 2 thus formed, for example, by ITO (Indium).
Tin Oxide). Although not shown in FIG. 1, the photoconductor film 2 and the transparent electrode 24 on the dummy electrode 20.
Is partially removed by etching, and a desired voltage is applied to the dummy electrode 20 from the outside through the exposed portion of the dummy electrode.

この実施例の撮像装置の光感度の測定を行った。CCD
撮像素子チップは20万画素、2/3吋サイズのものであ
る。撮像装置の受光面の照度が1.5ルクスとなるように
白色光を入射した。光導電体膜2で光電変換され蓄積ダ
イオード13に蓄積された電荷担体は転送ゲート161に印
加される読み出しパルス電圧によって垂直CCD14に移さ
れる。従って蓄積ダイオード13と電気的につながってい
る画素電極19の電位は転送ゲート161に印加される読み
出しパルス電圧の電位に等しくなる。この読み出しパル
スを+5Vに、透明電極24をグランドにシヨートして測定
した。従って画素電極20と透明電極24の間に印加された
電圧は5Vである。次表にダミー電極20に画素電極19と等
しい5Vの電圧を加えた場合の光感度の測定の結果を次表
に示す。結果は端部の画素からの出力電圧V1を端部から
10画素めの画素の信号電圧V2で割り算して示した。
The optical sensitivity of the image pickup apparatus of this example was measured. CCD
The image sensor chip is a 200,000 pixel, 2/3 inch size. White light was made incident so that the illuminance on the light receiving surface of the image pickup device was 1.5 lux. The charge carriers photoelectrically converted in the photoconductor film 2 and stored in the storage diode 13 are transferred to the vertical CCD 14 by the read pulse voltage applied to the transfer gate 16 1 . Therefore, the potential of the pixel electrode 19 electrically connected to the storage diode 13 becomes equal to the potential of the read pulse voltage applied to the transfer gate 16 1 . This read pulse was measured at + 5V and the transparent electrode 24 was grounded. Therefore, the voltage applied between the pixel electrode 20 and the transparent electrode 24 is 5V. The following table shows the result of measurement of photosensitivity when a voltage of 5 V, which is equal to that of the pixel electrode 19, is applied to the dummy electrode 20. The result is that the output voltage V 1 from the pixel at the edge is
It is shown by dividing by the signal voltage V 2 of the 10th pixel.

またダミー電極のない従来の積層型固体撮像装置の場
合の結果を参考のためあわせて示した。この積層型固体
撮像装置はダミー電極を形成していない点以外は実施例
とまったく同じ構造の積層型固体撮像装置である。ダミ
ー電極のない従来例では端部の画素の信号電圧が他の画
素に比べて大きくなっている事がわかる。これは端部の
画素電極19の外側の領域Aに入射して生成した電子が端
部の隣接する画素電極19に流れ込むためである。ダミー
電極を設けた実施例の場合ではダミー電極20と透明電極
24の間にある垂直方向の電界によって領域Aで生成した
電子がダミー電極20に流れ込み、余計な電子が端部の画
素電極19に流れ込む事が防がれる。従って端部の画素の
出力信号電圧が他の部分の画素と等しくなる事がわか
る。また強い光を入射した場合に画素配列の端部でのブ
ルーミングが抑制される事を確認した。
In addition, the results in the case of the conventional stacked type solid-state imaging device having no dummy electrode are also shown for reference. This laminated solid-state imaging device has the same structure as that of the embodiment except that no dummy electrode is formed. It can be seen that in the conventional example having no dummy electrode, the signal voltage of the pixel at the end is higher than that of the other pixels. This is because the electrons generated by entering the area A outside the pixel electrode 19 at the end flow into the adjacent pixel electrode 19 at the end. In the case of the embodiment in which the dummy electrode is provided, the dummy electrode 20 and the transparent electrode
It is possible to prevent electrons generated in the region A from flowing into the dummy electrode 20 due to the vertical electric field between 24, and unnecessary electrons from flowing into the pixel electrode 19 at the end. Therefore, it can be seen that the output signal voltage of the pixel at the end portion becomes equal to that of the pixels at other portions. It was also confirmed that blooming at the edge of the pixel array was suppressed when strong light was incident.

以上の結果から明らかなように、画素配列の端部の画
素に隣接したダミー電極を形成した積層型固体撮像装置
では、画素配列の端部の画素からの出力信号を有効に映
像信号として利用する事ができる。
As is clear from the above results, in the stacked solid-state imaging device in which the dummy electrode adjacent to the pixel at the end of the pixel array is formed, the output signal from the pixel at the end of the pixel array is effectively used as the video signal. I can do things.

第2図は他の実施例の積層型固体撮像装置である。第
1図と対応する部分には第1図と同一符号を付して詳細
な説明は省略する。第1図と異なる点はSiウエハのpウ
エルにn+型層のドレイン部26を形成しこのドレイン部26
上にダミー電極20と電気的につながる多結晶シリコン電
極25を形成した事である。この実施例ではダミー電極20
の電位をドレイン部26に印加する電圧により第1図と同
じく制御するものであり、先の実施例と同様な効果が得
られる。
FIG. 2 shows a laminated solid-state image pickup device according to another embodiment. The parts corresponding to those in FIG. 1 are designated by the same reference numerals as those in FIG. 1 and their detailed description is omitted. The difference from FIG. 1 is that the drain portion 26 of the n + type layer is formed in the p well of the Si wafer and the drain portion 26 is formed.
That is, the polycrystalline silicon electrode 25 electrically connected to the dummy electrode 20 is formed thereon. In this embodiment, the dummy electrode 20
The potential is controlled by the voltage applied to the drain portion 26 in the same manner as in FIG. 1, and the same effect as in the previous embodiment can be obtained.

なお実施例では、CCD撮像素子を用いたが、MOS型やBB
D型撮像素子チップを電荷転送部として用い、これに光
導体膜を積層する積層型固体撮像装置の場合にも、本発
明を同様に適用する事ができる。
Although the CCD image sensor is used in the embodiment, the MOS type or BB
The present invention can be similarly applied to a stacked solid-state imaging device in which a D-type imaging element chip is used as a charge transfer section and a photoconductor film is stacked on the charge transfer section.

〔発明の効果〕〔The invention's effect〕

以上述べたように本発明によれば画素配列の端部の画
素の画素電極に隣接してダミー電極を設け、このダミー
電極の電位を制御する事で、端部の画素でも一様な光感
度が得られ、端部の画素の出力信号をも有効に利用する
積層型固体撮像装置が得られる。
As described above, according to the present invention, the dummy electrode is provided adjacent to the pixel electrode of the pixel at the end of the pixel array, and the potential of this dummy electrode is controlled, so that even the pixel at the end has uniform photosensitivity. Thus, a stacked solid-state imaging device that effectively utilizes the output signals of the pixels at the end portions can be obtained.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例の積層型固体撮像装置を示す
図、第2図は他の実施例の積層型固体撮像装置を示す図
である。図において、 1……CCD撮像素子チップ、2……光導電体膜、11……p
+型Si基板、12……pウエル、13……蓄積ダイオード、1
4……垂直CCD、15……p+型層、161,162……転送ゲー
ト、17……n+型多結晶シリコン電極、181,182……層間
絶縁膜、19……画素電極、20……ダミー電極、21……i
型a-SiC:H膜、22……i型a-Si:H膜、23……p型a-SiC:H
膜、24……透明電極、25……n+型多結晶シリコン電極、
26……n+型ドレイン部、27……入射光、a……端部の画
素電極19とダミー電極20の間の距離、b……各画素電極
19の間の距離、A……画素配列の外側の領域。
FIG. 1 is a diagram showing a laminated solid-state imaging device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a laminated solid-state imaging device according to another embodiment. In the figure, 1 ... CCD image sensor chip, 2 ... photoconductor film, 11 ... p
+ Type Si substrate, 12 …… p well, 13 …… storage diode, 1
4 …… vertical CCD, 15 …… p + type layer, 16 1 , 16 2 …… transfer gate, 17 …… n + type polycrystalline silicon electrode, 18 1 , 18 2 …… interlayer insulating film, 19 …… pixel Electrode, 20 ... Dummy electrode, 21 ... i
Type a-SiC: H film, 22 …… i-type a-Si: H film, 23 …… p-type a-SiC: H film
Membrane, 24 ... Transparent electrode, 25 ... n + type polycrystalline silicon electrode,
26 …… n + type drain part, 27 …… incident light, a …… distance between the pixel electrode 19 and the dummy electrode 20 at the end, b …… each pixel electrode
Distance between 19, A ... area outside the pixel array.

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板に信号電荷蓄積ダイオードの配
列と信号電荷読み出し部の配列が形成され、最上部に前
記信号電荷蓄積ダイオードと電気的に接続された画素電
極の配列が形成された固体撮像素子チップ上に光電変換
部として光導電体膜が積層された固体撮像装置におい
て、前記画素電極の配列の端部の画素電極に隣接してダ
ミー電極が形成され、前記光導電体膜で発生した信号電
荷のうち、前記ダミー電極に流れ込んだ信号電荷を排出
することを特徴とする積層型固体撮像装置。
1. A solid-state imaging device in which an array of signal charge storage diodes and an array of signal charge readout units are formed on a semiconductor substrate, and an array of pixel electrodes electrically connected to the signal charge storage diodes is formed on an uppermost portion. In a solid-state imaging device in which a photoconductor film is stacked as a photoelectric conversion unit on an element chip, a dummy electrode is formed adjacent to the pixel electrode at the end of the array of pixel electrodes, and the dummy electrode is generated in the photoconductor film. A stacked solid-state image pickup device, characterized in that, of the signal charges, the signal charges flowing into the dummy electrode are discharged.
【請求項2】前記半導体基板に拡散領域からなるドレイ
ン部が形成され、このドレイン部が前記ダミー電極と電
気的に接続されたことを特徴とする特許請求の範囲第1
項記載の積層型固体撮像装置。
2. A drain portion formed of a diffusion region is formed on the semiconductor substrate, and the drain portion is electrically connected to the dummy electrode.
The laminated solid-state imaging device according to the item.
【請求項3】前記信号電荷蓄積ダイオードと前記信号電
荷蓄積ダイオードと電気的に接続された前記画素電極と
が2次元に配列されたことを特徴とする特許請求の範囲
第1項記載の積層型固体撮像装置。
3. The stacked type device according to claim 1, wherein the signal charge storage diode and the pixel electrode electrically connected to the signal charge storage diode are two-dimensionally arranged. Solid-state imaging device.
JP61308282A 1986-12-26 1986-12-26 Stacked solid-state imaging device Expired - Fee Related JP2509592B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61308282A JP2509592B2 (en) 1986-12-26 1986-12-26 Stacked solid-state imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61308282A JP2509592B2 (en) 1986-12-26 1986-12-26 Stacked solid-state imaging device

Publications (2)

Publication Number Publication Date
JPS63164270A JPS63164270A (en) 1988-07-07
JP2509592B2 true JP2509592B2 (en) 1996-06-19

Family

ID=17979155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61308282A Expired - Fee Related JP2509592B2 (en) 1986-12-26 1986-12-26 Stacked solid-state imaging device

Country Status (1)

Country Link
JP (1) JP2509592B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6545711B1 (en) * 1998-11-02 2003-04-08 Agilent Technologies, Inc. Photo diode pixel sensor array having a guard ring
JP4130211B2 (en) * 2006-05-31 2008-08-06 三洋電機株式会社 Imaging device
JP5927483B2 (en) * 2011-10-12 2016-06-01 パナソニックIpマネジメント株式会社 Solid-state imaging device
JP7134911B2 (en) * 2019-04-22 2022-09-12 キヤノン株式会社 Solid-state image sensor and imaging system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5387619A (en) * 1977-01-13 1978-08-02 Toshiba Corp Solid pickup unit
JPS6149569A (en) * 1984-08-17 1986-03-11 Matsushita Electronics Corp solid-state imaging device
JPS61127165A (en) * 1984-11-24 1986-06-14 Sharp Corp Semiconductor device

Also Published As

Publication number Publication date
JPS63164270A (en) 1988-07-07

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