JP2672578B2 - Still image playback circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention mainly relates to a circuit such as a color television receiver or a VTR which can store a television image signal in a memory and reproduce it as a still image. A stable black level can be reproduced even during reproduction. The present invention relates to a still image reproducing circuit.

[Conventional technology]

A video signal processing device has been developed aiming at high image quality and multi-functionality by performing video signal processing using a large capacity memory such as a field memory and a frame memory.
In particular, as one of the multi-functionalization, development of a video signal processing device having a still image reproducing function for stillly displaying a moving image is being actively developed. Examples of such still picture reproducing technology include JP-A-60-182283 "Still picture reproducing apparatus" and TV technology VOL.35, No.2p47-54.

An example of a conventional still image reproducing circuit will be described with reference to FIG. In the figure, 101 is a composite video input terminal, 102 is an A / D conversion circuit, 103 is a sync separation circuit, 104 is a burst signal extraction circuit, 105 is a clock generation circuit, 106 is a memory control circuit, 108 is an image memory, 110 is a still image reproduction control signal input terminal, 111 is a D / A conversion circuit, and 112 is a video output terminal. The basic operation of this device is shown below.

The composite video signal input from the composite video input terminal 101 is converted by the A / D conversion circuit 102 from an analog value to a digital value. The sync separation circuit 103 outputs a horizontal sync signal H and a vertical sync signal V and sends them to the memory control circuit 106. In the burst signal extraction circuit 104,
The burst signal fsc is extracted from the composite video signal and sent to the clock generation circuit 105. Clock generation circuit 105
Then, the clock signal synchronized with the burst signal fsc is generated to generate the memory control circuit 106, the A / D conversion circuit 102 and the D / A.
The necessary clocks are supplied to the conversion circuits 111.

In the memory control circuit 106, the A / D conversion circuit 102
Then, the operation of writing the video signal data converted into the digital value to the image memory 108 and the operation of reading it from the image memory 108 are controlled. The operation of the memory control circuit 106 in the case of still image reproduction will be described with reference to FIG.

FIG. 5A shows an input signal to the image memory 108.
B, C ... Represent data for one field, respectively. In the case of still image reproduction, the image memory 10 is activated by the still image reproduction start signal input from the still image reproduction control terminal 110.
Stop writing to 8. This write operation is controlled by a write signal ▲ ▼ (FIG. 5 (b)). FIG. 5 (b) shows an example in which the writing is stopped after the A field data is written.

The read operation is controlled by the read signal ▲ ▼ (FIG. 5 (c)). The read signal is the fifth
As shown in FIG. 6D, the A field data is repeatedly read out and the still image is reproduced.

[Problems to be solved by the invention]

In the still image reproducing circuit as shown in FIG. 4, the image memory usually has to have a storage capacity of one field of pixels or one frame, which is a problem in terms of cost reduction. In order to reduce the memory capacity, it is possible to store only the video period of the image and replace the signal of the blanking period (hereinafter referred to as the blanking period) in the analog circuit, but it is unique to the analog circuit such as temperature characteristics. The luminance reference information (black level) existing in the blanking period of the digitized video signal due to
There was a problem that was lost.

It is an object of the present invention to provide a still picture reproducing apparatus which can reduce the memory capacity and can reproduce a stable black level in an all digital manner.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a still picture reproducing circuit for reproducing a still picture using an image memory for storing one field period or one frame period of a quantized television video signal. A reference level reproduction circuit for reproducing the reference level of the video signal by averaging the signal levels of a part of the blanking period of the television video signal, and a television video signal obtained from the reference level reproduction circuit. The image memory includes: a holding circuit that holds the reference level during the still image reproduction period; and a switching circuit that switches and outputs the reference level obtained from the holding circuit and the video signal reproduced from the image memory. , The signal of the video period excluding the blanking period of the television video signal is stored in the switching circuit, and the switching circuit switches the blanking of the still image. During between a reference level signal from the holding circuit, except the blanking period of the still image is accomplished by switching and outputting a video signal from the image memory.

[Action]

The reference level reproducing circuit during the blanking period of the video signal uses the reference level extracting circuit to extract the reference level (black level) of the blanking period from the video signal before it is written to the image memory, and cumulatively adds it. Play the reference level. The reference level holding circuit, during the still image playback period,
The reference level reproduced from the reference level reproduction circuit is held. Further, since the switching circuit switches the blanking period of the video signal read from the image memory to the reference level reproduced by the reference level reproducing circuit, it is not necessary to store the blanking period information in the image memory. , It is possible to reproduce a stable black level when reproducing a still image.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
In the figure, 101 is a composite video signal input terminal, 10
2 is an A / D conversion circuit, 103 is a sync separation circuit, 104 is a burst signal extraction circuit, 105 is a clock generation circuit, 106 is a memory control circuit, 107 is a black level reproduction circuit, 108 is an image memory, 109
Is a switching switch, 111 is a D / A conversion circuit, 112 is a video output terminal, and 110 is a still image reproduction control signal input terminal.

The composite video signal input from the composite video input terminal 101 is converted by the A / D conversion circuit 102 from an analog value to a digital value. The sync separation circuit 105 outputs a horizontal sync signal H and a vertical sync signal V and sends them to the memory control circuit 106. In the burst signal extraction circuit 104,
The burst signal fsc is extracted from the composite video signal and sent to the clock generation circuit 105. Clock generation circuit 105
Then, a clock signal synchronized with the burst signal fsc is generated and the necessary clock is supplied to the memory control circuit 106, the A / D conversion circuit 102, and the D / A conversion circuit 111. The memory-control circuit 106 controls the operation of writing the digital data converted into the digital value by the A / D conversion circuit 102 to the image memory 108 and the operation of reading the digital data from the image memory 108. In the case of still image reproduction, the image memory 108 is controlled by the control signal input from the still image reproduction control signal input terminal 110.
Still image reproduction is performed by stopping the write operation to and re-reading the video information written in the image memory 108.

Normally, the image memory 108 has a storage capacity for one field of an image and one frame, but in order to reduce the memory capacity,
Only the video period of the image is stored, and the blanking period (blanking period) is not stored. Therefore, the luminance reference information (black level) existing in the blanking period
Is lost. Therefore, with the black level reproduction circuit 107,
The lost black level is reproduced, and the black level output from the black level reproducing circuit 107 is inserted by the switching switch 109 during the blanking period of the video signal reproduced from the image memory 108.

Further, the digital value is converted into an analog value by the D / A conversion circuit 111 and output from the video output terminal 112.

In the black level reproduction circuit 107, in order to reproduce the black level corresponding to the video signal read from the image memory 108,
The black level is maintained during the still image reproduction period by the control signal input from the still image reproduction control signal input terminal 110.
An example of the black level reproducing circuit 107 is shown in FIG. 201 is A /
In the D conversion circuit 103, a video signal input terminal converted into digital data, 202 is a pedestal position pulse input terminal of the video signal, 203 is a subtraction circuit, 204 is a coefficient circuit, 205 is an addition circuit, 206 and 208 are latch circuits, and 207 is An averaging circuit, 209 is an AND gate, 210 is an OR gate, 211 is a clock input terminal, and 110 is a still image reproduction control signal input terminal. The operation of this circuit will be described below.

The video signal converted into digital data by the A / D conversion circuit 102 is input to the video signal input terminal 201. Further, in the subtraction circuit 203, the coefficient circuit 204, and the addition circuit 205,
The output of the latch circuit 206 is fed back to perform cumulative addition. Further, the output of the latch circuit 206 is averaged by the averaging circuit 207 to reproduce the black level. In this case, the pedestal position pulse input from the pedestal position pulse input terminal 202 is the frequency 4 input from the clock input terminal 211.
The clock signal of fsc is gated by the AND gate 209 and supplied to the clock terminal of the latch circuit 206, and cumulative addition is performed only during the blanking period to retain the data. Further, the control signal input from the still image reproduction control terminal 110 is gated by the OR gate 210 and the clock signal input from the clock input terminal 211 is supplied to the latch circuit 208. , Stop the clock of the latch circuit 208,
The black level output from the averaging circuit 207 is held.

In the present embodiment, the subtraction circuit 203 of the black level reproduction circuit 107
A coefficient circuit 204, an addition circuit 205, and a latch circuit 206.
And an averaging circuit 207 constitute a reference level reproducing circuit,
The latch circuit 208 constitutes a holding circuit.

A second embodiment according to the present invention will be described with reference to FIG. In the figure, 301 is a composite video input terminal, 3
02 is a clamp circuit, 303 is an A / D conversion circuit, 304 is a motion adaptive Y separation circuit, 305 and 307 are switching switches, 306 is a frame memory, 308 is a sync separation circuit, 309 is a burst signal extraction circuit, and 310
Is a memory control circuit, 311 is a clock generation circuit, 312
Is a still image reproduction control signal, 313 is a D / A conversion circuit, and 314 is a luminance signal output terminal.

The operation of this circuit is based on the composite video input terminal 301.
The composite signal input from the clamp circuit 302
And is clamped to the pedestal level of the video signal. Furthermore, the A / D conversion circuit 303 converts the analog value into a digital value. Motion adaptive Y separation circuit
In 304, only the luminance signal is output from the composite signal by using the frame memory 306 or the like. The memory control circuit 310 controls the frame memory so that the signal delay is required for the motion adaptive Y separation circuit 304 during normal operation (when not reproducing a still image). During still image reproduction, the switching switch 305 controls the movement adaptive Y separation circuit 304.
The output signal from is written in the frame memory 306. In reading, a still image is reproduced by repeatedly reading the data written in the frame memory 306. Control of still image reproduction in this case is performed by a control signal from the still image reproduction control signal input terminal 312. Black level reproduction circuit 107
Then, by the above control signal, a stable black level can be reproduced by holding the black level value during reproduction of a still image.

〔The invention's effect〕

As described above, according to the present invention, the information of only the video period is stored in the image memory, and the information of the blanking period is not stored, but from the video signal before being written in the image memory,
Extracts the reference level during the blanking period, adds and averages it to reproduce the black level, holds the reproduced black level during the still image reproduction period, and blanks the video signal read from the image memory. By inserting the reproduced black level during the period, the black level at the time of still image reproduction can be reproduced correctly digitally.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment according to the present invention.
2 is a block diagram showing a concrete example of the black level reproducing circuit in FIG. 1, FIG. 3 is a diagram showing a second embodiment according to the present invention, and FIG. 4 is a block diagram of a conventional example of a still image reproducing circuit. ，
FIG. 5 is an operation diagram of the memory control circuit in FIG. Explanation of symbols 108 …… Image memory, 109 …… Switching switch 106 …… Memory control circuit 107 …… Black level reproduction circuit 110 …… Still image reproduction control signal input terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masato Sugiyama, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Home Appliances Research Laboratory, Hitachi, Ltd. (72) Kenji Katsuma, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa (72) Inventor Nao Suzuki, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Video Engineering Co., Ltd. (72) Kazuhiro Kaizaki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Yokohama factory (56) Reference JP-A-1-164182 (JP, A)

Claims (1)

(57) [Claims] 1. A still image reproducing circuit for reproducing a still image using an image memory for storing one field period or one frame period of a quantized television video signal, A reference level reproduction circuit for reproducing the reference level of the video signal by averaging the signal levels of a part of the blanking period, and a still image reproduction period for the reference level of the television video signal obtained from the reference level reproduction circuit. And a switching circuit for switching and outputting a reference level obtained from the holding circuit and a video signal reproduced from the image memory, and a television video signal in the image memory. A signal of a video period excluding a blanking period, and the switching circuit controls the holding circuit during a blanking period of a still image. The reference level signal et, the still image reproducing circuit other than the blanking period of still image and outputs by switching the video signal from the image memory.