JP2698236B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory in which writing and reading of data are performed asynchronously.

[0002]

2. Description of the Related Art In general, a dual port memory has been developed for a video memory used for a screen memory, a 1H delay or the like, or a FIFO memory of a system for performing digital processing by AD conversion of a video signal.

FIG. 2 shows a conventional dual-port memory composed of a DRAM.

The memory cell 1 is a so-called three-transistor type dynamic memory cell constituted by N-channel MOS transistors, and comprises a write transistor 2, a read transistor 3, and a memory transistor 4 serving as a capacitor. The information charge is accumulated in the NOS capacitance between the gate electrode and the channel of the memory transistor 4, and data is determined based on whether the memory transistor 4 is on or off based on the accumulated charge.

[0005] The memory cell 1 of the write transistor 2 gate is connected to each of the write word line WWL is outputted from the write row address decoder 5 _i (i = 1~X), the write row address decoder 5,
The count value of the write row address counter 6 that counts the write row address clock Wφ _ROW is applied. The drains of the write transistors 2 are respectively connected to write bit lines BLW _j (j = 1 to Y), and a write amplifier 7 and a precharge transistor 8 are connected to each write bit line BLW _j . Further, the output W of the write column address decoder 9 is provided between the input of the write amplifier 7 and the data input line D _IN.
A selection transistor 10 controlled by C _j is provided, and a count value of a write column address counter 11 that counts a write control clock Wφ _CL is applied to a write column address decoder 9.

On the other hand, the gate of the reading transistor 4 of the memory cell 1 is connected to each of the read word line RWL _i output from the read row address decoder 12, the read row address decoder 12, the read row address clock R [phi] _ROW The count value of the read row address counter 13 for counting the number of bits is applied. The drain of the readout transistor 4 are respectively connected to the read bit lines BLR _j, the sense amplifier 14 to each of the read bit lines BLR _j and Purocha -
The di-transistor 15 is connected. Further, between the sense amplifier 14 and data output lines D _OUT, select transistor 17 which is controlled by the output RC _j of the read column address decoder 16 is provided to the read column address decoder 16, the read control clock R [phi] _CL
The count value of the read column address counter 18 that counts the number is applied.

In FIG. 2, in a write operation and a read operation of the memory cell 1, peripheral circuits, that is, a write row address decoder 5, a write column address decoder 9, a read row address decoder 12, and
A circuit such as a read column address decoder 16, and
In order to prevent the data generated in the memory cell 1 from being affected by noise generated from circuits other than the memory when circuits other than the memory shown in FIG. 2 are formed on the same semiconductor substrate, Is formed in a P-type region independent of the semiconductor region where the MOS transistor of the peripheral circuit is provided, and a supply line for the substrate voltage of the P-type region and a ground voltage connected to the N-channel MOS transistor Was independent of the ground voltage lines of other circuits.

[0008]

According to the configuration of FIG. 2,
Characteristics of the writing transistor 2 of the memory cell 1, for example, the source-drain voltage V _DS constitutes the write amplifier 7 for driving the write bit line BLW _j C-
It depends on the ground voltage level of the N-channel transistor of the MOS transistor. Therefore, the amount of charge charged in the memory transistor 4 changes depending on the characteristics of the writing transistor 2. That is, the noise generated in the ground voltage of the peripheral circuit affects the memory cell 1.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and a write word line selected according to write address data and a signal based on the write data are transmitted. A write bit line, a read word line selected according to read address data, a read bit line to which a signal corresponding to stored data is transmitted, a write word line driver driving the write word line, and the write bit line A write bit line driver for driving a line, a read word line driver for driving the read word line, and memory cells respectively arranged at intersections of the write word line and the write bit line and the read word line and the read bit line. A semiconductor substrate region in which the memory cell is formed, wherein the write word line driver and the write bit line driver are each formed of a CMOS in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series, and A word line driver and the write bit line driver are formed in the semiconductor substrate region, and a source of an N-channel MOS transistor forming the write word line driver and the write bit line driver in the semiconductor substrate region; Are grounded in common with the substrate voltages of the MOS transistors constituting the MOS transistors.

[0010]

According to the above means, a write word line driver and a write word line driver are provided in a semiconductor region in which a memory cell is formed.
By forming a MOS transistor constituting a write bit line driver and connecting it to a dedicated ground line independent of other ground lines, noise generated on the ground line of the peripheral circuit is transmitted to the write bit line and the write word line. And the effect of noise on the memory cells is eliminated.

[0011]

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same components as those in FIG. 2 are omitted.

[0012] Memory cell 1 is a dynamic memory cell of the three-transistor type of the indicated memory cells 1 in the same configuration in FIG. 2, the read word with each being connected to the write word line WWL _i and the write bit lines BLW _j Line RWL _i and read bit line BLR _j
Connected to. Each of the read bit lines BLR _j, the sense amplifier 20 is connected, the sense amplifiers 20
Is connected to the selection transistor 17 shown in FIG.

[0013] The write word line WWL _i are each connected to the output of the write word line driver 21, decoder output of the write row address decoder 5 in FIG. 2 is connected to the input of the write word line driver 21. Each of the write bit lines BLW _j is connected to the output of the write amplifier 22, the input of the write amplifier 22 is connected to the selection transistor 10 in FIG. 2. Also,
Each read word line RWL _i is connected to the output of the read word line driver 23, the input of the read word line driver 23 is connected to the decoder output of the read row address decoder 12 of FIG.

Each of the drivers 21, 23 and the write amplifier 22 is a CMOS composed of a P-channel MOS transistor and an N-channel MOS transistor. Here, the N-channel MOS transistors 2, 3, and 4 constituting the memory cell 1 are all the same P-type semiconductor region 24.
(Indicated by a circuit portion surrounded by a broken line, but actually formed in an independent P-WELL formed on a semiconductor substrate). Further, the N of each of the drivers 21 and 23 and the write amplifier 22 is The channel MOS transistor is also formed in the same P-type semiconductor region 24 as memory cell 1.
A ground line 25 for supplying a substrate voltage of the N-channel MOS transistors 2, 3, and 4 of the memory cell 1, that is, a ground voltage for supplying a ground voltage for reversely biasing the P-type semiconductor region 24 to the semiconductor substrate body is provided. , The source electrode of the memory transistor 3 is connected to the ground line 25, and the drivers 21, 23,
The source electrode of the N-channel MOS transistor of the write amplifier 22 is connected.

The ground line 25 is provided independently of a ground line of a peripheral circuit formed outside the P-type semiconductor region 24, and is connected to a ground voltage pad on a semiconductor integrated circuit substrate. Or, ground line 2
The pad to which the pad 5 is connected and the pad to which the ground line of the peripheral circuit is connected may be separately formed.

According to the configuration of FIG. 1, the current flowing due to the operation of the peripheral circuit concentrates on the ground line of the peripheral circuit and does not flow to the ground line 25 of the memory cell 1.
Therefore, each of the drivers 21 and 23 and the write amplifier 22
For variations in the source voltage of N-channel MOS transistor is eliminated, there is no voltage variation of the write word line WWL _i and write bit lines BLW _j or read word line RWL _i, the characteristic change of the transistor 2, 3 and 4 of the memory cell 1 Is prevented. That is, the influence of noise generated on the ground line of the peripheral circuit does not affect the memory cell 1.

[0017]

As described above, according to the present invention, in a memory cell and its peripheral circuit formed on the same semiconductor substrate, it is possible to prevent noise generated in the peripheral circuit from affecting the memory cell, and to improve reliability. Semiconductor memory with high performance can be realized. In particular, when a functional circuit such as a digital signal processing circuit and a memory circuit are built on the same semiconductor substrate, the effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 1 memory cell 20 sense amplifier 21 write word line driver 22 write bit line driver 23 read word line driver 24 P-type semiconductor region 25 ground line

Claims (1)

(57) [Claims] A write word line selected according to write address data, a write bit line to which a signal based on the write data is transmitted, a read word line selected according to the read address data, and a read word line selected according to the stored data. A read bit line to which the read signal is transmitted, a write word line driver driving the write word line, a write bit line driver driving the write bit line, a read word line driver driving the read word line, comprising a respective memory cells arranged in said write word line and write bit line and the intersection of the read word lines and read bit lines, and a semiconductor substrate region in which the memory cells are formed, the write Wadora In-driver and the write driver
The set line drivers are each a P-channel MOS transistor.
And N-channel MOS transistor are connected in series
A CMOS comprising at least the write word line driver and the write word line driver;
The write bit line driver is located in the semiconductor substrate area.
And the write word line is formed in the semiconductor substrate region.
A write driver and the write bit line driver.
A source of an N-channel MOS transistor to be formed;
The substrate voltage of the MOS transistor forming the memory cell and
Are commonly grounded.