JP2600588B2 - Method of forming dry etching mask - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a dry etching mask.

[0002]

2. Description of the Related Art Conventionally, an organic resist or a silicon oxide (Si) to which an organic resist pattern has been transferred has been used as a dry etching mask in a manufacturing process of a semiconductor device or the like.
A mask of an inorganic film such as O ₂ ) or silicon nitride (SiN _x ) or a metal film is used. Optical exposure, electron beam exposure, and the like are used for patterning the organic resist.

[0003] For example, in optical exposure, patterning is performed by using an exposure mask drawn by an electron beam, disposing the mask between a resist film and a light source, and exposing an unmasked portion to light. In electron beam exposure, patterning is performed by irradiating an electron beam on a substrate coated with an organic resist sensitive to the electron beam and drawing a pattern directly. In a method called lift-off, a metal thin film is vapor-deposited on a patterned organic resist, and then the organic resist is removed with a solvent, and a metal thin film is formed by removing the metal on the organic resist. .

[0004]

In any of the above-described mask forming methods, an organic resist is used for patterning. Therefore, the size fluctuation of the end face due to non-uniformity of the omission during development of the organic resist film and a large molecular size. Occurs.
Further, in the optical exposure, there is fluctuation of an electron beam at the time of preparing an optical exposure mask, and in the lift-off method, there is fluctuation of a pattern end caused by grains or the like at the time of vapor deposition of a lift-off metal thin film. When etching is performed using an etching mask having these end face fluctuations, the end face fluctuations are transferred as they are, and a vertical stripe 15 as shown in FIG.

In the case of forming a semiconductor laser stripe, for example, the vertical stripes increase the waveguide loss due to the vertical stripes on the side surfaces. In the case of forming a quantum wire, there is a problem that the quantum effect is canceled out because the vertical stripes fluctuate in size.

An object of the present invention is to provide a method for forming a dry etching mask having less side fluctuation.

[0007]

According to the present invention, there is provided a method of forming a mask for dry etching, comprising the steps of forming a film to be etched and an oxide film or a nitride film on a substrate, and exposing the oxide film or the nitride film after patterning the same. Selectively forming a mask semiconductor film on the film to be etched.

[0008]

In the selective growth of a semiconductor film, a plane orientation with a slow growth appears on the side surface. At this time, even if there is fluctuation at the end of the mask for selective growth made of the initial oxide film or nitride film,
The fluctuation disappears as the semiconductor film growth proceeds, and a flat side surface is formed on the order of an atomic layer. Therefore, by dry-etching the film to be etched using this as a mask, it becomes possible to perform etching with less side fluctuation.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.
FIGS. 1A to 1C are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention. In particular, FIGS.
The case of creating a quantum wire is shown.

First, as shown in FIG. 1A, a metalorganic vapor phase epitaxial growth method (MO-V
The InGaAs layer 2 is grown to a thickness of 50 nm by PE). Next, a thermal chemical vapor deposition (thermal CVD: Che
An SiO ₂ thin film having a thickness of 10 nm is formed by a physical vapor deposition. Patterning of an electron beam resist by electron beam lithography and pattern transfer by reactive ion etching using CF ₄ gas are performed on this to form a stripe-shaped SiO ₂ pattern 3 having a thickness of 10 nm and a width of 30 nm parallel to the <110> direction. Form. Next, using this SiO2 pattern 3, an InP mask 4 is selectively grown to a thickness of 50 nm by a selective growth method using MO-VPE. At this time, the side surface of the InP mask 4 becomes the (111) surface, and a flat surface is formed on the order of the atomic layer.

Next, as shown in FIG. 1B, the SiO ₂ pattern 3 is removed with buffered hydrofluoric acid. Then, using this InP mask 4, room temperature, 8 × 10 ⁻⁴ Torr
etching with chlorine gas in a reactive ion beam etching apparatus under etching conditions of
The aAs layer 2 is etched.

As shown in FIG. 1C, the MO-VP
The whole is buried and grown by InP5 by the E method,
A GaAs embedded quantum wire structure is formed.

FIGS. 2A to 2D are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention. In particular, the present invention relates to a SCH (InGaAs / InGaAsP / InP embedded quantum wire laser). separate conf
The case where the present invention is applied to the production of an ined heterostructure structure substrate is shown.

First, as shown in FIG. 2A, an InGaAsP cladding layer 6 having a thickness of 0.2 μm and a wavelength composition of 1.3 μm is formed on an InP substrate 1 by MO-VPE, and a thickness of 10 μm.
nm InGaAs active layer 7, 20 nm thick InAl
An As removal layer 8 and a 20 nm thick InGaAs cap layer 9 are grown. Next, a 10 nm-thick SiN _x film is deposited thereon by plasma CVD, and a striped SiN _x pattern 3 having a width of 20 nm is formed in parallel with the <110> direction by electron beam lithography and RIE using CF ₄ gas.
Form A. Next, an InP mask 4 having a thickness of 50 nm is formed by selective MO-VPE. The side surfaces of the InP mask 4 are also flat on the order of the atomic layer.

Next, as shown in FIG. 2B, the SiN _x film is removed with buffered hydrofluoric acid. Subsequently, using an InP mask 4, room temperature, acceleration voltage 400 V, gas pressure 8 × 1
Chemically reactive ion beam etching is performed under the condition of 0 ^-4 Torr to etch the InGaAs cap layer 9, the InAlAs removal layer 8, and the InGaAs active layer 6.

Next, as shown in FIG. 2C, the InAlAs removal layer 8 is removed by etching with buffered hydrofluoric acid, thereby simultaneously removing the InGaAs cap layer 9 and the InP mask 4 thereon.

Next, as shown in FIG.
2 μm thick InGaAsP cladding layer 10 and InP
By growing the cap layer 11, a SCH structure substrate for a quantum wire laser is created.

FIGS. 3A and 3B are cross-sectional views of a semiconductor chip for explaining a third embodiment of the present invention, particularly showing a case where the present invention is applied to GaAs etching.

First, as shown in FIG.
On the GaAs substrate 12 on the B side, Si is applied in the same manner as in the first embodiment.
An O ₂ pattern 3 is formed. Next, A by MO-VPE
lGaAs is selectively grown. 1993 Spring Applied Physics Society Proceedings, First Volume, 263 pages, 30p-ZR-. As reported by Ando et al. At this time, the AlGaAs mask 13
Becomes the (110) plane, and vertical side walls are obtained. Utilizing this AlGaAs mask 13, chlorine and SF 6 are added in a ratio of 1:
Room temperature, 8 × 10 ⁻⁴ Torr,
When reactive ion beam etching is performed under the condition of 400 V, the selectivity between GaAs and AlGaAs is 20 or more, so that a pattern in which the side surface becomes flat on the GaAs substrate 12 can be formed.

[0020]

As described above, according to the present invention, there is an effect that a dry etching mask with little side fluctuation can be easily formed. Therefore, the characteristics of a semiconductor device such as a semiconductor laser and a quantum wire laser can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor chip for explaining a third embodiment of the present invention.

FIG. 4 is a perspective view showing a fluctuation of a mask side surface and a vertical stripe on a side to which the fluctuation is transferred.

[Explanation of symbols]

1 InP substrate 2 InGaAs layer 3 SiO ₂ pattern 3A SiN _X pattern 4 InP mask 5 InP buried layer 6 InGaAsP cladding layer 7 InGaAs active layer 8 InAlAs removal layer 9 InGaAs cap layer 10 InGaAsP clad layer 11 InP cap layer 12 GaAs substrate 13 AlGaAs mask

Claims (1)

(57) [Claims] A step of forming a film to be etched and an oxide film or a nitride film on a substrate; and patterning the oxide film or the nitride film to selectively form a semiconductor film for a mask on the exposed film to be etched. Forming a dry etching mask.