JP2610858B2 - Color pixel information processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing apparatus, for example,
The present invention relates to a technology effective for use in a color drawing processor.

[Conventional technology]

As a processor for graphic controllers,
For example, there is “Hitachi Microcomputer 8 / 16-bit Microcomputer Peripheral LSI”, pp. 522 to 589 (HD63484), published in September 1985 by Hitachi, Ltd.

Typical drawing functions of this processor include straight lines,
Interpret and execute 38 graphic drawing commands such as circle, paint, and copy. In addition, it has eight types of drawing operation modes. In particular, when conditional replacement is used, it has a color drawing function such as specification of a specific background color, specification of a drawing prohibition color, and drawing with priorities of color data.

[Problems to be solved by the invention]

In the above-mentioned processor, since the development of a character font and the calculation of pixels are performed in units of one pixel (pixel) regardless of monochrome or color, there is a problem that the processing speed is slow.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus that increases the drawing processing speed.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
A plurality of bits to be subjected to color development are extracted by a barrel shifter in response to a plurality of bits of information representing a character or a graphic in which one pixel is composed of one bit, and a plurality of bits corresponding to a plurality of N-bit color pixels are extracted by a barrel shifter. And selectively outputs the contents of the first and second color registers holding the color pixel information of the plurality of pixels represented by N bits according to the bit information. is there. Also,
Using a plurality of color pixel information as one word, two words of color pixel information are stored in the source data register, and one pixel data is stored in the source data register according to the destination data by the barrel shifter.
The pixel data is extracted in word units, and the output signal of this barrel shifter and the destination data, or the output signal of this barrel shifter and the color information specified by the color comparison register, or the destination data and the color specified by the color comparison register A color operation comparison is performed on the information in accordance with a color comparison mode, and write color pixel information is generated in word units by the output signal of the barrel shifter and destination data in accordance with the output signal and a predetermined color processing signal. It is.

(Operation)

According to the above-described means, since data processing is performed in word units, high-speed processing becomes possible.

〔Example〕

FIG. 1 is a block diagram showing an embodiment for realizing a circuit function for performing color development of characters and the like and color pixel processing in a drawing processor to which the present invention is applied. Although not particularly limited, the drawing processor of this embodiment is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The source data register is composed of SLBU and SLBV.
Two words of data are stored in the source data registers SLBU and SLBV. For example, the data buses UBB and VBB
It is configured by a bit bus, and data is transferred in units of 16 bits. The above source data registers SLBU and SLBV
Is composed of a 16-bit register, so that the source data for the two words is stored in two cycles.

For example, as shown in FIG. 2, the rendering processor GDP decodes the character code sent from the microprocessor, accesses the character area of the frame buffer memory FB, and displays a monochrome image in which one pixel is composed of one bit. The bit pattern is extracted in units of 16 bits. That is, in FIG. 1, the memory address register MAR
The information read out to the bus IDB connected to the frame buffer memory by accessing the memory is taken into the read data register RDBR. This read register RDBR
Is temporarily taken into a temporary register (not shown) through the bus UBB. The data for the next one word is also taken into the read register RDBR in the same manner as
Is taken into the source data register SLBU via At this time, the immediately preceding data of one word already stored in the temporary register is transferred to the source data register SLBV via the bus VBB. As a result, the character pattern information for two words is stored in the source data register SLBU.
SLBV will be read.

When the unit color pixel is composed of 4 bits, for example, of the character information composed of 32 bits in total, the first 4 bits of information that is the basis of the pixel information corresponding to one word are extracted by the barrel shifter BRLSFT. The control signal of the barrel shifter BRLSFT is formed by a microprogram ROM (not shown). This microprogram ROM has a character A represented by 5 × 7 bits.
In the case of (1), after the extraction of the first 4 bits (0010), a control signal for extracting bit pattern information for each 4 bits (boundary processing) such as 4 bits (0010)... . Each of the above circuits corresponds to the interworking register IWR in FIG.

The 4-bit character pattern information extracted in this manner is supplied to a data expansion circuit DE, where data expansion is performed so that one pixel becomes 4 bits at a time. That is, in the case of the above 4 bits (0010), 0000, 0000, 1111,
It is expanded by four bits according to each bit like 0000.

The color registers CL0 and CL1 store color pixel information signals for four pixels, respectively. For example, the color register CL0 stores color pixel signals for four pixels specified by 0001, and the color register CL1 stores color information for four pixels specified by 1101. These pixel information is 1/0 of the above character pattern (black / white)
For example, red / blue. Each color information of the color registers CL0 and CL1 is supplied to the multiplexer MPX in bit units. The multiplexer MPX outputs the bit of the color register CL0 if 0, for example, and outputs the bit of the color register CL1 if 1 according to the output bit of the bit extension circuit DE. As a result, the character pattern 0 is converted into color pixel information such as 0001, and the character pattern 1 is converted into color pixel information such as 1101. In the simplest image processing, the pixel information is directly written into the frame buffer memory FB, and one pixel is set to 0001 or 11
The character A represented by the two colors designated by 01 will be drawn. That is, the character A of the color designated by 1101 is drawn on the background of the color designated by 0001.

In this embodiment, a character pattern in which one pixel is composed of one bit is written in the character area of the frame buffer memory FB, so that a large number of characters or symbols (including registered figures) can be stored with a small storage capacity. Can be. Then, the data processing is performed in word units (one word is
By performing the processing in 16-bit units (in units of 4 pixels when one pixel is 4 bits), the color development of a monochrome character font can be performed at high speed.

The color character information generated as described above and the color calculation processing of the source data already drawn in the frame buffer memory FB are also processed in units of one word as described above.
For example, the source data stored in the frame buffer memory FB is read out in word units to the read data register RDBR in the same manner as described above by being addressed by the memory address register MAR, and the source data registers SLBU and SLBV are read out. It is stored in a similar source data register (not shown). At this time, the source data for two words is read out for the boundary processing with the detonation data, as in the color development of the character pattern. That is, as shown in FIG. 3, when the source data SD does not extend over two words, the source data SD of one word including pixels or
1 and another one-word source data SD2 including “1” and “1” are extracted. On the other hand, when the destination data DD is composed of a word including a pixel and a word including a pixel, the pixel of the source data SD1 is shifted by the barrel shifter BRLSFT and is adjusted to the destination data DD1. When the output signal of the barrel shifter BRLSFT is color pixel information, the bit expansion circuit DE outputs the signal as it is. This output signal is selectively transmitted to the buses VBB, WBB and CLB via the register DLB. For example, when performing a color operation, it is transmitted to the color bus CLB and supplied to the operation circuit AU and the logical operation circuit LU. Also for the color character information formed by the color development of the character font, if predetermined arithmetic processing is necessary, the color developed character information is transmitted from the multiplexer MPX to the color bus.

The arithmetic circuit AU performs various color operations in the above word units. For example, a match with color information specified by the color comparison register CLCMP is detected, and a magnitude determination is performed. Alternatively, a comparison operation is performed between the destination data and the source data. Alternatively, a comparison operation is performed between the destination data and the color information specified by the color comparison register CLCMP. The zero extension circuit ZE extends the coincidence result in pixel units to four bits as described above. For example, no operation is performed on a pixel having the same color as the background color, or data of the color specified by the color comparison register CLCMP is cut out. The carry extension circuit CE processes the carry signal for the magnitude comparison determination. The above arithmetic circuit AU
Output signal is selected by the CMPMSEL
Is output to the mask bus MSKB via the.

The logical operation circuit LU performs various logical operations on a bit basis, for example, a logical operation process with a base to form write information on the frame buffer memory FB on a word basis. At this time, writing to the pixel specified by the mask register MSK can be prohibited. This makes it possible to perform a masking process as shown in FIG. 3 in which, in writing in units of words, a portion where no effective pixel exists is marked with a cross. While writing in the frame buffer memory FB in units of the words, the arithmetic circuit AU performs the next color operation, and the logical operation circuit LU forms write information for the frame buffer memory FB. While the arithmetic operation circuit AU performs the color operation and the logical operation circuit LU performs the logical operation processing, the barrel shifter extracts the next pixel to be processed. In other words, the barrel shifter extracts a plurality of pixel data for color processing including boundary processing, and the color arithmetic processing and the logical arithmetic processing are performed by a pipeline method, so that the parallel processing of the plurality of pixels (four pixels) is performed. Together, the color drawing operation can be performed at high speed.

The operational effects obtained from the above embodiment are as follows. That is, (1) receiving a plurality of bits of information representing a character or a graphic in which one pixel is composed of one bit, extracting a plurality of bits to be color-developed by a barrel shifter, and corresponding to a color pixel composed of N bits. The contents of the first and second color registers that hold the color pixel information of the plurality of pixels represented by N bits are selectively expanded according to the bit information while expanding the bit information corresponding to the plurality of color pixels. In this case, data of a plurality of pixels constituting a color character or the like can be generated at high speed, in other words, the color development of a character font can be performed at high speed.

(2) Since a character pattern in which one pixel consists of one bit is written in the character area of the frame buffer memory, many characters or symbols (including registered figures) can be stored with a small storage capacity. The effect is obtained.

(3) Two or more words of color pixel information are stored in a source data register with a plurality of pieces of color pixel information as one word, and pixel data is taken out in units of one word by a barrel shifter in accordance with the destination data, and the destination is extracted therefrom. A color comparison operation according to the color comparison mode is performed between the data, the color information specified by the color comparison register CLCMP, or the destination data and the color information specified by the color comparison register CLCMP. By generating write color pixel information in units of one word based on the output signal of the barrel shifter and the destination data in accordance with the color processing signal, the effect of increasing the speed of the color drawing operation can be obtained.

(4) The pixel image to be processed by the barrel shifter, the color arithmetic processing thereof, and the logical operation for forming a write signal to be written to the frame buffer memory are performed by a pipeline method, whereby the color image signal in word units is obtained. In combination with the above processing, the effect that the speed of the color drawing operation can be further increased can be obtained.

Although the invention made by the inventor of the present application has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and it is needless to say that various changes can be made without departing from the gist of the invention. Nor. For example, the configuration of each register and arithmetic circuit and the bus system can be variously modified as long as the same operation as described above is realized.

The present invention can be widely used for various information processing apparatuses that process graphic data, such as the above-described drawing processor.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a plurality of bits to be subjected to color development are extracted by a barrel shifter by receiving information of a plurality of bits representing a character or a figure in which one pixel is composed of one bit, and a plurality of colors corresponding to a color pixel in which one pixel is composed of N bits. The contents are expanded to bit information corresponding to the pixels, and the contents of the first and second color registers holding the color pixel information of the plurality of pixels each represented by N bits are selectively output according to the bit information. As a result, data for a plurality of pixels constituting a color character or the like can be generated at high speed, in other words, color development of a character font can be performed at high speed. The color pixel information for two words is stored in the source data register with the plurality of pieces of color pixel information as one word, and the pixel data is taken out in units of one word by the barrel shifter in accordance with the destination data. Or a color comparison operation between the output signal of the barrel shifter and the color information specified by the color comparison register, or the destination data and the color information specified by the color comparison register according to the color comparison mode. By generating write color pixel information in units of one word based on the output signal of the barrel shifter and the destination data according to the signal and a predetermined color processing signal, the color drawing operation can be speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part showing an embodiment of the present invention, FIG. 2 is a principle diagram for explaining color development of the character font, and FIG. 3 is a processing of the plurality of color pixel information. It is a principle diagram for explaining operation. SLBU, SLBV: Source data register, BRLSFT: Barrel shifter, DE: Data extension circuit, DLB: Register, M
PX: Multiplexer, CL0, CL1: Color register, C
LCMP: color comparison register, MSK: mask register, AU: arithmetic circuit, ZE: zero extension circuit, CE: carry extension circuit, CMPMSEL: selector, LU: logical operation circuit, WDBR: write data Register, RDBR …… Read data register, MAR …… Memory address register, FB…
… Frame buffer memory, GDP …… drawing processor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masahiko Kikuchi 3-2-1, Yukicho, Hitachi City Within Hitachi Engineering Co., Ltd. (72) Shigeru Matsuo 4026 Kujimachi, Hitachi City Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Akihiro Katsura 4026 Kuji-cho, Hitachi City Hitachi, Ltd. Hitachi Research Laboratory (56) References JP-A-61-107290 (JP, A) JP-A-62-15595 (JP, A)

Claims (3)

(57) [Claims] 1. A barrel shifter for extracting a plurality of N bits to be color-developed from image data representing a graphic including a character or a symbol in which one pixel is composed of one bit, and a plurality of bits corresponding to lighting of the pixel. A first color register that stores the first color pixel information as data of a total of M bits corresponding to the N bits extracted by the barrel shifter; and a second color register that includes a plurality of bits corresponding to lighting of pixels. A second color register for storing color pixel information as a total of M bits of data corresponding to the N bits extracted by the barrel shifter; and a first and a second color register for extracting the pixels extracted by the barrel shifter, respectively. A data expansion circuit that expands the data into a plurality of bits corresponding to the color pixel information and expands the data to a total of M bits; For each bit of the output signal of the extension circuit,
A multiplexer for selectively outputting each bit of the first or second color register; and a write circuit for writing color pixel information output via the multiplexer to a frame buffer memory via the M-bit width data bus. And a color image information processing apparatus. 2. The color shifter according to claim 1, wherein the plurality of N to be color-developed from first and second source registers for receiving the first and second image data read from the frame buffer in units of M bits. 2. The color image information processing apparatus according to claim 1, wherein bits are taken out. 3. A color image information processing device connected to a frame buffer memory having a drawing area to be displayed on a display device by a data bus having an M bit width, wherein the color image information processing device is provided in units of M bits from the frame buffer memory. First and second source data registers for respectively capturing first and second first image data to which continuous addresses corresponding to the X direction on the display screen are assigned, and a plurality of pixel data from the source data register A barrel shifter to be taken out, an arithmetic circuit for performing color arithmetic including color information match detection and magnitude judgment, and a logical arithmetic circuit for performing logical arithmetic with reference to mask information in bit units to form write information in a frame buffer memory. While writing in the frame buffer in units of M bits, The path performs a color operation on the image data to be processed next, the logic operation circuit forms information to be written to the frame buffer memory, and while the operation is being performed, the barrel shifter has to process the next. A color image information processing apparatus, wherein a series of operations for extracting image data is performed by a pipeline method.