JP2618502B2 - Semiconductor device and electronic device - Google Patents

Description

The present invention relates to a semiconductor device, particularly to a structure of a bipolar transistor (BPT), and an electronic device as an application example thereof.

[Prior Art] Conventionally, a bipolar transistor (DOPOS BPT) in which an emitter region is formed by doped polycrystalline silicon
Or hetero-bipolar transistor (HBT) that forms the emitter region with microcrystal (μc) etc.
It has been known.

[Problems to be Solved by the Invention] However, in the DOPOS BPT, when miniaturized, a large current amplification factor h _FE cannot be obtained, and it is difficult to reduce the resistance of the base region, Further, there is a problem that the use limit in the high frequency range is low in the frequency characteristics.

On the other hand, although HBT is formed to solve the above problem, it is a serious problem that a good hetero interface cannot be formed.

One solution to the problem is to make microcrystalline silicon (microcrystal (μc) -Si containing hydrogen).
It is not a stable crystalline form by heat treatment during the process.
Often, characteristic degradation occurs. In addition, since hydrogen is contained, the deterioration is further promoted.

SUMMARY OF THE INVENTION The present invention provides a semiconductor device which aims to increase the current amplification factor, reduce the base current, and prevent deterioration in characteristics due to heat treatment, and an electronic device as an application example thereof in order to solve the above problems. The purpose is to provide.

[MEANS FOR SOLVING THE PROBLEMS] An object of the present invention is to provide a semiconductor device including a first conductivity type collector region, a second conductivity type base region, and a first conductivity type emitter region. Is the energy φ of the potential of the barrier formed at the internal grain boundary.
This is achieved by a semiconductor device in which a polycrystalline layer having a grain size of 200 ° to 1000 ° whose _B is larger than the thermal energy kT at the operating temperature of the semiconductor is provided.

In the above feature, it is preferable that the polycrystalline layer has a characteristic that a reciprocal of a resistance value thereof is substantially constant with respect to a temperature rise or has a characteristic of increasing with the temperature rise. The polycrystalline layer preferably contains silicon as a main component. Further, it is preferable that the thickness of the emitter region is set to be smaller than the diffusion length of minority carriers injected from the base region into the emitter region. Further, the polycrystalline layer is formed in a layer structure in which a plurality of polycrystalline layers are vertically stacked, and the upper polycrystalline layer is set to have a larger particle size or a higher impurity concentration than the lower polycrystalline layer. Is preferred.

Further, the above-described semiconductor device can be applied to an electronic device characterized by being used at least as a photoelectric conversion element.

[Operation] The polycrystalline layer formed on the emitter region has the same effect as that of μc-Si having a wide bandgap. For example, the polycrystalline layer is formed on the emitter region at a temperature of about 550 to 640 [° C.] by LPCVD. accumulate. Also, the polycrystalline layer hardly contains hydrogen,
A stable crystal grain size range is provided, and a barrier is provided for carriers injected from the base into the emitter region.

Embodiment FIG. 1 shows a first embodiment according to the semiconductor device of the present invention.

In FIG. 1, reference numeral 1 denotes a silicon substrate, which is made of phosphorus (P), arsenic (As), antimony (Sb).
And n-type by doping with impurities such as boron (B), aluminum (Al), and gallium (Ga).

2 is an n ⁺ buried region, and the n ⁺ buried region 2
For example, it is composed of 10 ¹⁶ to 10 ²⁰ [cm ⁻³ ] having a low impurity concentration.

Reference numeral 3 denotes an n-type region as a part of the collector region. The n-type region 3 is formed by an epitaxial technique or the like and has a low impurity concentration (about 10 ^{13 to} 5 × 10 ¹⁷ [cm ⁻³ ]). Consists of

Reference numeral 4 denotes a p-type region as a base region. The p-type region 4 has an impurity concentration of 10 ¹⁵ to 10 ²⁰ [cm ⁻³ ].

5 is a P ⁺ region, and the P ⁺ region 5 has an impurity concentration of 10 ¹⁷ to 10
²⁰ [cm ^-3 ].

6 is an n ⁺ emitter region.

Reference numeral 7 denotes an n ⁺ region, and the n ⁺ region 7 connects a later-described collector electrode 202 and the buried region 2 to reduce the collector resistance.

Reference numeral 8 denotes a polycrystalline layer made of polysilicon, and the polycrystalline layer 8 is a region serving as a barrier for carriers injected from the base region.

Reference numerals 101, 102, and 103 denote insulating films for separating electrodes, elements, and wiring.

Reference numerals 200, 201, and 202 denote an emitter electrode, a base electrode, and a collector electrode, respectively, which are formed of metal, silicide, or the like.

Next, the polycrystalline layer 8, which is the most important component in the present invention, will be described.

A polycrystal is a collection of single crystals having a certain size distribution, and the crystal grains of each single crystal do not have a fixed crystal orientation. Further, it has a crystal grain boundary, and the crystal grain boundary has remarkable lattice disorder. Due to the formation of the crystal grain boundaries, the polycrystal has different electric characteristics from the single crystal.

The electrical properties of polycrystals are greatly affected by the crystal grain size and the density of lattice defects at the grain boundaries.

Lattice defects present at the grain boundaries serve as deep acceptor or donor levels and become trapping centers for free carriers.
Captures charge in the forbidden zone. As a result, a depletion layer region is generated around the crystal grain boundary, the potential changes, and acts as a barrier against carriers.

The polycrystal has a particle size L [cm] and an impurity concentration Ni [c
m ^-3 ], trap level density at crystal grain boundaries Q _t [cm ^-2 ]
, The characteristic changes. The characteristic change will be described below using polycrystalline silicon as an example.

FIG. 2, Q _t> L · energy band diagram in the case of Ni (FIG. 2 (a)) and grain boundary B _C of the thin N-type polycrystalline in silicon, the depletion layer E _P spread (second FIG.

Figure 3 is, Q _t <energy band diagram in the case of L · Ni (FIG. 3 (a)) and a thin film N-type polycrystalline grain boundary B _C in the silicon, the depletion layer E _P spread (Third FIG.

That is, when Q _t > L · Ni, the inside of the polycrystalline silicon is completely depleted, whereas when Q _t <L · Ni, the depletion layer region is spread only near the crystal grain boundaries, and the neutral region is Is leaving. In other words, when Q _t > L · Ni, the resistance becomes extremely high.

FIG. 4 shows an example of the specific resistance ρ with respect to the impurity concentration Ni when the particle size L is changed to 200 [Å], 420 [Å], and 1220 [Å] while the trap state density _Qt is fixed. Have been.

Here, when the region is _Qt > L · Ni, the region is _Qt <L
・ Indicates the case of Ni.

The region has a high impurity concentration, a case where barrier phi _B shown in Figure 3 is extremely thin, since the carrier to pass by a tunnel effect barrier, there is no substantial barriers, close to a single crystal ratio It has resistance.

The region is a characteristic region unique to the polycrystal,
The region has too high a resistance and is not suitable for the semiconductor device of the present invention.

Therefore, in the present invention, the polycrystal in the above-mentioned region is used for the emitter region of the BPT.

Since it is difficult to actually measure the height of the barrier in the region, an example obtained by calculation as shown in FIG. 5 is shown.

That is, the crystal grain size L = 10 ⁻⁵ [cm] is fixed, and each value of the trap state density Q _t [cm ⁻² ] (1 × 10 ⁻¹³ , 5 × 10 ⁻⁵ corresponding to 〜 in FIG. 5, respectively) ^-12 , 2 × 10 ^-12 , 1 × 10 ^-12 , 5 × 10
^-11, 2 × 10 ^-11, is intended the height phi _B of the barrier 1 × 10 ^-11 of each value) respectively as the parameter plotted against impurity concentration Ni [cm ^-3].

According to experimental data, polycrystalline trap level density Q _t according to the present invention has a ^{1 × 10 -12 ~1 × 10 -13} [cm -2] value of about, and usually polycrystalline Particle size of 200 ~ 1000
Because it is [Å], height phi _B of the barrier is considered the value of the degree shown in Figure 5 typically has. Therefore, the height of the barrier φ
The maximum value of _B may be about 0.45 [eV]. However, the particle size L, the interface trap level density Q _t, impurity concentration Ni
Need to be optimized.

The current flowing through the polycrystalline region is determined by the carrier having a barrier φ _B
The current becomes a thermionic emission type current that flows beyond.

On the other hand, the width W (FIG. 3 (a) see) of the depletion layer E _P is the approximate, the Is represented by For example, when Q _t = 5 × 10 ⁻¹² [cm ⁻² ] and Ni is 1
If it is ^{0 18 [cm -3], W} = 5 × 10 -6 [cm] = 500 [Å] next, phi _B would occur extent 0.35 [eV]. As shown in FIG. 4, if L = 1000 [Å], the neutral region n _R is 500
[Å] remains.

FIG. 6 shows a potential diagram in a section taken along the line AA 'of FIG. Incidentally, E _R in the figure the emitter region,
B _R is a base region, C _R represents a collector region.

In the present invention, polycrystalline silicon having a potential barrier is used for an emitter region, and carriers injected from a base region are reduced to increase the gain of a BPT.

As shown in FIG. 6, a convex potential barrier for electrons is formed in the polycrystalline layer 8, while a concave potential barrier is formed for holes.

As shown in FIG. 7A, when the depth of the potential well is -φ _B and the width is a, the transmission probability T of the carrier is
_t is Is represented by

It is.

As an example, Then, T _t becomes as shown in FIG. 7 (b). E is the energy of the electron, and the transmission probability is remarkable when E / φ _B <1.
T _t goes down. E is usually a hole-blocking effect when the are the thermal energy kT temperature of about T phi _B> kT occur.

FIG. 8 shows characteristics of the reciprocal (conductivity) of the sheet resistance R of the polycrystalline silicon according to the present invention with respect to the reciprocal of the temperature T.

In the case of ', the concentration of polycrystalline silicon is the highest, and then the concentration decreases in the order of', '. In this case, the deposition temperature, thickness, and heat treatment are the same.

'Is the same as that of the conventional polycrystalline silicon. When the temperature T increases, 1 / R decreases. However, for 'and', the slope becomes gentler.
1 / R will rise.

In the cases of 'and', the potential described above is generated, and the mechanism of current flow is increased in the number of thermionic emission type, and the characteristics are changed. Whether at least 1 / R is flat with temperature,
When 1 / R increases due to temperature rise, BPT characteristics are improved.

′ For an emitter using polycrystalline silicon,
BPT using ',' polycrystalline silicon for emitter
, The base current decreases sequentially to 2/3, 1/3. Therefore, h _FE becomes 1.5 times and 3 times, respectively.

As shown in FIG. 1, n ⁺ region 6 is formed in a single crystal. When determining the base current, the n ⁺ region 6 is also an extremely important factor.

 The components of the BPT current will be described.

The collector current is approximately It is represented by

However, the electron diffusion distance is longer than the base width. Incidentally, N _B is base density, W _B bale width, D _n is the electron diffusion length, n _i is the intrinsic carrier density of Si, the V _BE is a voltage applied between the base and emitter.

That is, the collector current is determined not by the emitter region but by the base concentration thickness.

The base current includes a recombination current J _Brec of electrons injected from the emitter region in the base and a diffusion current J _{Bdiff of} holes injected from the base to the emitter. Here, the recrystallization current J _Brec is (However, L _n is the electron diffusion length) In addition, a conventional homojunction type BPT the diffusion current J _bdiff main component, high current gain can not be obtained.

This J _Bdiff of a normal homo BPT is obtained when the conventional hole diffusion length L _P is smaller than the emitter thickness W _E (case 1) (L _P ≪W _E ) It is.

On the other hand, with the recent high integration, the shallowing of the emitter junction is made, L _P »W _E becomes (Case 2) Next, further J _bdiff becomes large, a decrease in the BPT of h _FE occurs.

In the case of the present invention, when the recombination rate at the hetero interface is sufficiently suppressed, J _Bdiff3 becomes as follows. (L _P ≫W _E ) In the BPT of the present invention, in the case 1, the diffusion current J _Bdiff is W _E / L _P times that of the conventional _{homostructure} BPT. In addition, the diffusion current J
_Bdiff is ^twice (W _E / L _P).

As described above, by extremely reducing the diffusion current J _Bdiff , the current amplification factor h _FE can be dramatically increased.

FIG. 9 is a graph showing the relationship between the impurity concentration in the n ⁺ region, the hole diffusion distance, and the hole lifetime. From this relationship, the emitter depth is at least as large as the hole diffusion distance.
It is better to make it about 1/5.

Next, a manufacturing process of the semiconductor device shown in FIG. 1 will be described.

By implanting As, Sb, P, or the like into the p-type or n-type substrate 1 by ion implantation (impurity diffusion or the like may be performed), the n ⁺ buried region 2 having an impurity concentration of 1 × 10 ¹⁵ to 10 ¹⁹ [cm ⁻³ ] may be used. To form

Impurity concentration of 1 × 10 ¹⁴ by epitaxial technology
An n-type region 3 of 1010 ¹⁷ [cm ⁻³ ] is formed.

An n ⁺ region 7 (impurity concentration 1 × 10 ¹⁷ to 10 ²⁰ [cm ⁻³ ]) for reducing the resistance of the collector is formed.

An insulating film 102 for element isolation is formed by a selective oxidation method, a CVD method, or the like.

In order to form an active region, ap ⁺ region 5 and a p region 4 as a base region are formed by ion implantation or the like.

After opening the emitter contact in the insulating film 101, As, S
n ⁺ region doped with b, P, etc. (impurity concentration 5 × 10 ^{17 to} 5 × 1
[0 ²⁰ [cm ^-3 ]) 6 is formed by ion implantation or thermal diffusion.

Polycrystalline Si is deposited by the LPCVD method, and a polycrystalline layer 8 as an n ⁺ layer is formed by ion implantation or thermal diffusion, and then patterned.

After depositing the insulating film 103 and annealing it, a contact opening is made.

Al-Si (1%) serving as the electrode 200 is sputtered, and thereafter, Al-Si patterning is performed.

After alloying the Al-Si electrode, a passivation film is formed to complete the MIS structure BPT.

FIG. 10 shows a second embodiment according to the semiconductor device of the present invention.

Another polycrystalline layer 10 is stacked on the polycrystalline layer 8 having a potential barrier. That is, as shown in FIG. 3, since the polycrystalline layer 8 according to the present invention uses a region having higher resistance than conventional polycrystalline silicon or the like, a low resistance layer is provided on the polycrystalline layer 8.

One technique for forming the low resistance polycrystalline layer 10 is to increase the crystal grain size and lower the resistance.

For example, when the deposition temperature of polycrystalline silicon is
By changing the temperature from [° C] to 640 [° C],
0 can be created in the same process.

One technique for forming the low-resistance polycrystalline layer 10 involves changing the impurity concentrations of the polycrystalline layer 8 and the low-resistance polycrystalline layer 10.

The impurity concentration of the polycrystalline layer 10 is set to, for example, a region shown in FIG. For example, As, P
To make use of the difference in the diffusion coefficient between the polycrystalline layer 8 and the low-resistance polycrystalline layer 10, or to create a region of the polycrystalline layer 8 on the entire substrate 1 and then ion-implant the low-resistance polycrystalline layer 10 , Diffusion, etc.

FIG. 11 shows a third embodiment according to the semiconductor device of the present invention. In the third embodiment, after forming a P-type region 4 as a base region, an n ⁺ emitter region 6 is formed by selectively epitaxially growing only an emitter contact. In this structure, the impurity concentration of the emitter region 6 can be formed independently of the impurity concentration of the P ⁺ region 5 of the base, and a hetero bipolar characteristic can be utilized. Further, since the current in the horizontal direction in the emitter region can be reduced, the two-dimensional current is reduced, and the current amplification factor h _FE can be easily increased.

Next, FIG. 12 is a circuit diagram showing an embodiment of an electronic device as an application example of the semiconductor device according to the present invention. This shows a case where the BPT shown in the above embodiment is used for the solid-state imaging device disclosed by the present applicant in Japanese Patent Application No. 62-321423.

That is, in FIG. 12, the BPT shown in the above embodiment is used for the portion indicated by Tr. In other words, in this embodiment, the MIS type BPT is connected to the photoelectric conversion element (sensor cells C ₁₁ , C ₁₂ ,
... C _mn ).

When the area sensor AS shown in FIG. 12 is used as a color camera, an operation of reading out the optical information of the same photoelectric conversion element a plurality of times is performed. In this case, the ratio of the electrical output at the time of the first reading and the ratio of the electrical output at the time of the second and subsequent readings becomes a problem in order to perform reading from the same element a plurality of times. When the value of this ratio becomes small, correction is required.

If the ratio between the first and second read outputs is defined as the non-destructive degree, the non-destructive degree is expressed by the following equation.

Non-destructive degree = (C _tot × h _FE ) / (C _tot × h _FE + C _V ) where C _tot indicates the total capacitance connected to the base of transistor Tr shown in FIG. Determined by the capacitances _Cbc and _COX . Also, C _V is the stray capacitance of the reading line represented by VL ₁ ... VL _n. However, C _OX may not exist depending on the circuit system. The degree of non-destruction can be easily improved by increasing the current amplification factor _hFE . That is, it is possible to increase the non-destructive level by increasing the h _FE.

Here, in an area sensor compatible with HD (High Division), that is, a high-vision compatible, since C _tot = 10 [pF] and C _V = 2.5 [pF], for example,
H _FE is required 2250 or more non-destructive degree in order to be 0.90 or more. In order to obtain a sufficient non-destructive degree, h _FE is deemed necessary 2000 or more.

In contrast, conventionally, for example, in homozygous BPT, h _FE
Is about 1000, so that a sufficient degree of non-destruction cannot be obtained. On the other hand, in the semiconductor device of the present invention, _hFE can be sufficiently increased, so that an excellent degree of non-destruction can be obtained.

Further, desirably, the degree of non-destruction is 0.98 or more. In that case, _hFE is required to be about 10,000. Such values cannot be obtained with conventional homozygous BPTs.

In this embodiment, the case of the area sensor is described, but it is needless to say that the present invention can be applied to a line sensor.

[Effects of the Invention] As described above, according to the present invention, the following effects can be obtained.

A semiconductor device according to the present invention includes a semiconductor device having a first conductivity type collector region, a second conductivity type base region, and a first conductivity type emitter region. in the size of the energy phi _B of the potential barrier formed in the grain boundary is the semiconductor of the operating temperature, particle size 200Å, which is a value larger than the thermal energy kT
With the provision of the polycrystalline layer having a thickness of 1000 ° to 1000 °, the base current can be reduced, and the current amplification factor can be increased.

In particular, since the particle size is provided a polycrystalline layer of 1000Å from 200 Å, it is possible to change the barrier height phi _B as shown in Figure 5.

Also, since the polycrystalline layer is more stable than a single crystal,
The reliability of the semiconductor device is improved, and the characteristic deterioration due to the heat treatment is small.

Further, since the conventional mass production technology can be used, it can be manufactured at low cost. In addition, since stress such as a heterojunction does not occur in the emitter region, defects and the like are less induced, while np
It works effectively on semiconductor devices having both n and pnp structures.

In the above-described semiconductor device, the polycrystalline layer has a configuration in which the reciprocal of the resistance value is substantially constant with respect to a temperature rise or has a characteristic of increasing with the temperature rise. A barrier potential is generated inside, and the current of thermionic emission type increases, which can contribute to the improvement of BPT characteristics.

In the above semiconductor device, since the polycrystalline layer has a structure containing silicon as a main component, it can be deposited at a relatively low temperature, but has stable characteristics without containing hydrogen.

Further, in the above semiconductor device, the emitter region is
Since the thickness is set to be smaller than the diffusion length of minority carriers injected from the base region into the emitter region,
The diffusion current that contributes to the base current can be reduced, and the current amplification factor can be increased.

Still further, in the above-described semiconductor device, the polycrystalline layer may include:
Since the upper polycrystal is formed in a layered structure in which a plurality of polycrystal layers are vertically stacked, the upper polycrystal has a larger grain size or a higher impurity concentration than the lower polycrystal. Can be reduced.

In the electronic device of the present invention, since the above-described semiconductor device is used at least as a photoelectric conversion element, the current amplification factor of the transistor as the photoelectric conversion element increases,
An electronic device with improved non-destruction and a large signal / noise ratio can be provided.

[Brief description of the drawings]

Sectional view of FIG. 1 is a semiconductor device showing a first embodiment of the present invention, the energy level diagram of the polycrystalline layer in the case of FIG. 2 Q _t> L · Ni, FIG. 3 is Q _t <L · Energy level diagram of the polycrystalline layer in the case of Ni, FIG. 4 is a graph showing the relationship between the resistivity and the impurity concentration of the polycrystalline layer, and FIG. 5 is the height of the potential barrier height with respect to the impurity concentration of the polycrystalline layer. graph showing the relationship, FIG. 6 is an explanatory view showing a potential well in the case of FIG., FIG. 7 (a) depth -.phi _B, the width a indicating a potential along the line a-a 'of Figure 1 graph FIG. 7 (b) is representative of the relationship between the transmittance of the carrier with respect to E / phi _B, FIG. 8 is a graph showing the relationship between the diffusion length and minority carrier lifetime with respect to the impurity concentration, Fig. 9 is a polycrystalline silicon Reciprocal of sheet resistance (conductivity)
FIG. 10 is a cross-sectional view showing the configuration of a second embodiment of the semiconductor device according to the present invention; FIG. 11 is a cross-sectional view showing a third embodiment of the semiconductor device according to the present invention; FIG. 1 is a circuit diagram of an electronic device to which the semiconductor device according to the present invention is applied. (Reference Numerals) 1 ...... substrate, 2 ...... buried region, 3 ...... n-type region, 4 ...... p-type region, 5 ...... P ⁺ region 6 ...... n ⁺ emitter region, 7 ...... n ⁺ region 8 polycrystalline layer 101, 102, 103 insulating film 200, 201, 201 electrode, Tr BPT (photoelectric conversion element).

Claims (6)

(57) [Claims] 1. A semiconductor device comprising a collector region of a first conductivity type, a base region of a second conductivity type, and an emitter region of a first conductivity type. The energy φ _B of the potential of the formed barrier
Is the thermal energy at the operating temperature of the semiconductor.
A semiconductor device comprising a polycrystalline layer having a grain size of 200 to 1000 mm, which is larger than kT. 2. The polycrystalline layer according to claim 1, wherein the reciprocal value of the resistance value is substantially constant with respect to a temperature rise or has a characteristic of increasing with the temperature rise. Semiconductor device. 3. The semiconductor device according to claim 1, wherein the polycrystalline layer is mainly composed of silicon. 4. The emitter region according to claim 1, wherein the thickness of the emitter region is set to be smaller than the diffusion length of minority carriers injected from the base region into the emitter region. A semiconductor device characterized by the above-mentioned. 5. The polycrystalline layer according to any one of claims 1 to 4, wherein the polycrystalline layer is formed in a layer structure in which a plurality of polycrystalline layers are vertically stacked, and the upper polycrystalline layer is a lower polycrystalline layer. A semiconductor device characterized in that the particle size is set to be larger or the impurity concentration is set to be higher than in (1). 6. An electronic device, wherein the semiconductor device according to claim 1 is used at least as a photoelectric conversion element.