JP2622179B2 - Dynamic semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an improvement of a dynamic semiconductor memory device, and more particularly, to a dynamic memory device having a novel structure capable of improving the performance of a dynamic memory element. The present invention relates to a semiconductor memory device.

<Conventional Technology> In recent years, high integration of dynamic semiconductor memory devices has been proceeding at a tremendous rate, but two elements per bit (1
The memory cell configuration (transistor and one capacitor) has not changed.

FIG. 2 is a circuit diagram showing a configuration of a conventional dynamic semiconductor memory device.

In the figure, reference numeral 20 denotes a conventional memory cell (for one bit), 21 denotes a storage capacitor, 22 denotes a transfer gate serving as selection means, and 23 denotes a storage node.

On the other hand, there is a restriction that the storage capacity of the capacitor cannot be made very small from the viewpoint of reliability such as soft errors.

Therefore, in recent high integration, the approach from the process side has been mainly made to secure the minimum necessary storage volume in a small area. Stacked types or memory cells combining them have been developed.

<Problems to be Solved by the Invention> However, such a three-dimensional memory cell has many problems in the manufacturing process, and requires a considerable development period to ensure high reliability.

The present invention has been made in view of the above problems,
An object of the present invention is to provide a memory element in which two bits of information are stored by three elements of two transistors and one capacitor having the same storage capacity as before, that is, 1.5 elements per bit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

<Means and Actions for Solving the Problems> The following is a brief description of an outline of the invention disclosed in the present application. That is, it comprises complementary first and second bit lines for inputting and outputting information, storage capacity means for storing information, and first and second selection means for designating the storage capacity means. Bit line first
To one end of the storage capacitor means via the first selection means, and connect the other end of the storage capacitor means to the second
Has a memory cell structure connected to the second bit line of the complementary bit line via the selecting means, and the memory cell has positive and negative polarities and two types of stored charge amounts.
By storing quaternary, that is, 2-bit information, a memory cell with 1.5 elements per bit can be realized with a read margin higher than that of the conventional memory cell.

Embodiment FIG. 1 is a circuit diagram of a memory cell and a read / write circuit of a dynamic semiconductor memory device according to an embodiment of the present invention.

FIG. 3 shows input timing waveforms for explaining the operation of FIG. 1, and FIGS. 4 and 5 show waveforms at the time of reading bit lines for explaining the operation of the circuit of FIG. It is shown.

In the figure, reference numeral 10 denotes a memory cell (2) according to the method of the present invention.
11) are storage capacitors, 12 and 13 are transfer gates serving as first and second selection means, 14 and 15 are storage nodes, and 16 and 17 are sense amplifiers.

 The operation of the circuit shown in FIG. 1 will be described below.

Here, the word line WLL1 and the bit lines BLL1, ▲
(1) reading of the memory cell 10 selected by ▼,
Consider (2) rewrite, (3) precharge and (4) write operation.

FIG. 3 shows input timing waveforms for explaining the operation of FIG.

(1) Read operation At time t0 in FIG. 3, when NEQ and PEQ change as shown, all the transistors of the bit line equalizing circuit in FIG. 1 are turned off, and precharging of the bit line is completed. The voltage also becomes 1 / 2Vcc.

Next, the memory cell 10 connected to BLL1 and ▲ ▼
Is selected, the transistor of CUT2 is turned off, and the word line WLL1 rises at time t1.

Then, the information stored in the storage capacitor 11 is changed to the bit line
BLL1, BLR1, SBL1, SBL2, and ▲ ▼, ▲
The charge is transferred to ▼, ▲ ▼, ▲ ▼.

Further, when CUT1 and REQ fall at time t2, the bit line on the memory cell side is disconnected from the sense amplifier, and SBL1
And SBL2 and ▲ ▼ and ▲ ▼ are also separated. Thus, the same information in the memory cell 10 is
And 17 have separately.

At time t3, UP and DOWN are changed as shown in FIG. And pull up with ▲ ▼.

Finally, at time t6, the CSEL falls, the information of the amplified memory cell is transferred to the data line, and the read operation is completed.

Note that the bit lines SBL1, ▲ ▼ and S at time t3
The change of BL2, ▲ ▼ will be described in detail below.

Since the memory cell of the present invention stores 2-bit information in one storage capacitor, there are four types of voltage states of the storage nodes 14 and 15 when the memory cell holds information as shown in Table 1 below. is there. The data in the table indicates information output to the data lines D1 and D2, where H corresponds to Vcc and L corresponds to the GND voltage.

Among them, FIG. 4 shows a state when reading information of D1 = H and D2 = H, and FIG. 5 shows a state when reading information of D1 = H and D2 = L. . In the case of D1 = L and D2 = L, SBL1 and ▲ ▼ and ▲ ▼
If SBL2 is replaced and D1 = L and D2 = H, the fifth
In the figure, if SBL1 and ▼▼ and SBL2 and ▼▼ are interchanged, only the former two will be described.

First, when information of D1 = H and D2 = H is read, at time t1 when the word line rises as shown in FIG. 4, a potential difference of ΔV is generated between the complementary bit line pairs. At time t3,
SBL1, ▲ ▼ is 1 / 3Δ by UP and DOWN signal
The potential is increased by V, while the potential of SBL1 and SBL2 is decreased by 1 / 3ΔV. However, SBL1 and ▲ ▼ and SB
The voltages of L2 and ▲ ▼ do not reverse, and at time t4
After the subsequent sensing operation, both D1 and D2 output the Vcc level.

On the other hand, when reading the information _D1 = H α D2 = L, at time t1 word line as FIG. 5 rises, the bit line pairs each comprising complementary only occurs potential difference between 1 / 3ΔV. Therefore, at time t3, the SBL1, ▲
▼ raises the potential by 1 / 3ΔV, while ▲
▼, When the potential is lowered by 1 / 3ΔV, SBL2
And the potentials of ▲ ▼ are reversed. Therefore, after the sensing operation after time t4, Vcc is output to D1 and the GND level is output to D2.

Note that the value of 1 / 3ΔV is as follows, where the parasitic capacitance of the bit line is CB and the storage capacitance of the memory cell is CS. And when the CB / CS ratio is 2 or more,
Value in the case of the conventional method using Considering that the larger and practical CB / CS ratio is around 10, it can be understood that the read voltage of the bit line, that is, the read margin is better in the present invention.

(2) Rewrite operation At time t7 in FIG. 3, CSEL falls, the data line is disconnected, and at time t3, CUT1 and CUT2 fall, and the sense amplifier is also disconnected.

After the bit line on the memory cell side is floated in this way, BLS2 falls at time t9, and the bit lines BLL2, BLR2 and ▲ on the side where the memory cell 10 is not connected.
▼ and ▲ ▼ are divided into two.

Then, at time t10, W on the side where the memory cell 10 is connected
Turn down EQL, change BLL2 to BLL1 and BLR1, and ▲
Connect ▼ to ▲ ▼ and ▲ ▼.

As a result, the potential changes as shown in Table 2 below, and the same voltage as before the rise of the word line is written to the storage nodes 14 and 15 of the selected memory cell 10, and the storage capacitor 11 stores the same voltage. An electric charge corresponding to the voltage is stored.

Thus, at time t11, the word line WLL1 falls,
End rewriting.

(3) Precharge operation In the subsequent precharge, at time t12, UP, DOWN, BLS2, WE
Return QL, NEQ, PEQ to the initial state of the cycle, set the voltage of the bit line on the memory cell side to 1/2 Vcc by charge division, SA
Return S and ▲ ▼ to 1 / 2Vcc and stop the sense amplifier.

Finally, at time t13, CUT1, CUT2, and REQ rise to complete the precharge operation.

(4) Write Operation At the time of reading, at time t6 in FIG. 3, the data line is in a floating state until the CSEL rises. on the other hand,
At the time of writing, this data line is connected to H of write data.
(Vcc) is fixed to L (GND), and after time t6, the read data of the bit line is replaced with the write data.

After time t7, new information is written to the memory cell by the same operation as in the rewriting in (2).

FIG. 6 shows a second embodiment. The difference from FIG. 1 is that there is no need for a transistor having the gate of WEQR of the writing circuit. Also, two types of sense amplifiers SAS and ▲ ▼ are prepared for each sense amplifier (SAS1, SAS2, ▲
▼, ▲ ▼), operation of sense amplifier 17
By delaying it, the capacitor of the readout circuit rises
Only the signal may be used to boost only SBL2 and ▲ ▼.

FIG. 7 shows a third embodiment. The difference from FIG. 6 is that the readout circuit can boost SBL2, ▲ ▼ and also boost SBL1, ▲ ▼. Further, the transfer gates of the bit line sense amplifier disconnection circuit and the write circuit are complementary.

<Effects of the Invention> As described above, according to the present invention, a memory cell of 1.5 elements per bit can be realized with a read margin larger than that of the conventional memory cell, which greatly contributes to high integration of a dynamic semiconductor memory device. is there.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention;
FIG. 6 is a circuit diagram showing a configuration of a second embodiment of the present invention,
FIG. 7 is a circuit diagram showing a configuration of a third embodiment of the present invention,
FIG. 2 is a circuit diagram showing the configuration of a conventional dynamic semiconductor memory device, FIG. 3 is an input timing waveform diagram for explaining the operation of FIG. 1, and FIGS. FIG. 2 is a diagram showing waveforms at the time of reading of bit lines for explaining the operation of the circuit of FIG. DESCRIPTION OF SYMBOLS 10: Memory cell (2 bits) according to the method of the present invention,
Storage capacitors, 12, 13: transfer gates serving as first and second selection means, 14, 15: storage nodes, 16, 17: sense amplifier, 20: memory cell (1 bit) by conventional method, 2
1: Storage capacity, 22: Transfer gate as selection means, 2
3: Storage node.

Claims (1)

(57) [Claims] 1. Comprising: first and second complementary bit lines for inputting and outputting information, storage capacity means for storing information, and first and second selection means for designating the storage capacity means,
One end of the storage capacitance means is connected to the first bit line of the complementary bit lines via the first selection means, and the other end of the storage capacitance means is connected to the complementary bit line via the second selection means. A memory cell structure which is connected to a second bit line of a given bit line, and stores quaternary, that is, 2-bit information in the memory cell depending on whether the polarity is positive or negative and the amount of accumulated charge. Wherein the first and second bit lines complementary to each other are provided with a first differential amplifier via a third selector, and via a fourth selector. A second differential amplifier is connected to each other, and between a first input of the first differential amplifier connected to the first bit line and a second input connected to the second bit line. ,
And different changes in voltage between a first input of the second differential amplifier connected to the first bit line and a second input of the second differential amplifier connected to the second bit line. When the amount of charge stored in the storage capacitor means is large, the polarity of the potential difference between the two inputs of the first and second differential amplifiers is maintained as it is, and the amount of charge stored in the storage capacitor means is small. In this case, the polarity of the potential difference between the two inputs of the first or second differential amplifier is inverted.