JP2635631B2 - Nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a non-volatile semiconductor memory device using a rewritable memory cell having a floating gate and a control gate.

(Prior Art) In the field of EPROM, an ultraviolet erasing nonvolatile memory device using a memory cell having a MOSFET structure having a floating gate is widely known. Among EPROM, which are enable electrical erasing and writing is known as E ² PROM. A memory array of this type of EPROM is configured by arranging a memory cell at each intersection of a row line and a column line that cross each other. On the actual pattern, the drains of the two memory cells are made common, and the cell line occupied area is made as small as possible by contacting the column lines. However, even in this case, a contact portion with the column line is required for each common drain of the two memory cells, and this contact portion occupies a large area of the cell.

On the other hand, recently, an EPROM that can greatly reduce the number of contacts by connecting a plurality of memory cells to form a memory cell unit and connecting this memory cell unit to a column line is described above. A configuration in which memory cells are connected in series to form a memory cell unit is called a NAND cell. However, in an EPROM using such a memory cell unit such as a NAND cell, a peripheral circuit for controlling the EPROM has not been studied.

(Problems to be Solved by the Invention) As described above, in the EPROM using the memory cell unit recently proposed, a peripheral circuit for controlling the EPROM has not yet been studied.

An object of the present invention is to provide a nonvolatile semiconductor memory device which realizes an optimal peripheral circuit for controlling a memory cell unit when it is used.

[Structure of the Invention] (Means for Solving the Problems) In an EPROM according to the present invention, memory cells having a floating gate and a control gate are arranged in a matrix to constitute a memory array. In the memory cell, writing and erasing are performed by tunneling electrons between the floating gate and the substrate. Around the memory array, a sense array, a row and column decoder, a latch circuit for temporarily storing input / output data, and the like are arranged. In the present invention, apart from the latch circuit, a buffer memory having an integer larger than that of the latch circuit is provided. It is characterized by having.

(Operation) In the present invention, writing and erasing are performed by tunneling between the floating gate and the substrate, which can provide an oxide film having excellent film quality. Therefore, the EPROM has high reliability.

In the erasing operation of the cells according to the present invention, for example, in a NAND cell, an “H” level potential is applied to the control gates of all the memory cells constituting the NAND cell, the channel is set to an “L” level potential, Electrons from the region are injected into the floating gate by tunneling. This allows
In all the memory cells, the threshold value shifts in the positive direction to a “0” state. In the write operation, the “L” level potential is applied to the control gate of the selected one of the memory cells constituting the NAND cell, and the “H” level potential is applied to the control gate of all the memory cells on the drain side of the selected memory cell. In this state, an “H” level or “L” level potential is applied to the bit line according to data “1” and “0”. At this time, in a plurality of memory cells constituting the NAND cell, it is necessary to perform writing sequentially from a far side from the bit line. Because,
This is because a memory cell located on the bit line side with respect to a memory cell selected for writing has an "H" level applied to the control gate, so that when the writing order is reversed, the memory cell may enter the erase mode.

In the present invention, for example, when performing a page mode operation in an EPROM having such an operation principle, a buffer memory having a larger capacity is provided around the periphery separately from a data latch circuit, so that the time required for writing is reduced. It is possible to greatly shorten the time.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 5 is a plan view showing one NAND cell in the E ² PROM of one embodiment, and FIGS.
It is A ', BB' sectional drawing. FIG. 7 is an equivalent circuit of the NAND cell. Element isolation insulating film 2 of silicon substrate 1
In this embodiment, four memory cells are formed in one region surrounded by. In each memory cell, a floating gate 4 is formed of a first-layer polycrystalline silicon film via a first gate insulating film 3 of a thermal oxide film on a substrate 1, and a second gate insulating film of a thermal oxide film is formed thereon. A control gate 6 made of a second-layer polycrystalline silicon film is formed via the film 5. The control gate 6 of each memory cell is connected to the word line WL
Leads to. N ^{+ as} the source and drain of each memory cell
The mold layer 9 is shared by adjacent ones, and four memory cells are connected in series. The drain at one end of the memory cell is connected to the bit line 8.

In this configuration, the coupling capacitor C ₁ between the floating gate 4 and the substrate 1 in each memory cell is set smaller than the coupling capacitance C ₂ between the floating gate 4 control gate 6. Explaining this with specific cell parameters, the pattern size is 1 μm in width for both the floating gate 4 and the control gate 6 according to the 1 μm rule as shown in FIG. 5, and the channel width is 1 μm. It extends 1 μm on both sides on the field region. The first gate insulating film is, for example, a 200 ° thermal oxide film, and the second gate insulating film 5 is a 350 ° thermal oxide film. If the dielectric constant of the thermal oxide film is ε, then C ₁ = ε / 0.02 and C ₂ = 3ε / 0.035. That is, C ₁ <C ₂ .

FIG. 8 is a waveform diagram for explaining the write and erase operations in the NAND cell of this embodiment. First, collectively erased memory cells M ₁ ~M ₄ constituting the NAND cell. For this purpose, the bit line BL is set to the “L” level (for example, 0 V), the gate SG of the selection transistor is set to the “H” level (for example, the boosted potential Vpp = 20 V), and the control gates CG _{1 to} CG ₄ are all set to the “H” level ( For example, 20V). In this case, an electric field is applied between the control gate and the substrate of the memory cell M ₁ ~M _4, electrons from the substrate are injected into the floating gate by a tunnel effect. The threshold voltage of the memory cell M ₁ ~M ₄ is thereby moved in the positive direction, for example, an erase state threshold 2V.

Next, data is written to the NAND cell. In this case the writing is performed from the farther the memory cell M ₄ from the bit line BL in this order. Next, as will be apparent from the description, the memory cell on the bit line BL side from the selected memory cell is in the erase mode during the write operation. First of all, writing to the memory cell M ₄ is,
As shown in FIG. 8, the gate SG and control gate CG ₁ ~CG ₃ of the selection transistors, the boosted potential Vpp + Vth (the erased state of the memory cell threshold) or more "H" level (for example, 23
V). The control gate CG ₄ of a selected memory cell M ₄ is at "L" level (e.g., 0V). At this time, the bit line BL
"H" Given the level to which is transmitted to the drain of the memory cell M ₄ through the channel of the select transistors Q and memory cell M ₁ ~M _3, the memory cell M ₄ the control gate CG
High electric field is applied between ₄ and the substrate. As a result, electrons in the floating gate are emitted to the substrate by the tunnel effect, and the threshold value moves in the negative direction, for example, the state becomes "1" with a threshold value of -2V. Not applied electric field between the time the memory cell M ₁ in ~M ₃ control gate and the substrate, keeping the erased state. In the case of “0” writing, “L” level is applied to the bit line BL. It becomes a memory cell M ₁ ~M ₃ In the erase mode is from the selected memory cell M ₄ this time to the bit line BL side, they no problem because not yet data writing is performed. Next, as shown in FIG.
It goes to the writing of the memory cell M _3. That is, the selection gate SG is “H”
While maintaining the level, lowering the control gate CG ₅ to "L" level. If this time the bit line BL "H" level is given, the memory cell M ₃ "1" write is performed. Thereafter, similarly, writing is sequentially performed on the memory cells M ₂ and M ₁ .

In the foregoing, the configuration and operation of the basic NAND cell configuring the E ² PROM of the embodiment have been described. Next, the configuration and operation of the entire EPROM including the memory array using such NAND cells and its peripheral circuits will be described.

FIG. 1 is a block diagram showing the overall configuration of the E ² PROM. Reference numeral 11 denotes a memory array in which NAND cells as described above are arranged in a matrix. The specific configuration is, for example, the second
As shown in the figure. The bit lines BL and the word lines WL are arranged crossing each other, and memory cells M11, M12,... Each memory cell has four NAND cells as described above.
A cell is formed, and a drain at one end is connected to a bit line BL via a selection transistor. A bit line sense array 1 for detecting its output is provided around the memory array 11.
2, row decoder 13, row address buffer 14, column decoder 1
5. A column address buffer 16 is provided. Latch circuit 17
Is for temporarily storing input / output data, and has a capacity of the number of bit lines (256) in this embodiment. 18 is I / O
A sense amplifier, 19 is a data out buffer, and 21 is a data in buffer. In this embodiment, the latch circuit 17
Separately, a static RAM (SRAM) 20 as a buffer memory having a larger capacity is provided between the latch circuit 17 and the data-in buffer 21. In this embodiment, the SRAM 20 has 1 k bits of the number of bit lines (256) × the number of NAND stages (4). FIG. 4 shows a specific memory configuration of this SRAM.

FIG. 3 shows the page / page of the E ² PROM thus configured.
6 is a time chart for explaining an operation according to a mode. ▲ ▼ is the chip enable signal, which is “L”
Active at level. ▲ ▼ is an output enable signal. When this signal is at “H” level, it is in the write mode. ▲ ▼ is a write enable signal, which takes in an address when it changes from “H” level to “L” level, and takes in input data when it changes from “L” level to “H” level. R / is a Ready / Busy signal, which is at the "L" level during writing to notify the outside that writing is in progress.

Now, consider the case where there is no SRAM 20 in FIG. Light
High-speed data is obtained by repeating the cycle of “H” → “L” → “H” of the enable signal ▲ ▼ for one page (this embodiment assumes that the number of bit lines of the memory array is 256). Can be included. The data for one page is stored in the latch circuit 17 connected to the bit line.
The latched data is transferred to the bit line at the same time, and is simultaneously written to the memory cell specified by the address. These are the well-known page modes. For example, when writing 256 bits of data without using the page mode, the erase time and the write time are each 10 msec,
It takes 256 × 20 (msec) ≒ 5 (sec). On the other hand, when the above-described page mode is used, the time for taking in 256 external data (= 1 μsec × 256) + erasing time (10 msec) sec20.2
(Msec). That is, the speed is increased by about 250 times.

In this embodiment, as shown in FIG. 1, an SRAM 20 is provided separately from the latch circuit 17 in the peripheral circuit. This SRAM20
Has a capacity of one page (256) × the number of NAND cell stages (4), that is, a capacity of 1 k bits. FIG. 4 shows the internal configuration of the SRAM 20. The row is the number of NAND cell columns and the column is the page length. Data can be randomly written into this SRAM 20 at an arbitrary address in a page mode.
That is, the write enable signal ▲ depends on the page mode.
The “H” → “L” → “H” of ▼ is repeated 256 × 4 times, and 1 k of data is first taken into the SRAM 20. First, one page of M4, 1, M4, 2,..., M4, 256 data transferred to the SRAM 20 is transferred to the latch circuit 17. The transferred data for one page is based on the operation principle already described, and the word line WL in FIG.
The data is collectively written to 256 memory cells along ₄ . Next, the data of one page of M3, 1, M3, 2, ..., M3, 256 is SRA
It is transferred from the M20 to the latch circuit 17, which is simultaneously written to the 256 memory cells along the word line WL ₃ of Figure 2. In the same manner, the 1k-bit data of the SRAM 20 is sequentially and sequentially written.

In the page mode in which the SRAM 20 is not mounted, as described above, it takes 20.2 msec to write one page, and 20.2 (msec) × 4 = 80.8 (msec) to write 1 kbit. On the other hand, in this embodiment in which the SRAM 20 having a capacity of 1 kbit is mounted, the writing time of 1 kbit in the page mode is a time for taking in 256 external data (1 μsec × 256) + erase time (1
0msec) + writing time 10msec × 4) ≒ 50.2msec.
That is, the mounting of the SRAM 20 makes it possible to reduce the write time by about 62%.

As described above, according to this embodiment, it is possible to obtain a highly reliable E ² PROM by using a memory cell that performs writing and erasing by a tunnel current between a substrate and a floating gate in a NAND configuration. By mounting a buffer SRAM having a capacity of one page or more in addition to the latch circuit around the memory array, it is possible to speed up data writing in the page mode.

The present invention is not limited to the above embodiment. For example, in the above embodiment, a case has been described in which four memory cells are connected in series to form a NAND cell, but the number of memory cells forming the NAND cell is arbitrary. If the number of stages of NAND cells is increased, the speed of writing in the page mode is further accelerated. In the case of eight stages, the speed is increased by 56%. It is also useful to provide a buffer memory for output data. In the embodiment, the E ² PROM for electrically writing and erasing has been described.
The present invention can be applied to an ultraviolet-erasable EPROM.

In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, a buffer memory is provided in a peripheral circuit by using a memory cell unit capable of writing and erasing only by using tunneling between a substrate and a floating gate. By providing the EPROM, an EPROM capable of high-speed writing can be obtained.

[Brief description of the drawings]

Figure 1 is a block diagram showing the overall configuration of the E ² PROM of an embodiment of the present invention, FIG. 2 shows the configuration of the memory array, FIG. 3 is an operation of the E ² PROM in this embodiment FIG. 4 is a diagram showing the internal configuration of the SRAM mounted on the E ² PROM, FIG. 5 is a plan view showing one NAND cell constituting the E ² PROM of this embodiment, FIG. 6 (a) (b)
Is a sectional view taken along the line AA 'and BB' in FIG. 5, and FIG.
FIG. 8 is a waveform diagram for explaining the basic operation of the NAND cell. 1 ... silicon substrate, 4 ... floating gate, 6 ... control gate, M (M ₁ , M ₁ , ...) ... memory cell, BL (BL ₁ , BL ₂ ,
…)… Bit line, WL (WL ₁ , WL ₂ ,…) word line, 11
…… Memory array, 12… Bit line sense amplifier, 13…
... row decoder, 14 ... row address buffer, 15 ... column decoder, 16 ... column address buffer, 17 ... latch circuit, 18 ... I / O sense amplifier, 19 ... data out buffer, 20 ... SRAM (Buffer memory), 21 ... Data-in buffer.

Continuing from the front page (72) Inventor Fujio Masuzoka 1 Toshiba-cho, Komukai-shi, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Research Institute, Inc. (72) Inventor Masahiko Chiba 1-Toshiba-cho, Komukai-ku, Saitama-ku, Kawasaki-shi, Kanagawa Co., Ltd. Inside Toshiba Research Institute (56) References JP-A-61-294565 (JP, A) JP-A-60-229298 (JP, A)

Claims (4)

(57) [Claims] A floating gate and a control gate are stacked on a semiconductor substrate, and rewritable memory cells for performing writing and erasing by transferring charges between the floating gate and the substrate by a tunnel current are arranged in a matrix. A memory array formed by connecting the gate of each memory cell to a word line; a sense amplifier provided for each bit line; a row decoder and a column decoder for selecting an address of the memory array; A latch circuit for temporarily storing input / output data of an array, a buffer memory having an integral multiple of the capacity of the latch circuit and for temporarily storing input data to be sent to the latch circuit; The input data sent to the memory array is written into the memory array by a write operation in the page mode. The nonvolatile semiconductor memory device characterized by comprising a control circuit which controls to perform only once the erasing of the memory array when. 2. The method according to claim 1, wherein the buffer memory is a static RAM.
2. The non-volatile semiconductor memory device according to claim 1, wherein: 3. The memory cell unit according to claim 1, wherein a plurality of said memory cells are connected to form a memory cell unit, and a drain at one end of said memory cell unit is connected to a bit line. Nonvolatile semiconductor memory device. 4. The nonvolatile semiconductor memory device according to claim 3, wherein said memory cell unit comprises a plurality of memory cells connected in series to form a NAND cell.