JP2752948B2 - Floating point arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating-point arithmetic device, and more particularly, to a floating-point arithmetic device capable of obtaining an accurate result without a cancellation error and a propagation error associated therewith.

[0002]

2. Description of the Related Art In recent years, a large amount of data has been handled in the field of information processing. At that time, it has become an important issue to perform processing at higher speed and with higher accuracy.

For example, when performing arithmetic processing including decimal point data, there are generally fixed point arithmetic and floating point arithmetic. Fixed point arithmetic is high speed but inferior in accuracy.
Floating-point arithmetic has high and low characteristics, such as high precision but poor performance.

As a method of improving accuracy while maintaining processing performance, there has been proposed a technique of comparing the errors after calculation and separating the calculation units, as in the method described in Japanese Utility Model Laid-Open No. 64-18344.

However, in the above technique, since an error smaller than a certain value occurs, there is a possibility that a minute error at the time of occurrence of a digit loss as described below is mixed.

[0006] A floating point arithmetic unit processes numerical data in a floating point format. In the floating-point format, a numerical value is held in a mantissa part and an exponent part, and the relationship is expressed by the following equation, where N is the floating-point number.

N = 1. M * BexponentE M: mantissa part B: radix E: exponent part The most significant effect in performing a floating-point operation is a digit cancellation error that occurs when performing addition and subtraction between similar numerical values. In this case, not only the significant digits are lost, but also a small error may enter the lower digits of the mantissa during normalization.

Hereinafter, the calculation of "1.001-1" will be described as an example.

The radix B is "2", the exponent part E is 11 bits,
When the bias of the exponent is “1023” (expressed in hexadecimal,
"3FF"), and the mantissa M is 52 bits.

Hereinafter, the exponent part and the mantissa part are represented by hexadecimal numbers.

"1.001" means that the exponent part is "3FF",
The mantissa is “0041189374BC6A”.

For "1", the exponent part is "3FF" and the mantissa part is "0000000000000".

When the floating-point operation of the subtraction "1.001-1" is performed, the result becomes "0.004189374BC6A".

When this is rounded (supplementation of “0”) and normalized (in this case, shifted left by 10 bits), N1 =
"1.0624DD2F1A800".

As a result, the exponent is "3F5" and the mantissa is "0624DD2F1A800".

On the other hand, the actual "1.001-1 = 0.00
The result of shifting 1 ”to the left by 10 bits is N2 =“ 1.0
624DD2F1A9FC ".

Therefore, the correct mantissa is "1.06
24DD2F1A9FC ".

As described above, by the floating-point operation, N
2-N1 = an error of "0.0000000001FC" occurs.

[0019]

In the above-mentioned prior art, the erroneous calculation result due to the occurrence of the cancellation error is not considered.

This problem can be avoided by having the numerical data not in the floating point format but in a binary-coded decimal (hereinafter, referred to as BCD) format (the decimal point is treated as fixed), and the BCD operation can be avoided. There is a disadvantage that it takes more time than floating point arithmetic.

[0021] An object of the present invention is to perform a BCD operation only on an operation type that may cause a digit loss,
It is an object of the present invention to provide a floating-point operation device that can obtain an accurate operation result without significantly lowering the processing speed.

[0022]

According to a first aspect of the present invention, there is provided a floating-point arithmetic device comprising: (a) an arithmetic expression input means for inputting an arithmetic expression; and (b) an arithmetic expression input to the arithmetic expression input means. An arithmetic expression analyzing means for analyzing the expression and decomposing it into a combination of binary operations and outputting an operation type group and a floating-point data group; and (c) inputting the operation type group and the floating-point data group to An arithmetic control means for determining whether to perform an evolutionary decimal (BCD) operation or a floating-point operation; (d) an underflow determination means for determining the possibility of an underflow in the binary operation; Converting a floating point data pair of the floating point data group determined to have a possibility of a digit loss by the digit loss determining means into a binary coded decimal (BCD) data pair;
In addition, the binary code 10 for the binary code data pair
Data conversion means for converting a result of a binary (BCD) operation into first partial result data in a floating-point format; and (f) a binary coded decimal (B) code for the binary coded decimal data pair from the data conversion means. Binary Evolution Decimal (BC) that performs BCD) operation
D) calculating means, and (g) performing a floating-point operation on a floating-point data pair of the floating-point data group, the floating-point data of which is determined to be free from a possibility of loss of precision, Floating point arithmetic means for outputting partial result data and calculating the first partial result data and the second partial result data to calculate result data; and (h) result output means for outputting the result data. And.

The second floating-point arithmetic unit according to the present invention is the first floating-point arithmetic unit, wherein the digit for judging that there is a possibility of loss of digits in subtraction among the arithmetic type groups. It is provided with an omission determining means.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a floating point arithmetic unit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a floating point arithmetic unit according to the present invention.

FIG. 2 is a flowchart of the processing of the floating-point arithmetic unit of FIG.

FIG. 3 shows an example of an operation performed by the floating-point operation device of FIG.

Referring to FIG. 1, a floating-point arithmetic device using a binary-coded decimal number (hereinafter, referred to as BCD) operation according to the present invention comprises an arithmetic expression input means 1 for inputting an arithmetic expression.
And an arithmetic expression analyzing means 2 for analyzing the input arithmetic expression, an arithmetic control means 3 for extracting data of a binary operation based on the analyzed arithmetic expression, and a digit for determining whether or not a digit loss occurs in the arithmetic operation. Omission determining means 4 and arithmetic means 5 for performing a binomial operation
And data conversion means 6 for converting the data format, and result output means 7 for outputting the operation result.

The arithmetic means 5 is a floating point arithmetic means 51
And BCD operation means 52.

Next, the operation of the floating-point arithmetic unit of FIG. 1 will be described with reference to FIG.

Input from the arithmetic expression input means 1 (S20
1) The arithmetic expression is analyzed by the arithmetic expression analysis means 2 (S20)
2) It is decomposed into a combination of binary operations consisting of numerical data and operation types (addition, subtraction, multiplication, division).

Here, the numerical data is in a floating point format.

Next, the arithmetic control means 3 comprises the arithmetic expression analyzing means 2
Based on the arithmetic expression sent from, the numerical data of the binomial operation and the operation type are input (S203), and sent to the digit loss determination means 4.

The digit loss determining means 4 determines whether or not a digit loss will occur in the calculation to be performed (S204, S20).
5), and return the result to the arithmetic and control unit 3.

The arithmetic control means 3 passes the data to the arithmetic means 5, and the arithmetic means 5 performs the arithmetic. The arithmetic unit 5 performs floating-point arithmetic with the floating-point arithmetic unit 51 when the digit loss does not occur (S209), and performs the BCD operation with the BCD arithmetic unit 52 when the digit loss occurs. In the case of the floating-point operation, since the numerical data is stored in a floating-point format, the operation is performed as it is. In the case of the BCD operation, the data conversion means 6 converts the binary data of the binary operation from the floating-point format to the BC
After the conversion into the D format (S206), the BCD operation is performed, and the result (BCD format) is returned to the floating point format again by the data conversion means 6 (S208).

The result of the binary operation obtained by the floating point or BCD operation is reflected in the original operation expression (S21).
0), The calculation is repeatedly performed until the calculation formula sent from the calculation formula analysis means is completed. Finally, when the operation expression ends, the result is output by the result output means 7 (S21).
1).

If the analyzed expression is addition, multiplication, or division, there is no risk of occurrence of a digit loss, so that the binary operation is performed by a floating-point operation (S209).

If the arithmetic expression is subtraction, it is first determined based on the numerical data of the binomial operation whether there is a possibility of a loss of value in the operation to be performed (S205). Occurs, a BCD operation is performed (S
207) If no dropout occurs, a floating-point operation is performed (S209).

When performing the BCD operation, the data is converted from the floating point format to the BCD format in advance (S206).
From the floating point format to the BCD format (S208).

If the arithmetic expression includes all addition, subtraction, multiplication, and division, it is decomposed into binary operations, and the operations are performed in order. The calculation and the BCD calculation are performed separately.

FIG. 3 shows "(1.0
01-1) * 1000 ". First, the arithmetic expression" (1.001-1) * 1 "input from the arithmetic expression input means 1 is shown.
000 "is analyzed by the arithmetic expression analyzing means 2 and decomposed into a combination of binary data consisting of numerical data and an operation type.

In the case of the above arithmetic expression, (1) numerical data "1.001", "1", operation type: subtraction (2) numerical data (subtraction result of (1), "100
0 "), operation type: decomposed like multiplication.

At this time, the numerical data to be operated is stored in a floating-point format.

Next, the binary operation is repeatedly performed by the arithmetic means 5 until the arithmetic expression is completed.

In the above case, the binary operation of "1.001-1" is first performed. However, since the digit loss determination means 4 determines that a digit loss occurs, the numerical data "1.001,1" Is converted from the floating point format to the BCD format by the data conversion means 6, and the BCD calculation means 52 performs the BCD calculation.

The obtained result "0.001" is again converted from the BCD format to the floating point format by the data conversion means 6, and is reflected in the original arithmetic expression (→ "0.001 * 10").
00 ").

Since the arithmetic expression has not been completed yet, a binary operation of "0.001 * 1000" is performed next.

In the case of multiplication, no digit loss occurs, so that the floating-point arithmetic means 51 performs floating-point arithmetic and reflects the result in the original arithmetic expression (→ “1”). Here, the arithmetic expression ends, and the result output means 7 outputs the result “1”.

In the case where all of these operations are performed by floating-point operations, the first subtraction causes a cancellation error, so that exactly "0.
001 "is not obtained, and the error is reflected in the next multiplication, and an incorrect result may be obtained.

In the present apparatus, since no cancellation error occurs, the result of "1" can be obtained accurately.

[0051]

As described above, the BC according to the present invention is used.
Since the floating-point arithmetic device using the D operation is provided with a cancellation error determining means and uses the BCD operation when there is a possibility of an occurrence of an error, it is possible to obtain an accurate result without an error. Has an effect.

Further, since the time-consuming BCD operation is performed only when a digit loss occurs, there is an effect that a significant reduction in processing speed can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a floating-point arithmetic device according to the present invention.

FIG. 2 is a flowchart showing a process of the floating-point arithmetic device of FIG. 1;

FIG. 3 is an explanatory diagram illustrating an example of an operation performed by the floating-point operation device of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Arithmetic expression input means 2 Arithmetic expression analysis means 3 Arithmetic control means 4 Digit cancellation determination means 5 Arithmetic means 6 Data conversion means 7 Result output means 51 Floating point arithmetic means 52 BCD arithmetic means

Claims (2)

(57) [Claims] 1. An arithmetic expression input means for inputting an arithmetic expression, and (b) an arithmetic expression inputted to the arithmetic expression input means is analyzed and decomposed into a combination of binomial operations. Arithmetic expression analysis means for outputting a group and a floating-point data group;
(C) an operation control means for inputting the operation type group and the floating-point data group to determine whether to perform a binary-coded decimal (BCD) operation or a floating-point operation; Digit loss determining means for determining the possibility of digit loss,
(E) converting the floating-point data pair of the floating-point data group determined to have a possibility of cancellation by the cancel-out determination means into a binary-coded decimal (BCD) data pair; Data conversion means for converting the result of a binary-coded decimal (BCD) operation on the decimal data pair into first partial result data in floating-point format; and (f) the binary-coded decimal data pair from the data conversion means. 2 for
Binary Evolution Decimal (BC) that performs Evolutionary Decimal (BCD) operation
D) calculating means, and (g) performing a floating-point operation on a floating-point data pair of the floating-point data group, the floating-point data of which is determined to be free from a possibility of loss of precision, Floating point arithmetic means for outputting partial result data and calculating the first partial result data and the second partial result data to calculate result data; and (h) result output means for outputting the result data. And a floating point arithmetic unit. 2. The floating-point arithmetic device according to claim 1, further comprising: the digit loss determining means for determining that there is a possibility of a digit loss in the subtraction of the arithmetic type group.