JP2780406B2 - Initial setting control method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an initialization control method, and particularly to a large-scale integrated circuit (LSI) requiring an initialization such as a bus connection control circuit.
And a control method for performing an initial setting.

For example, "common buses (or buses)" used as information transfer means in exchanges, information processing devices, and the like include:
Many bus connection devices are connected, and a bus connection control circuit (Bus Interface Controlle) is provided at the bus connection portion of these devices.
r: BIC) is indispensable. The BIC has control registers that specify various transfer operation conditions according to the applicable device.The contents of these control registers are cleared when the power is turned off or reset. A so-called "initial setting" for setting to a predetermined state is required.

[Conventional technology]

In a common bus used as information transfer means in exchanges, information processing devices, etc., various devices (CPU / memory / IO
The BIC is used to connect to the bus in these devices. To use the BIC in a normal state, it is necessary to initialize the internal control register. However, when writing / reading to / from the control register by the bus access order for the initial setting, the device is separate from the so-called address information. Is given an identification code (ID) for identifying
BIC compares the ID value sent separately from the address with the ID value held by itself, and if the ID matches, accepts the access,
In the case of ID mismatch, there is a case where no response is made and a method for preventing unnecessary erroneous access is used.
In this case, it is used to specify the control register inside the BIC.) In addition, the ID assigned to the entire device including the BIC and the devices connected to the internal bus under the BIC (ID
A) and ID (IDB) for specifying a device connected to the BIC itself or the internal bus of the BIC.

The general method of initializing the BIC is to access control registers from the CPU or other device connected to the common bus via the common bus interface, or to connect the internal bus to a device with intelligence such as a microprocessor. There is a case where the control register is accessed by using. In the former case, IDA must be specified, and in the latter case, IDB must be specified to access the control register.

The procedure of the initial setting by order access of the control register is as described above. However, in the case of the control register access at the time of turning on the power or executing the reset, the autonomous initial setting for determining the ID information described later is further required. That is, when the power is turned on or the reset is executed, the contents of the control registers in the BIC are cleared, so that neither IDA nor IDB has a correct value. In such a state, the acceptance of the bus access cannot be correctly determined. Therefore, it is necessary to autonomously initialize these IDs in advance by means different from a normal bus interface.

Recently, the BIC is usually realized by an LSI, and this autonomous initialization is performed by using a part of the input / output terminals of the BIC-LSI for an ID so that the terminal has a desired ID value. Until now, it has been realized by the initial setting control method that the terminal information is directly taken into the own ID holding control register in the BIC when the power is turned on or the reset is executed. is there.

In the conventional initialization control method described in the above example, IDA
Alternatively, an LSI terminal equal to the number of bits of IDB information and an LSI terminal indicating the type of ID are indispensable.

[Problems to be solved by the invention]

However, in the conventional method, in order to realize the autonomous initial setting of IDA / IDB of BIC by directly inputting from the LSI terminal, at the time of autonomous initial setting of ID, only IDA / IDB needs to be provided for only one of IDA / IDB. Alternatively, the number of terminals equal to the larger number of bits of IDB is required. The information to be set is ID
One terminal for an ID type indication bit for specifying which of A / IDB is required. For example, if IDA / IDB are both 8 bits, a total of 9 terminals are required. For this reason, the BIC has both a common bus and an internal bus interface, and originally requires a large number of LSI terminals, and also requires a large number of LSI terminals for autonomous initialization as described above. Therefore, there is a problem that BIC becomes expensive.

The present invention has been made in view of the above points, and in a control LSI with severe terminal restrictions, the number of terminals required for initial setting to be autonomously performed by hardware can be reduced, and further, setting information can be easily changed. An object is to provide an initialization control method.

[Means for solving the problem]

FIG. 1 shows a principle configuration diagram of the present invention. In the figure, reference numeral 101 denotes an initial setting target integrated circuit, which internally has a serial-parallel conversion means 102, a holding register 103, and a signal generation circuit 104, and has a serial data input terminal 105, a clock output terminal 106, and a shift input / output instruction signal. It has an output terminal 107. Holding register 1 above
03 holds the output parallel data of the serial-parallel conversion means 102.
The signal generating circuit 104 generates at least a shift input / output instruction signal and a clock.

Outside the initialization target integrated circuit 101, a parallel / serial conversion means 108 and a parallel data output means 109 are provided. The parallel-to-serial conversion means 108 is triggered by the shift input / output instruction signal being asserted.
Is set internally, parallel-to-serial conversion is performed in synchronization with the clock, and the obtained serial data is supplied to the serial-to-parallel conversion means 102 via the serial data input terminal 105.

The serial / parallel conversion means 102 performs serial / parallel conversion of the input serial data in synchronization with the clock, and causes the holding register 103 to hold the obtained parallel data as initial setting information.

Further, the parallel data output means 109 is provided in the holding register 1.
03 is parallel data held as initial setting information, a part of the parallel data indicates a setting data type, and
The remaining parallel data outputs parallel data in a data format indicating the contents of the setting data.

[Action]

In the initialization control method of the present invention, since the autonomous initialization input interface of the control LSI is serialized, a serial data signal (one), a clock (one), and a shift input / output instruction signal (one) are required. Only one LSI terminal 105 to 107 is needed, which can contribute to the improvement of the terminal neck of the control LSI.

In addition, the autonomous initial setting information is composed of a setting data type and setting data, and the initial setting information is given as a parallel input of the parallel-serial conversion means 108 provided outside the control LSI, so that it is free and variable according to the purpose. Autonomous initialization becomes possible.

〔Example〕

The method of the present invention is applied to a multiprocessor system having a configuration as shown in FIG. In the figure, 1 is a common bus, 2-
1 to 2-n are n central processing units (CPUs), 3 is a common memory (abbreviated as CM), and the CPUs 2-1 to 2-n and CM3 are connected via a common bus 1.

CPU 2-1 to 2- having interface with common bus 1
n and CM3 each have a built-in BIC,
While performing bus communication for data transmission and reception between PU and CM,
Execute the target program in the CPU.

Fig. 3 shows C to clarify the position of BIC in Fig. 2.
The internal configuration of the PU 2-1 is illustrated as an example. 4 is a BIC, 5 is an external initialization control circuit (abbreviated as INIC), 6 is a serial interface between INIC and BIC, 7 is an internal bus connected to the BIC, 8 Denotes a microprocessor (abbreviated as MPU), and 9 denotes RAM. INIC5 has an ID for autonomous initialization in the BIC control register when the power is turned on or the system is reset.
This is a circuit for transferring data. Once autonomous initialization is completed, it becomes irrelevant for the subsequent execution of programs in the CPU.

A program to be executed by the CPU 2-1 is stored in the RAM 9, and the MPU 8 is a main body for executing the program. The internal bus 7 transfers data within the CPU 2-1, and transmits data from the common bus 1.
It is also used for reception transfer via the BIC4 or transmission transfer from the MPU 8 to the internal bus 7 → BIC4 → common bus 1 → CM3 of FIG. 2 or other CPUs 2-2 to 2-n according to execution of a program instruction. In this case, data shared by the CPUs is stored in the CM3 in FIG.

This embodiment is an example in which each of the BICs 4 in the CPUs 2-1 to 2-n constituting such a multiprocessor system is set as the initialization target integrated circuit 101, and initialization is performed by using the INIC 5. FIG. An embodiment of the system of the present invention will be described with reference to FIGS.

FIG. 4 is a circuit diagram of an embodiment of the method of the present invention.
The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 4, reference numeral 10 denotes a serial-parallel conversion shifter;
-1 is an output signal line (m bit width) of the serial-parallel conversion shifter,
11 is a holding register, 11-1 is an output signal line of the holding register 11, 12 is a pulse generator (abbreviated as PG) for supplying a clock required for each circuit operation, and 13 is a circuit for receiving initial setting data in the INIC5 and the BIC. 13-1 is a data set instruction output signal line for the holding register 11, 13-2 is a reset output signal line of the counter 18, and 14 is a first AND gate. , 15 is a power clamp input signal line, 16 is a reset input signal line, 17 is a second AND gate, 17-1 is an output signal line of the second AND gate, and 18 is a bit input count of the serial-parallel conversion shifter. 2 ^m -1 bit counter, 18-1 is a counter overflow output signal line, 19 is a parallel / serial conversion shifter, 20
Is a third AND gate, 20-1 is an output signal line of the third AND gate, 21 is a two-input selection type DIP switch (DI
PSW), 21-1 to 21-m are output signal lines of DIPSW21,
Reference numeral 22 denotes a ground line connected to one of the two-input selection terminals of the DIPSW 21, and reference numeral 23 denotes a + V volt power supply line connected to the other one of the two-input selection terminals of the DIPSW 21. 6-1 is a serial data line, 6-2 is a clock line, 6-3 is a shift input / output instruction signal (abbreviated as TRNS) line, and these constitute the serial interface 6.

In this embodiment, the required number of terminals of the BIC-LSI itself is reduced by serializing the interface for inputting the IDA / IDB value of the BIC 4 and sending information prepared by an external circuit of the BIC 4.
Also, from an external circuit, an ID type indication bit (1 bit) indicating IDA or IDB and an ID value bit (the number of bits required by the system, for example, 8 bits)
It has a function that can generate and transmit only to BIC4. The actual external circuit is composed mainly of the parallel / serial conversion shifter 19,
The parallel input of the parallel-to-serial conversion shifter 19 is assigned to the ID value and the ID type display bit, and the parallel information is converted to serial information at the completion timing of the power-on or reset execution, and is transmitted to the BIC4 via the ID initial setting serial interface. Configure to send. A basic circuit having such a function is commercially available and can be easily obtained (for example, an SN54 / 74LSI65-IC for 8-bit parallel / serial conversion by Texas Instruments). In BIC4, these
A control register for holding ID information is prepared, and this point is the same in the conventional method and the present embodiment.

In this embodiment, at the time of the autonomous initialization, the ID type display bit and the ID value (IDA / IDB) received in the BIC 4 are stored in the holding register, and the contents of the holding register are used for the subsequent BIC control.

Next, the operation of this embodiment will be described with reference to FIG.
It will be described with reference to the drawings. In FIG. 4, via signal line 15
Power supply clamp input or signal line supplied from outside BIC4
When the reset input supplied from the outside of the BIC 4 via "16" becomes "1", the output 14-1 of the first AND gate 14 becomes "1", and the control circuit 13 sets the output 14-1 to "1". After a certain timing delay, the fifth PG12
In synchronization with the output clock shown in FIG.
The TRNS signal is set to "1" as shown in FIG. 5 (A), the shift function of the parallel / serial conversion shifter 19 and the serial / parallel conversion shifter 10 is enabled, and the reset output signal line 13-2 is set.
Is set to "1" to instruct the counter 18 to reset.
At the same time, when the TRNS signal becomes "1", the second AND gate 17 and the third AND gate 20 output a clock as shown in FIG. 5 (C) to the clock terminals of the shifters 10 and 19. Supply.

The parallel input of the parallel-to-serial conversion shifter 19 is the m-bit output of the DIPSW21, and the two-input selection corresponding to the m-bit output of the DIPSW21 depends on the ground level 22 or the voltage level supplied from the power supply 23 of + V volt through the resistor. is there. The choice is DI
This is set by the m switches of the PSW 21, and the parallel-to-serial conversion shifter 19 is provided with an m-bit input of any combination of “0” or “1”. The actual input of the m-bit parallel data to the parallel-to-serial conversion shifter 19 is performed when the TRNS signal input to the third AND gate 20 via the TRNS signal line 6-3 becomes "1" and the clock is The clock input to the third AND gate 20 via the line 6-2 is performed in synchronization with the clock shown in FIG. 5C output from the AND gate 20 to the signal line 20-1. .

When the TRNS signal becomes “1” (that is, asserted), the set of m-bit data is completed by the parallel / serial conversion shifter 19, and after a certain timing, the parallel / serial conversion shifter 19 outputs the parallel data. The data is transmitted bit-serially in synchronization with the clock via the serial data line 6-1 as shown in FIG. FIG. 5 (D) schematically shows the determination of the shifter data in the parallel / serial conversion shifter 19 by "1".

On the other hand, when the TRNS signal becomes "1", the serial-parallel conversion shifter 10 is in an operable state, and transfers serial data transmitted from the serial data line 6-1 to the output signal line 17- 1 and is received in synchronization with a clock input through the clock. At this time, the counter 18 counts up for each clock by the clock output from the AND gate 17, and when the m bits are counted, the output signal of the overflow output signal line 18-1 is set to "1", and the counter 18 is connected to the control circuit 13 in series. Notifies completion of data reception.

Between the parallel / serial conversion shifter 19 and the serial / parallel conversion shifter 10,
When the transmission and reception of m-bit data are completed, the control circuit 13
Control is performed so that the NS signal becomes "0" (negated) as shown in FIG. 5 (A). At this point, the m-bit parallel data extracted to the m-bit output signal line 10-1 of the serial-parallel conversion shifter 10 is determined as schematically shown by "1" in FIG. 5 (F).

Next, the control circuit 13 supplies the set input signal to the holding register 11 from the output 13-1, and receives the set input signal from the holding register 11.
Captures the m-bit parallel data on the output signal line 10-1 in synchronization with the clock as initial setting information as schematically shown in FIG. 5 (G). Thereafter, the data on the output signal line 11-1 of the holding register 11 is determined as schematically shown by "1" in FIG. 5 (H), and is referred to for various controls inside the BIC.

Next, the data content will be described. The data finally set in the holding register 11 includes ID type display data 1 bit corresponding to the set data type and ID data (m-1) corresponding to the specific data content. Consisting of bits,
The data itself is determined by the state of the switch of the source DIPSW21. For example, if the ID type indicator bit is “0”, the ID data indicates IDB, and the ID type indicator bit is “1”.
In the case of, the ID data is defined to mean IDA.

As described above, in the embodiment of the present invention, the ID type display bit and the
Any ID data of (m-1) bits of IDB / IDA can be autonomously initialized.

BIC4 thereafter refers to the contents of the holding register 11, and
If the content of the ID type display bit specifies IDB, the bus access from the internal bus 7 in FIG. 3 is accepted. At this time, the remaining (m-1) -bit data of the holding register 11 is transferred to the BIC4. It interprets the IDB as its own IDB, compares it with the IDB sent from the internal bus 7, accepts the access if it matches, and operates without response if it does not match.

On the other hand, when the ID type indication bit specifies IDA, the access from the common bus 1 in FIG. 3 is accepted, and the operation corresponding to the match / mismatch is performed in the same manner as described above. BIC4 is
By receiving these bus accesses,
The so-called "initial setting" of writing the contents of other various control registers necessary for the transfer control operation of the BIC 4 becomes possible. Note that m can be selected to any bit width in accordance with the requirements of the system, but it is generally considered that about 8 bits is sufficient (ID
Is 7 bits and 2 ⁷ = 128 can be specified).

In the above-described embodiment, the case where the DIPSW 21 is used as the parallel input means of the parallel-to-serial conversion shifter 19 has been described.
If it is better to fix the input depending on the application, soldering processing may be performed so that each parallel input terminal of the parallel-to-serial conversion shifter 19 is pulled up or down.

In the embodiment of the present invention, the case where only the ID of BIC4 is autonomously initialized has been described.
By changing the definition of the m-bit content to be loaded into 11, other control information can be set, and other control LSI
It is clear from the above that the present invention can be easily applied to the autonomous initialization of the control information.

〔The invention's effect〕

As described above, according to the method of the present invention, the conventional LSI
Compared to the control method of direct input from the terminals, only three terminals for the serial interface are required, so the number of required LSI terminals can be greatly reduced. Also, the setting information contents for the parallel input of the external parallel-to-serial conversion shifter Can be varied,
Not only the ID but also various kinds of control information can be freely and variably initialized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a diagram showing a configuration example of a multiprocessor system to which the present invention is applied, FIG. 3 is a block diagram of a CPU in FIG. 2, and FIG. FIG. 5 is a circuit diagram of an embodiment of the method of the invention, and FIG. 5 is a time chart for explaining the operation of FIG. 4 Bus connection control circuit (BIC), 5 External initialization control circuit (INIC), 10 Serial-parallel conversion shifter, 11,103 Holding register, 19 Parallel serial shifter, 21 Dip switch (DIPSW), 101 Initial setting target integrated circuit, 102: serial-parallel conversion means, 104: signal generation circuit, 105: serial data input terminal, 106: clock output terminal, 107: shift input / output instruction signal output terminal.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-58109 (JP, A) JP-A-61-289452 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 1/24

Claims (2)

(57) [Claims] 1. A serial / parallel converter, a holding register for holding output parallel data of the serial / parallel converter, and a shift input / output for controlling at least a shift operation of the serial / parallel converter in an integrated circuit to be initialized. A signal generating circuit for respectively generating an instruction signal and a clock, a serial data input terminal to the serial-parallel conversion means, an output terminal for the clock, and an output terminal for the shift input / output instruction signal; A parallel / serial conversion means for controlling the operation of the shift input / output instruction signal outside the circuit and for parallel / serial conversion of external input parallel data based on the clock, and a parallel / serial conversion means for outputting parallel data to the parallel / serial conversion means. Data output means, and when the shift input / output instruction signal is asserted,
The parallel / serial conversion means sets parallel data from the parallel data output means therein, performs parallel / serial conversion in synchronization with the clock, and converts the serial data to the serial / parallel conversion means via the serial data input terminal. An initial setting control method, wherein parallel data input and serial data converted by the serial / parallel conversion means in synchronization with the clock is held in the holding register as initial setting information. 2. The parallel data output means according to claim 1, wherein said parallel data is held as initial setting information in said holding register, wherein a part of said parallel data indicates a set data type, and a remainder of said parallel data is 2. The initial setting control method according to claim 1, wherein parallel data in a data format indicating the contents of the setting data is output.