JP2785708B2 - Logic simulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method, and more particularly to a logic simulation method used as an event-driven delay simulation.

[0002]

2. Description of the Related Art In a conventional logic simulation method of this type, as one method, a method of assigning a delay amount to a gate which is a component of an internal logic macro is used. According to this logic simulation method, when delay data from an input pin to an output pin of an internal logic macro is to be reflected by a delay simulation, a delay value is forcibly assigned to each gate, or Further, there is no method other than modeling the internal logic macro itself as one large gate and expressing the delay value. As described above, in the method of forcibly assigning the delay value, it is necessary to appropriately distribute the delay value to the gates. Even if it is possible to accurately model the delay value of one path, it is difficult to accurately model the other paths, which often results in distortion. It is a fact. In order to solve this problem, delay values are conventionally assigned by generating dummy gates. However, in this method, it is necessary to perform logic simulation by the number of dummy gates, and the time required for this is required. Is increased.

As another conventional method, there is a method of modeling as one large gate. In this method, it is easy to assign a delay value and it is possible to reduce an error. Despite the advantages, modeling is becoming more and more difficult as the number of gates of internal logic macros in semiconductor integrated circuits is increasing significantly. An example of the prior art of this method is disclosed in
No. 2673 proposes a "logic circuit simulator". In the proposal by the patent publication, the output value and the delay value of the internal logic macro are all stored in a storage area in the ROM for each combination of input values, and the value of the address of each of these storage areas is stored. A technique for performing a logical operation by matching a block number with a binary number expressed by connecting a block number and each input value is disclosed. Also, originally, as an internal logic macro, in many cases, a logic connection designed and verified before that was diverted and the timing part was changed and used as one independent circuit, and this modeling method was used The delay allocation method has the disadvantage that the logical part must be rewritten. For this reason, the diversion or use of the conventional design assets is limited.

[0004] A procedure of a conventional logic circuit simulation will be described with reference to FIG. First, in processing step 601, the input pattern signal input to the input pin is changed. Next, in processing step 602, the presence / absence of an event remains is checked. If there is a remaining event, the flow shifts to processing step 606 to perform event fetch processing. Processing step 60
If there is no remaining event in 2, the presence or absence of schedule data is checked in processing step 603, and if there is schedule data, event registration processing is performed in processing step 605.
Next, in a processing step 606, an event fetch process is performed similarly. When the event extraction processing is performed in processing step 606, processing step 607
Then, the gate to be operated is specified with reference to the logical connection information, and a predetermined operation process is performed. Next, in processing step 608, it is checked whether or not an event has occurred according to the calculation processing result in processing step 607. If an event has occurred, processing step 609 is performed.
In, the scheduling process is performed in the processing step 610 with reference to the delay value allocated to the gate, and the process returns to the processing step 602. If the event disappears in step 608 without occurrence of an event, the scheduling process is not performed, and
Return to 2. As described above, the logic simulation is repeatedly performed until the event and the schedule data are lost through the processing steps 602 and 603. When the event and the schedule data are lost, the logic simulation ends ( EXIT 604).

[0005]

In the above-described conventional logic simulation method, in the case of the first method in which the delay value is forcibly assigned to the gate of the component of the logic macro described above, the delay value is not changed. There is a drawback that errors are likely to occur in value assignment, the simulation time increases by the number of dummy gates, and the time required for logic simulation increases. In the case of the second method of modeling as one large gate, Has the disadvantage that modeling becomes more difficult as the number of gates increases, and the use or use of logic parts by past design assets is limited.

[0006] The problems of the prior art technique will be clarified below, taking the case of the logic circuit shown in FIG. 2 as an example. In FIG. 2, for convenience of explanation, numerals are added to the pins, but the pins 1, 2, 3,.
The inside of the rectangle surrounded by 7, 8 and 9 is a so-called internal logic macro 22. The four gates, which are components of the internal logic macro 22, are A, B, C, and D, respectively. FIG. 3 shows a delay database from the input pin to the output pin in the internal logic macro 22.

In the case of the first method, delays are allocated to the gates A, B, C and D according to the delay database shown in FIG. For example, as shown in FIG. 3, in path 1, a delay value 6 is assigned to pins 1 to 7, and in path 2, a delay value 10 is assigned to pins 1 to 8. In the path 3, a delay value 10 is assigned from the pin 3 to the pin 8. As a result, in the path 4, the delay value from the pin 3 to the pin 9 should be 6, but since the delay value is 7 in the delay database, the dummy gate is connected between the pin 5 and the pin 9. Insert and delay 1 is assigned.
This insertion gate requires extra arithmetic processing in the simulation, which increases the processing time.

In the second method, when the logic circuit shown in FIG. 2 is used as an example, description conversion processing for describing four gates as one gate is required. For example, in the case of Japanese Patent Application Laid-Open No. 3-152873, all combinations of three inputs and three outputs are RO
It is necessary to store the data in a storage area in M and to provide delay data in a form corresponding to each combination.
In other methods, when connection information of a circuit held as four gates is treated as one gate,
The conversion or rewriting of the connection necessarily occurs, resulting in an increase in processing time.

Therefore, in both the first method and the second method, modeling and conversion have become practically difficult as the circuit scale increases. Therefore, it is an object of the present invention to realize a pin-to-pin delay simulation based on an existing logical connection and a delay database from an input pin to an output pin.

As a method for realizing a pin-to-pin delay simulation based on an existing logical connection and a delay database from an input pin to an output pin, there is another method proposed in Japanese Patent Application Laid-Open No. 3-250371. However, this proposal has problems in the following points. That is, Japanese Patent Laid-Open No. 3-2
In Japanese Patent No. 50371, a time wheel for controlling the event propagation in the internal logic macro and a time wheel for controlling the event propagation between the internal logic macros are individually provided.
The simulation time tends to increase. Although a method of storing the delay of the block in advance at the input terminal of the internal logic macro has been adopted, it cannot be handled as the circuit becomes large and the path becomes complicated,
There is a drawback that the risk of the time required for searching for the delay being a bottleneck is present.

SUMMARY OF THE INVENTION Therefore, the present invention provides
A logic circuit model equivalent to a logic circuit consisting of a number of gates
A time series change of the input pattern signal
At each time, the input / output pin of each gate
Schedule that indicates the change that occurs, that is, the time of the event occurrence
Event registration based on the
Until the events that have been taken out are
Operation of each gate with reference to logical connection information of a logical circuit
Processing, and the event of the next time of the input / output pin of each gate is performed.
Check the event occurrence, and check each of the gates where the event occurred
Of the schedule, and based on the delay information,
Perform scheduling processing to set schedule data,
Logic simulation for displaying and outputting the operation result of the logic circuit
The event occurrence at each of the times.
After the check, the logic that has already been verified
As an internal logic macro used as one of the circuit elements
Search BOUNDARY information indicating input / output pin data
The output pin of each gate where an event occurs
If the output pin is not an output pin as
Account registration. In addition, the event registration
The event that occurred,
The change time, the state value change information, and the propagation source information are based on the internal theory.
Is stored as pin progress information in the
Together with the BOUNDARY information after the
Searched.

[0011] In the seventh processing step, a delay value between corresponding pins may be searched by referring to a predetermined delay database via a hash table.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing a processing procedure in one embodiment of the present invention. Hereinafter, for the logic circuit of FIG.
As an input signal, input 1 in FIG. 5A and FIG.
The processing procedure according to the present embodiment will be described by taking as an example a case where the input 2 is applied. In addition, FIG.
(D), (e), (f), (g), (h) and (i)
Is a timing diagram of the signals at pins 1, 2, 3, 4, 5, 6, and 8 corresponding to the application of input 1 and input 2, respectively. FIG.
It is a figure which shows the change time corresponding to 2, 3, 4, 5, 6, and 8, the pin state value, the BOUNDARY information, and the pin table which stores the information of a propagation source. The BOUNDARY information in this pin table includes an internal logic macro 2
Information including the distinction between the two input pins and the output pins is stored. In the propagation source, information indicating which input pin of the internal logic macro 22 the latest event has passed is stored as the simulation proceeds.
In the pin table of FIG. 4, BOUNDARY
"Input" in the column represents an input pin of the internal logic macro 22, "output" represents an output pin, and "-" represents other things. This BOUNDARY information is information obtained by circuit connection development processing which is preprocessing of logic simulation.

Referring now to FIGS. 1, 2 and 5,
Focusing on the internal logic macro, a simulation procedure by signal application will be described. In the example of the logic circuit shown in FIG.
(See FIG. 5). As a result, in the processing step 101, in response to the application of the input 1, a RISE event occurs at the input pin 1 of the internal logic macro 22 via the inverter 21 at the time T1 (500 in FIG. 5C). ), And the internal logic macro 2
A RISE event occurs at the input pin 2 at time T2 (see 501 in FIG. 5D). At this point, in process step 102, a check is made to see if any event remains. In this example, the time T
Since the RISE event has been registered at 1 and at time T2, YES is determined, that is, there is a remaining event, and the routine proceeds to the processing step 106, where the event extracting process is performed. In this case, first, R at early time T1
An ISE event is retrieved. The propagation destination of this event is given by the logical connection information. In this example, since the propagation destination is the gate A as is clear from FIG. 2, the logical gate operation by the gate A is performed in the next processing step 107. Done. Then processing step 10
At step 8, the presence or absence of the occurrence of an event is checked. In this example, the input value to the gate A changes from the combination of 0 and 0 to the combination of 0 and 1 due to the RISE event. Is 0, the state value at the pin 4 of the gate A does not change, and the event disappears. Therefore, it is determined that no event has occurred, and the process returns to the processing step 102. Next, in the processing step 106, the RISE event at the time delay T2 is extracted. In this case, the combination of the input values to the gate A due to this event is 1 and 1, and as a result of the arithmetic processing in the processing step 107, a RISE event occurs at the pin 4 at the time T3 (FIG. 5 (f)).
502)). That is, it is determined in step 108 that an event has occurred, and the process proceeds to step 109. In processing step 109, the BUN
Referring to the DARY information, pin 4 is
Therefore, it is determined that the event is not output information, and an event registration process corresponding to the event is performed in processing step 110. In this event registration process, information such as a change time (T3) and a change in state value (RISE) are stored, and the change times of pins 1 and 2 which are the input sources of the gate A are compared. It is determined that the pin 2 which is the input source whose change time is later is the trigger of the event of the pin 4, and 2 is stored as the propagation destination of this event. In this case, since pin 2 is an input pin of the internal logic macro 22, it is stored as it is (401 in FIG. 4).
See). Then, the process returns to the process of checking whether or not the event remains in the processing step 102.

In response to the determination that there is an event remaining in processing step 102, in processing step 106,
The event of pin 4 that has just been registered is extracted, and then in processing step 107, the logical connection information
The arithmetic processing by the gate B and the gate D is performed,
By this operation, the event disappears without changing the pin 5 of the gate D, and the pin 6 of the gate B changes from 1 to 0 at time T4 (see 503 in FIG. 5H). That is, it is determined in step 108 that an event has occurred, and the process proceeds to step 109. In the processing step 109, referring to the BUNDARY information, since the pin 6 is not the output pin of the internal logic macro 22, it is determined that the event is not the output information as in the case described above. In, an event registration process corresponding to the event is performed. Since this gate B has one input, the pin 6
That the event is triggered by the pin 4 means that it is not necessary to look at the change time information. As is clear from FIG. 4, since the BUNDARY information of the pin 4 is “−”, the number 2 stored in the transmission source information is copied to the transmission source information of the pin 6 (see 402 in FIG. 4). .

Then, returning to the processing step 102 again,
The presence or absence of the event is checked. In response to the determination that the event remains, in step 106, the event of the pin 6 that has just been registered is extracted, and then in step 107, the arithmetic processing by the gate C is performed based on the logical connection information. By this operation, the pin 8 of the gate C changes from 0 to 1 at the time T5 (see 504 in FIG. 5I). That is, it is determined in step 108 that an event has occurred, and the process proceeds to step 109. In the processing step 109, referring to the BUNDARY information, since the pin 8 is the output pin of the internal logic macro 22, (4 in FIG. 4)
03), the event is determined to be output information, and the process proceeds to processing step 111. In processing step 111, the change time of the input source is checked.
The trigger of the RISE event of the pin 8 is the event of the pin 6, and the propagation source information gives that the event of the pin 6 is caused by the propagation of the event from the pin 2 (see 403 in FIG. 4). Therefore, the delay data from pin 2 to pin 8 is referred to from the delay database. In this case, in the present invention, in order to perform this search at high speed, the delay data is referred to from the delay database 12 via the hash table 11 . Next, in processing step 112 , scheduling data is processed according to the delay data, and after the processing, a predetermined simulation result is output.

Then, the process returns to the processing step 102. At this point, since there is no remaining event and no scheduling data exists, the simulation process ends (EXIT 104).

[0018]

As described above, according to the present invention, a logic circuit model equivalent to a logic circuit is constructed on a computer, an input test sequence signal for the logic circuit is applied to the logic circuit model, and a logic simulation is performed. Is applied to a logic simulation method of displaying and outputting the operation result, and has pin progress information of an event propagating in the circuit of the internal logic macro, and corresponds to an event propagating at an output pin of the internal logic macro. By searching the inter-pin delay database of the internal logic macro with reference to the pin progress information and assigning a delay with reference to the search data, a logic simulation that reflects the pin-to-pin delay without error is performed. Can be performed, existing logic circuit connections can be used, and no extra arithmetic processing is required. In order, there is an effect that it is possible to compress the processing time required for logic simulation.

[Brief description of the drawings]

FIG. 1 is a flowchart of a logic simulation according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a logic circuit to which the present embodiment is applied.

FIG. 3 is a diagram illustrating an example of a delay database according to the present embodiment.

FIG. 4 is a diagram illustrating a pin information table of a logic circuit example to which the present embodiment is applied;

FIG. 5 is a timing chart showing an operation of an example of a logic circuit to which the present embodiment is applied.

FIG. 6 is a flowchart of a logic simulation in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Hash table 12 Delay database 21 Inverter 22 Internal logic macro 101-112, 601-610 Processing steps

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50

Claims (2)

(57) [Claims] 1. A logic circuit comprising a plurality of gates and the like.
A costly logic circuit model on a computer
At each time, corresponding to the time series change of the signal, each of the gates
Changes that occur at the input / output pins, that is, when an event occurs
Event registration based on schedule data
This registered event is taken out in order and remains
Until the logic connection information of the logic circuit is
Performs the arithmetic processing of each gate, and the input / output pins of each gate
Check the event occurrence at the next time of the
Search for the delay information of each of the gates,
A schedule for setting the schedule data based on the schedule
And output and display the operation result of the logic circuit.
In the logic simulation method, after checking the occurrence of the event at each time, a plurality of
As one of the verified logic circuit elements consisting of gates etc.
Input / output pin data as internal logic macro used
Search for the indicated BOUNDARY information and an event occurred
The output pin of each of the gates serves as the internal logic macro.
When not an output pin, register an event at the next time.
A featured logic simulation method. 2. When an event is registered, an event occurs.
Change time and status value of the event corresponding to the pin
The change information and the propagation source information correspond to the pins in the internal logic macro.
Stored as progress information to check for the occurrence of the event
The logic simulation method according to claim 1 , wherein the logic simulation method is searched later together with the BOUNDARY information .