JP2795124B2 - Display method of halftone image on display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a display panel such as a plasma display panel (hereinafter simply referred to as PDP) or a liquid crystal display panel (hereinafter simply referred to as LCD). For example, one field display period or one frame display period is time-divided into a display period (for example, a subfield period) of a bit number N (N is an integer of 2 or more) corresponding to a display gradation, and a display pulse in each divided display period is displayed. The present invention relates to a method of displaying a halftone image of a video signal by weighting a number corresponding to each bit.

[0002]

2. Description of the Related Art Conventionally, this type of halftone image display method includes 605 to 6 of JAPAN DISPLAY '92.
08 "S16-2 A Full Color"
AC Plasma with 256 Gray S
The method described as "call" was known.

That is, in the case of displaying a halftone with 8 bits and 256 gradations, as shown in FIGS. 3A and 3B, one field display period 1F for each pixel (for example, about 16 pixels). 6 ms) for eight sub-field periods SF1
To SF8 in each subfield period SF1,
, SF8 is further divided into an address period AP and a display period SP, and the display period SP is 1: 2: 4: 8:.
The weighting of the ratio of 28 is performed.

For example, if two display pulses are allocated to the display period SP of the subfield period SF1, eight display pulses are assigned to the display period SP of the subfield periods SF3 and SF8.
(= 2 × 4) 256 (= 2 × 128) display pulses are allocated. The address period AP is constant regardless of the subfield periods SF1,.
5 ms), which depends on the display panel, and consists of steps 1, 2, 3, and 4.

In the period of Step 1, in order to eliminate the influence of the immediately preceding display period and to make all the discharge dots have the same state, X Sustain of the dot matrix type PDP is used.
An erase pulse is applied to the n-electrode. In the period of Step 2, the X Sustain electrode of the PDP and Y1, Y
2,..., Y480 A write pulse is applied between the Sustain electrodes, and some of the ions are stacked on the surface of the phosphor by the address electrode maintained at 0V. In the period of Step 3, XSus is used to remove wall charges.
An erase pulse is applied to the tail electrode. In the period of step 4, a scan pulse is applied to the address electrodes of the PDP.

[0006]

However, in the above-described conventional halftone image display method, if the number of subfield periods to be time-divided is increased in order to increase the display gradation, the address period AP is increased accordingly. As the number increases, the display period SP shortens (the number of display pulses decreases),
The maximum value of the display luminance decreases.

For this reason, on a dark screen where the APL (average picture level) of the video signal is small, there is a problem that the contrast ratio is lowered and the display quality is deteriorated. In a display panel (for example, PDP), APL
There is a problem that the difference between the power consumption when the power is large and the power consumption when the power is small is large, and the load on the power supply increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems. Even in a dark screen where the APL of a video signal is small, it is possible to prevent a decrease in contrast ratio and improve display quality, and to increase the APL. It is an object of the present invention to provide a method for displaying a halftone image on a display panel, which can reduce the difference between the power consumption when the display is small and the power consumption when the display is small.

[0009]

According to the present invention, one screen display period for each pixel of a display panel is time-divided into a display period of a bit number N (N is an integer of 2 or more) corresponding to a display gradation, In a method of displaying a halftone image of a video signal by weighting the number of display pulses in each divided display period in accordance with each bit, an AP of the video signal may be displayed.
By comparing L (average video level) with a set level, the brightness of the display image is divided into m stages (m is an integer of 2 or more), and the number of display gradations increases as the brightness of the display image increases. Further, the halftone image is displayed by switching the number of divisions N according to the brightness level of the display image.

[0010]

By comparing the APL of the video signal with the set level, the brightness of the displayed image can be increased by m levels (for example, 3 levels).
It is divided into Corresponding to the brightness of the divided m-stage display image, the number of divisions (for example, the number of subfields) N in one screen display period (for example, one field display period) increases as the brightness of the display image increases. For example, N ₁ (for example, 6), N ₂ (for example, 7), and N so that the display gradation becomes large (for example, the display gradation becomes 64, 128, and 256).
₃ (for example, 8).

For this reason, on a dark screen where the APL becomes small, the number of divisions (for example, the number of subfields) N is switched in a direction of decreasing (for example, from 8 to 6), so that the number of address periods AP becomes small. The display period is lengthened (the number of display pulses is increased), the maximum value of the display luminance does not decrease, and the contrast ratio does not decrease.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a halftone image display method according to the present invention will be described below with reference to FIGS. FIG. 1 shows a schematic configuration of a main part of an apparatus for performing the method of the present invention. In FIG. 1A, R, G, and B signals represent digital signals of 8-bit gradation (256 gradations) of red, green, and blue as video signals. Reference numeral 10 denotes a gamma correction / level conversion circuit. The gamma correction / level conversion circuit 10 is configured to perform gamma correction and level conversion of R, G, and B signals based on a control signal from a control circuit 20 described later. Have been.

On the output side of the gamma correction / level conversion circuit 10, a field memory 12, a PDP driver 14, and a dot matrix type PDP 16 as an example of a display panel are sequentially connected. The Y signal is a luminance signal, and the luminance signal Y is created based on, for example, R, G, and B signals. An integration circuit 18 is configured to output an APL (average video level) by integrating the Y signal.

Reference numeral 20 denotes a control circuit.
By comparing the APL from the integration circuit 18 with a preset set level, the brightness of the display image is divided into three large levels, and the corresponding control signal is output to a display timing signal output circuit 22 described later. In addition, each of these three stages is further divided into three stages, and the corresponding control signals l, m, h, l, m, h,
It is configured to output l, m, h to the γ correction / level conversion circuit 10.

That is, the control circuit 20 determines that the APL from the integration circuit 18 is low (eg, less than 3.5%), medium (eg, 3.5% or more and less than 7%) within a range of less than 10%. When it is high (for example, 7% or more and less than 10%), control signals l, m, and h are output, and 10% or more and 2
When the signal is low (for example, 10% or more and less than 15%), medium (for example, 15% or more but less than 20%), or high (for example, 20% or more and less than 25%) within the range of less than 5%, the control signals l, m, h, and outputs low (e.g., 25% or more and less than 50%) or medium (e.g., 50% or more and
When it is less than 5%) and high (for example, 75% or more), the control signals l, m, and h are respectively output.

The gamma correction / level conversion circuit 10
Are control signals l, m, h from the control circuit 20.
Based on the conversion patterns l, m,
As shown in FIG. h, R, G,
The B signal is configured so as to perform γ correction (correction of non-linearity of brightness) and to perform level conversion to R, G, and B signals for 6-bit gradation and output.

The gamma correction / level conversion circuit 10
Are control signals l, m, h from the control circuit 20.
Alternatively, based on the control signals l, m, h, the conversion patterns l, m, h, or l in FIG.
As shown in m and h, R, R,
G and B signals are γ-corrected and 7-bit gradation or 8
It is configured to convert the level into R, G, B signals for bit gradation and to output the signals.

Reference numeral 22 denotes a display timing signal output circuit. The display timing signal output circuit 22 mainly includes a subfield number counter 24 and a display pulse number counter 26, and includes a control signal from the control circuit 20,
, The display timing pulse is output to the display control circuit 28 at the timing shown in FIGS. 2 (a), 2 (b) and 2 (c).

That is, the subfield number counter 24 outputs pulses corresponding to the subfield numbers 6, 7 and 8 based on the control signal from the control circuit 20, and the display pulse number counter 26 outputs 6, based on the output signal from the field number counter 24,
The number of display pulses corresponding to the 7 or 8 bit gradation is output to the display control circuit 28, and the carry output is output to the subfield number counter 24 as a reset signal.

The display control circuit 28 includes a display timing pulse from the display timing signal output circuit 22,
, The display data to be written to the field memory 12 is controlled to data of 6, 7, or 8 bit gradation.

The display timing of the display timing pulse is, as shown in FIG. 2 (a), 1F (one field display period) divided into six subfield periods SF1 to SF6.
In each subfield period SF1, SF2, S
F3,..., SF6 further include AP (address period) and SP
1 (display period 1), AP and SP2, AP and SP3,.
AP and SP6 are time-divided, and these display periods SP1, S
14, 28, 56,..., 4 for P2, SP3,.
48 display pulses are assigned, and 1: 2: 4:...: 32
Is weighted. For the sake of convenience, the number of display pulses is set to 1.5 ms and 7.5 μs, respectively, for the AP and display pulse periods determined uniquely by the PDP 16.
F is determined as 16 ms.

That is, since 1F is time-divided into 6 SFs, the address period in 1F is 9 ms (= 1.5 m).
s × 6), and the display period within 1F is 7 ms (= 16 m).
s-9 ms). For this reason, the number of display pulses of the unit weight when weighting 64 (6 bits) in the 7 ms display period is 14 (= 7 × 1000/64/7.
5). The AP includes steps 1, 2, 3, and 4, similarly to the conventional example described with reference to FIG.

The display timing of the display timing pulse is, as shown in FIG. 2B, 1F divided into seven subfield periods SF1 to SF7, and each subfield period SF1, SF2, SF3,. The display periods SP1, SP2, SP3,...
, 320 display pulses are assigned, and 1: 2: 4:
..: Weighting is performed at a ratio of 64. The number of the display pulses is determined as follows.

That is, since 1F is time-divided into 7 SFs, the address period in 1F is 10.5 ms (=
1.5 ms × 7), and the display period within 1F is 5.5 m.
s (= 16 ms-10.5 ms). Therefore, the number of display pulses of the unit weight when weighting 128 (7 bits) in the 5.5 ms display period is 5 (=
5.5 × 1000/128 / 7.5).

The display timing of the display timing pulse is, as shown in FIG. 2C (substantially the same as in FIG. 3A), where 1F is 8 subfield periods SF1 to SF.
F8, each subfield period SF1, SF
, SF3,..., SF8 display periods SP1, SP2, S
.., 256 are assigned to P3,..., SP8, and weighted at a ratio of 1: 2: 4:. The number of the display pulses is determined as follows.

That is, since 1F is time-divided into 8 SFs, the address period within 1F is 12 ms (= 1.5
ms × 8), and the display period within 1F is 4 ms (= 16
ms-12 ms). For this reason, the number of display pulses of the unit weight when weighting 256 (8 bits) in this 4 ms display period is 2 (= 4 × 1000/256).
/7.5).

Next, the operation of the above embodiment will be described. (A) The integrating circuit 18 integrates the Y signal to obtain A
PL, and the control circuit 20 compares the APL with a preset setting level, thereby obtaining control signals l, m, h, l,
m, h, l, m, and h are output to the gamma correction / level conversion circuit 10 and a control signal is output to the display timing signal output circuit 22.

(B) The gamma correction / level conversion circuit 10 controls the control signals l, m, h, l,
Based on m, h, l, m, h, the entered R,
G and B signals are γ-corrected and the luminance level is converted. That is, when the APL is low (for example, less than 3.5%), medium (for example, 3.5% or more and less than 7%), or high (for example, 7% or more and less than 10%) within the range of less than 10%, FIG.
As shown in the conversion patterns l, m, and h of (b), the input R, G, and B signals for 8-bit gradation are γ-corrected, and the luminance levels are converted to R, G, and B signals for 6-bit gradation. And output.

An APL of 10% or more and less than 25% is low (for example, 10% or more and less than 15%), medium (for example, 15% or more and less than 20%), and high (for example, 20% or more and less than 25%).
%), The conversion pattern l in FIG.
As shown in m and h, the input R, G, and B signals for 8-bit gradation are γ-corrected, and the level is converted to R, G, and B signals for 7-bit gradation or 8-bit gradation and output. .

When the APL is low (for example, 25% or more and less than 50%), medium (for example, 50% or more and less than 75%), or high (for example, 75% or more) within the range of 25% or more, FIG. As shown in the conversion patterns l, m, and h in FIG. 7B, the input R, G, and B signals for 8-bit gradation are γ-corrected and level-converted into R, G, and B signals for 8-bit gradation. Output.

(C) On the other hand, the display timing signal output circuit 22 has a display having display timings as shown in FIGS. 2A, 2B and 2C based on the control signal from the control circuit 20. Are output to the display control circuit 28. That is, when the APL is less than 10%, a display timing pulse having a maximum display pulse number of 896 having a display timing of 6-bit gradation as shown in FIG.

When the APL is 10% or more and less than 25%, the display control pulse having the maximum display pulse number 640 having the display timing of the 7-bit gradation as shown in FIG. Input to the circuit 28. When the APL is 25% or more, a display timing pulse having a maximum display pulse number 512 having an 8-bit gradation display timing as shown in FIG. 2C is input to the display control circuit 28.

(D) The display control circuit 28 includes a display timing pulse from the display timing signal output circuit 22,
, The display data to be written to the field memory 12 is controlled to data of 6, 7, or 8 bit gradation.

(E) As described above, the γ correction and the level conversion are performed, and the gradation conversion is performed.
2 is sent to the PDP 16 via the PDP driver 14. Therefore, the PDP 16 displays an image with display characteristics similar to the conversion pattern shown in FIG.

That is, when the APL is low, medium, or high within a range of less than 10% (when the screen is dark), the PDP 16
Are displayed with display characteristics similar to the conversion patterns l, m, and h in FIG. When the APL is low, medium, or high within the range of 10% or more and less than 25%, the PDP 16
Are displayed with display characteristics similar to the conversion patterns l, m, and h in FIG. When the APL is low, medium, or high within the range of 25% or more, the display is performed with display characteristics similar to the conversion patterns 1, m, and h in FIG.

In the above embodiment, the APL is divided into three stages, and the display gradation is switched between three stages of 6, 7, and 8 bit gradations in accordance with this. However, the present invention is not limited to this. Instead, the APL is divided into m stages (m is an integer of 2 or more), and the display gradation is switched to m stages of different bit gradations in accordance with this, and the display gradation increases as the brightness of the display image increases. What is necessary is just to increase the number. For example, the APL may be divided into four stages, and the display gradation may be switched to four stages of 5, 6, 7, and 8-bit gradations in accordance with this.

In the above embodiment, three types of conversion patterns for gamma correction and level conversion of a video signal at each of the three levels of brightness of a display image are set according to the APL size in each level, and adjacent patterns are set. The change of the brightness level at the time of switching between the steps to be performed is made smooth, but the present invention is not limited to this, and the conversion pattern of the γ correction and the level conversion is changed according to the size of the APL in each step. A plurality of types (for example, two types) other than the three types may be provided to smoothly change the luminance level when switching between adjacent stages, or γ.
Only one conversion pattern for correction and level conversion may be provided for each stage.

In the above embodiment, for each of the three levels of brightness of the display image, the gamma correction and level conversion of the video signal are performed to simultaneously correct the nonlinearity of the brightness. However, the present invention is not limited to this, and the present invention can be applied to a device in which the γ correction is omitted.

[0039]

As described above, the method for displaying a halftone image on a display panel according to the present invention is based on the APL of a video signal.
Is compared with a set level to divide the brightness of the display image into m stages (m is an integer of 2 or more), and the brightness of the display image is increased so that the brightness of the display image increases as the brightness of the display image increases. The halftone image is displayed by switching the number of divisions (for example, the number of subfields) N of one screen display period (for example, one field display period) according to the stage, so that the number of divisions (for example, subfields) The number N is switched to, for example, 6, 7, and 8 so that the number of display gradations increases as the brightness of the display image increases (for example, the number of display gradations becomes 64, 128, and 256).

For this reason, in a dark screen where the APL is small, the number of divisions (for example, the number of subfields) N is switched (for example, from 8 to 6) to a smaller number, and the number of address periods AP becomes smaller. Even on the screen, the maximum value of the display luminance does not decrease and the contrast ratio does not decrease.
That is, the display image quality can be improved as compared with the conventional example. Further, when the APL is large, the number of display gradations is controlled in the direction of decreasing the display luminance, and when the APL is small, the number of display gradations is controlled in the direction of increasing the display luminance. The difference in power consumption when the power consumption is small can be reduced and averaged, and the load on the power supply can be reduced.

[Brief description of the drawings]

FIGS. 1A and 1B show an embodiment of a method for displaying a halftone image on a display panel according to the present invention, wherein FIG. 1A is a schematic configuration diagram of a main part of an apparatus for performing the method of the present invention, and FIG. γ
FIG. 4 is a characteristic diagram illustrating the operation of the correction / level conversion circuit.

FIGS. 2A and 2B are explanatory diagrams for explaining display timing of a display timing pulse output from the display timing signal output circuit of FIG. 1A, wherein FIG. 2A shows a display timing of a 6-bit gray scale, and FIG. 7C shows the display timing of the 7-bit gradation, and FIG. 7C shows the display timing of the 8-bit gradation.

FIG. 3 is an explanatory diagram illustrating display timing of a display timing pulse in a conventional example.

[Explanation of symbols]

10: γ correction / level conversion circuit, 12: Field memory, 14: PDP driver, 16: PDP, 18: Integration circuit, 20: Control circuit, 22: Display timing signal output circuit, 28: Display control circuit, 1F: 1 Field display period (one screen display period), APL: average image level, PDP: plasma display panel (one example of display panel), R, G, B: digital R, G, B signals (one example of video signal) SF1 to SF8... Subfield period (an example of a divided display period);

Claims (3)

(57) [Claims] 1. The method according to claim 1, wherein each pixel of the display panel has one pixel.
The screen display period is set to the number of bits N (N is 2
In the method of displaying a halftone image of a video signal by time-dividing into display periods of the above integers and weighting the number of display pulses in each divided display period in accordance with each bit, the APL (average) By comparing the image level with the set level, the brightness of the display image is divided into m stages (m is an integer of 2 or more), and the display is performed such that the brighter the display image, the greater the number of display gradations. A halftone image displaying method for a display panel, wherein a halftone image is displayed by switching the number of divisions N according to the brightness level of the image. 2. A plurality of types of level conversion patterns of video signals at each of m levels of display image brightness in accordance with the size of the APL in each stage in order to smoothly switch between adjacent stages. Claim 1 provided
A method for displaying a halftone image on a display panel according to the above. 3. The halftone image of a display panel according to claim 2, wherein the level conversion pattern of the video signal at each of the m levels of brightness of the display image is also used for γ correction for correcting the non-linearity of the brightness. Display method.