JP2796657B2 - Manufacturing method of semiconductor wafer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor wafer, for example, a method of manufacturing a semiconductor wafer for reducing warpage of a silicon wafer having an epitaxial layer used for a bipolar power IC or the like.

[0002]

2. Description of the Related Art Conventionally, a silicon wafer for forming a bipolar integrated circuit having an epitaxial film has been known as an N wafer.
Silicon wafer obtained by slicing an N-type silicon single crystal rod doped with antimony, which is a type impurity at a high concentration, and further mirror-polishing the silicon wafer (thickness: 600 to 700 μm)
Is formed by growing an epitaxial layer containing an N-type impurity to a predetermined thickness on the surface of the substrate. In a power IC, an epitaxial layer containing an N-type impurity such as phosphorus or antimony is grown to a predetermined thickness on the surface of a P-type wafer doped with boron at a high concentration.

[0003]

However, in such a manufacturing method, in growing the epitaxial layer, phosphorus or antimony is contained in the epitaxial layer at a high concentration, so that the lattice constant of these N-type impurities is increased. Was larger than that of the boron-doped portion, and the epitaxial wafer was warped with the surface epitaxial layer on the convex side. This warpage tends to increase as the IC manufacturing process proceeds. Due to this warpage, a problem has arisen in the transfer step of the silicon wafer or in the photolithography step which is a subsequent step. For example, a silicon wafer cannot be vacuum-sucked. In addition, there is a disadvantage that it cannot be set in the exposure apparatus.

[0004]

Therefore, the inventor of the present invention pays attention to the fact that this bow is due to the ionic radius of the N-type impurity being larger than that of silicon or boron, and grows an epitaxial layer in advance. It has been found that by slicing the surface side in a concave or convex shape, the amount of warpage of the epitaxial wafer can be controlled.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor wafer having an epitaxial layer on its surface and capable of controlling the warpage of the semiconductor wafer.

[0006]

According to the method of manufacturing a semiconductor wafer according to the first aspect of the present invention, when a wafer is formed by slicing a rod-shaped semiconductor single crystal, the wafer is curved and cut into a bowl shape ( This is a method for manufacturing a semiconductor wafer in which a curved surface having a predetermined radius of curvature is added) and an epitaxial layer containing an impurity having an ion radius larger than that of the semiconductor single crystal is stacked on the concave surface of the wafer.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor wafer, when a rod-shaped semiconductor single crystal is sliced by, for example, an inner peripheral slicer to form a wafer, the wafer is bent into a bowl shape. The wafer is cut out (with a curvature having a predetermined radius of curvature), and an epitaxial layer containing an impurity having an ion radius smaller than that of the semiconductor single crystal is stacked on the convex surface of the wafer.

[0008]

According to the method of the present invention, a curved semiconductor wafer is manufactured by slicing a rod-shaped semiconductor single crystal. In this case, a predetermined curvature is added to the semiconductor wafer so that one surface is convex and the other surface is concave. Thereafter, an epitaxial layer containing a predetermined impurity is grown on the concave surface of the semiconductor wafer. For example, a predetermined amount of phosphorus or antimony having an ion radius larger than that of silicon is contained in the epitaxial layer. As a result of this epitaxial growth, a warp (elastic strain) in a direction opposite to the above-described curvature (a direction in which the epitaxial layer becomes convex) is generated in the semiconductor wafer. Therefore, the warpage due to the initial curvature is corrected, and a flat semiconductor wafer is manufactured. In this epitaxial wafer, the elastic strain becomes a plastic strain and is stabilized by the subsequent thermal process. Further, according to the present invention, an epitaxial layer containing an impurity having an ionic radius smaller than that of the semiconductor single crystal can be grown on the convex surface of the semiconductor wafer curved as described above. Also in this case, similarly, the warpage of the semiconductor wafer due to the initial bending can be corrected, and a flat semiconductor wafer can be manufactured.

For example, when a silicon ingot pulled up by the CZ method is sliced with a thin stainless steel inner peripheral blade slicer, a phenomenon in which the center portion is curved outward due to the buckling of the blade is known. Conventionally, flat wafers were manufactured by changing the cutting conditions to prevent this, or dressing only one side, or tilting the slice blade to the opposite side with an electromagnet to adjust the sharpness of the slicer blade. That has been done. In the present invention, a slice wafer in which a predetermined curvature (corresponding to a warpage of 20 to 40 μm) is applied to a silicon wafer is manufactured by a method reverse to the conventional method. Then, normal lapping, etching, and mirror polishing are performed on the sliced wafer. Further, on the concave surface of the silicon wafer, an epitaxial layer doped with antimony by a predetermined concentration is grown to a predetermined thickness. By appropriately setting the type, concentration, layer thickness, etc. of the impurities in this growth, the same amount of warpage as the curvature given at the time of slicing can be added in the opposite direction, and as a result, a flat epitaxial wafer can be manufactured. Can be done.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a view for explaining one embodiment of a method of manufacturing a semiconductor wafer according to the present invention.

In this embodiment, a CZ method (Czochralski method) is used for growing a silicon single crystal rod.
In order to eliminate the influence of oxygen precipitation on warpage,
The initial oxygen concentration is set to 0.3 to 1.2 × 10 ¹⁸ cm ⁻³ .

The pulled silicon single crystal rod is sliced into a wafer by an inner peripheral slicer. A steel blade with industrial diamond powder adhered to the inner periphery is strongly pulled from the outer periphery and fixed, and while applying a cutting fluid, it is rotated at a high peripheral speed of about 1100 m / min to cut the single crystal rod into wafers. . Cutting speed is 60-70m
m / min. At this time, the silicon wafer has the same curvature as that of the single crystal rod end face at the center and the end of the end face of the single crystal rod, and has the same curvature as the cutting (the wafer center when the wafer is held on a horizontal table). It is manufactured by precisely cutting a single crystal rod so that the difference in the thickness direction from the outer peripheral portion of the wafer is 20 μm. This silicon wafer has a diameter of 5 inches and a thickness of 620μ.
m, the plane direction is (100).

Then, as shown in FIG. 1 (A), lapping after slicing removes slice damage on both sides,
Further, the lap damage is removed from the silicon wafer 11 by etching the surface by a thickness of 15 to 20 μm. By removing the damage layer on the surface, the warpage due to the elastically applied strain is removed, but the warpage due to the curvature that does not damage the crystal is not removed. Note that, in this case, the silicon wafer 11 has a deformation that is warped by 20 to 40 μm in which the surface side is concave as described above. Next, as shown in FIG. 1B, an oxide film 12 having a predetermined thickness is formed on the back surface of the silicon wafer 11. The oxide film is formed by LPCVD at 400 ° C. (ie, 650 to 700 ° C.).
(° C. or below the temperature range in which the elastic warpage is released). This oxide film 12 is for preventing auto doping during epitaxial growth.

Next, an epitaxial layer 13 is formed on the concave surface of the silicon wafer 11 to a thickness of 90 to 120 μm.
It is grown at 200 ° C. (see FIG. 3C). This thickness is a value obtained in advance by calculation corresponding to the amount of warpage of the silicon wafer 11. In this case, the epitaxial layer 13 is formed by doping silicon with phosphorus or antimony (N-type impurity) by 5 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ . As a result, the epitaxial layer 13
Since the dopant of (1) has an ionic radius (poling radius) larger than that of silicon, the epitaxial layer 13 itself tends to warp to a convex upper side in FIG. As a result, the curvature of the silicon wafer 11 and the epitaxial layer 1
3 cancel each other out, and the silicon wafer 11 warped flat can be manufactured. Then, the oxide film on the back surface is removed (D). In the above case, the measurement of the warpage of the silicon wafer 11 is performed by the FT-
7, or a wafer check 7200E which is a capacitance type flatness measuring device is used. As a result of the measurement, the warpage of the silicon wafer 11 after growing the epitaxial layer 13 was about several μm. This warp becomes a plastic strain in a subsequent heating step at 700 ° C. or more, and does not cause a deterioration in flatness thereafter.

FIG. 2 is a graph showing the transition of the warpage of the silicon wafer during the subsequent manufacturing process. As shown in this figure, it is clear that the warpage of the epitaxial silicon wafer EW having an epitaxial layer grown on its surface is smaller than that of a silicon wafer in another process. In this figure, the etched wafer HW is shown in FIG. 1 (A), the mirror-polished wafer PW is shown in FIG. 1 (B), and the epitaxial wafer (after removing the oxide film) EW.
Shows (D) respectively.

[0016]

According to the present invention, the flatness can be arbitrarily controlled when a semiconductor wafer for LSI is manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor wafer according to one embodiment of a manufacturing method of the present invention.

FIG. 2 is a graph showing a change in the amount of warpage of a silicon wafer in a manufacturing process according to one embodiment of the present invention.

[Explanation of symbols]

 11 silicon wafer 13 epitaxial layer

Claims (2)

(57) [Claims] When a wafer is formed by slicing a rod-shaped semiconductor single crystal, the wafer is curved and cut out in a bowl shape, and the concave surface of the wafer contains an impurity having an ion radius larger than that of the semiconductor single crystal. A method for manufacturing a semiconductor wafer, comprising stacking epitaxial layers. 2. When a wafer is formed by slicing a rod-shaped semiconductor single crystal, the wafer is curved and cut out in a bowl shape, and the convex surface of the wafer contains an impurity having an ion radius smaller than that of the semiconductor single crystal. A method for manufacturing a semiconductor wafer, comprising stacking epitaxial layers.