JP2705121B2 - Electronic computer system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic computer system for operating a plurality of virtual computers, and in particular, to test / debug a virtual computer by efficiently controlling an instruction event recording mechanism. The present invention relates to a computer system suitable for efficiently performing the above.

[Conventional technology]

A conventional example of an electronic computer running a virtual computer system is a computer of International Business Machines Corporation (IBM) 370 / XA architecture in the United States. In this computer, an instruction event recording mechanism (Program Even) is used to record an instruction execution event.
t Recorder: PER) is provided in an instruction processor that processes computer instructions.

When implementing a virtual machine system on this system, the execution of the virtual machine instructions is performed by directly executing ordinary instructions such as fixed-point operation instructions, floating-point operation instructions, logical operation instructions, and branch instructions on the computer. Be executed. Also,
Privileged instructions or I / O instructions that have a significant effect on computer control are executed by a virtual machine control program (VMCP).
Virtual simulation). However, in this method, the overhead due to software simulation is large, and the performance of the virtual machine is reduced.

To solve this problem, system resources such as a program status word (PSW) for controlling the computer, control registers, and timers, which control the computer, are provided to the computer for the actual computer (real computer) and for the VMCP operating on the real computer. And an instruction direct execution mechanism for directly executing instructions of the virtual computer using system resources for the virtual computer.

In the instruction direct execution mechanism, when a specific event occurs in the virtual machine when the VMCP controls the virtual machine, the function of stopping the operation of the virtual machine and returning the execution control of the instruction to the VMCP side (called an interception). ) Is supported. Here, the specific event in which the interception occurs refers to an interruption, execution of a privileged instruction, or the like.

A PER mechanism is provided on the instruction direct execution mechanism. The PER mechanism allocates one PER mechanism to each of a real computer and a virtual computer, as in the case of the system resources described above. As a result, the PER of the actual computer is
The (host PER) mechanism operates, and while the virtual machine is operating, the PER (guest PER) mechanism for the virtual machine operates.

[Problems to be solved by the invention]

According to the above-mentioned prior art, when performing an address stop / store stop on a virtual machine at the time of test / debug of a program operating on the virtual machine, an address on a main storage device that performs an address stop or a store stop on a PER mechanism of the virtual machine. Must be set to operate the RER mechanism.

However, the virtual machine PER mechanism cannot be controlled by the VMCP while the virtual machine is operating, and the virtual machine PER mechanism can be controlled from a program on the virtual machine. There may be differences from the contents of the PER mechanism. To prevent this, PE
When an instruction for controlling the R mechanism is executed on a virtual machine, it is necessary to generate an interception and check the instruction. The major problem here is that when an event related to the control of the PER mechanism is intercepted, an instruction to change the entire program status word (LPSW), an instruction to change the system mask of PSW (STNSM, STOSM), and all interrupts are executed. It is necessary to generate an interception for the execution of the event (LCTL) for updating the control register.

The above-mentioned events occur frequently, and intercepting all the above-mentioned events causes a very serious problem in performance.

An object of the present invention is to solve such a conventional problem and to enable the VMCP side to control the PER mechanism of the virtual machine without performing interception during the operation of the virtual machine,
An object of the present invention is to provide an electronic computer system capable of performing test debugging such as address stop / store stop and improving processing performance.

[Means for solving the problem]

In order to achieve the above object, the computer system of the present invention comprises the following steps: (1) As shown in FIG. 3, when the virtual machine is operating, the virtual machine operates according to the PER control bit R of the program status word PSW for the virtual machine. When the VMCP is operating, the program status word for this VMCP is activated.
First means (latch 10, multiplexer 1) for operating the PER mechanism for VMCP according to the PER control bit R of the PSW;
During operation of the virtual machine, at least the address step or the store stop instruction sent from VMCP at the time of test debugging of the virtual machine by VMCP.
Means for setting a control bit Ps for operating the PER mechanism for the virtual machine independently of the PER control bit R for the virtual machine when a predetermined instruction for controlling the mechanism is instructed (the latch 20 and the second Latch 21 of FIG. 4, readout circuit
22, an AND gate 23) and, in addition to the first means, the PER mechanism for the virtual machine is operated in accordance with the control bit Ps, and the program event detected by the PER mechanism for the virtual machine is transmitted to the VMCP.
And second means (OR gate 19, multiplexer 1).

(2) As shown in FIG. 4, the control bit Ps
Means for reading a predetermined instruction (Ps801) stored in a specific location in the main storage device 800 when an instruction to operate the virtual machine is executed.
2) and means for latching the read predetermined instruction (Ps801) and sending it to the second means (latch 20, OR gate 19)
And characterized by the following.

(3) As shown in FIG. 7, the operation of the virtual machine is monitored separately from the PER mechanism, and when a specific event occurs, the operation of the virtual machine is stopped and control is returned to VMCP. In addition, when this interception and the detection of a program event by the PER mechanism according to the control bit Ps occur at the same time, a means for notifying the fact to the VMCP (control word (IC) 702, display unit (IS) 703, control Equipment 200)
Is provided.

Also, (4) as shown in FIG. 5, identification information (control information) indicating whether the management area of the PER mechanism is designated by the physical address 610 or the logical address 609, which is given in a predetermined instruction from the VMCP. A means (multiplexer 601) for reading the "V" of the register (M) 402 and specifying the address of the main storage device required by the PER mechanism 300 based on the identification information is provided.

[Action]

In the present invention, the execution event of an instruction reported from a virtual machine to a virtual machine control program (VMCP) is stored in an instruction event recording device (PER) in a control word (PSW) for controlling the flow of a program of the virtual machine. The first operation for determining whether to perform recording in accordance with the recording control information for controlling the operation of the mechanism and the second operation for recording regardless of the value of the recording control information are included in the operation control information (bit) designated by the VMCP. Switch in response.

As a result, there is no need to intercept a PSW update instruction or an event related to an interrupt of the virtual machine, and it is possible to prevent performance degradation of the virtual machine when the address stop / store stop function is used. Also, during the operation of the virtual machine, the PER mechanism of the virtual machine can be operated from the VMCP side by the operation control information (bit).
Checking only the update of the control register enables the address stop processing.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a conceptual diagram of an electronic computer system for explaining the principle of the present invention. Hereinafter, in the reference numerals of the drawings, H indicates a host and G indicates a guest.

The computer includes real (host) and virtual (guest) instruction execution units 100H, 100G, and control devices 200H, 20G.
There is 0G. In contrast, the system has one PER mechanism that monitors program events occurring in each instruction execution unit. This is because the virtual machine is stopped while the virtual machine control program (VMCP) is running, and conversely, the VMCP does not work while the virtual machine is running, so even if only one PER mechanism Can respond to conditions.

For this reason, the signal line 15 for transmitting the address of a program event, an instruction, or data to the PER mechanism 300 includes one of a signal line 15H for transmitting a host instruction execution event and a signal line 15G for transmitting a guest instruction execution event. Multiplexer 1
Gives the selected information. This multiplexer 1 determines whether VMCP is operating on the computer system,
Alternatively, it is controlled by a latch 10 indicating whether the virtual machine is operating. When the latch 10 is ON, that is, when the virtual machine is operating, the multiplexer 1 selects the signal 15G from the guest instruction execution unit 100G. When the latch 10 is OFF, that is, when the VMCP is operating, Select the signal 15H from the host instruction execution unit 100H and set PER
Tell the mechanism 300.

Next, the program event detected by the PER mechanism 300 is transmitted to the controller via the signal line 17. At this time, the multiplexer 2 determines whether to report to the host-side controller 200H or to the guest-side controller 200G. Done by Here, the control of the multiplexer 2 is controlled by a latch 10 indicating the operation of the virtual machine or the VMCP and a latch 20 for the VMCP to control the PER mechanism 300 of the virtual machine. When the VMCP does not specify an address stop or the like and does not need to be aware of the PER mechanism 300 of the virtual machine, the value of the latch 10 is inverted and input to the OR gate 3 to control the multiplexer 2. Here, since the latch 10 is ON during the operation of the virtual machine and OFF during the operation of VMCP, the gate 3 is turned ON during the operation of VMCP.
Selects the control device 200H of the host, and the program event is communicated through the signal line 17H. Further, while the virtual machine is operating, an event is communicated to the guest control device 200G.

On the other hand, when the VMCP controls the PER mechanism of the virtual machine in processing such as address stop, the latch 20 is turned on.
As a result, the OR gate 3 is always turned ON, and all program events detected by the PER mechanism 300 are reported to the host control device regardless of the operation of the virtual machine, and processing is performed by the VMCP. It is possible.

The information of the latch 20 is transmitted by the signal line 7 to the PER mechanism 300.
To enable program events to be captured regardless of the PER control bit of the virtual machine.

FIG. 1 is an overall configuration diagram of a computer system showing one embodiment of the present invention. In FIG. 2, the instruction direct execution mechanism for the virtual machine is described in such a manner that there is an instruction execution unit and a control device for the host and for the guest, respectively. One of these devices is to use the system resources for the host and the resources for the guest separately, so that each of them appears to be an individual device. Here, the system resources are PSW, which controls the flow of the program,
Hardware resources such as control registers and timers.

The computer system includes an instruction execution unit 100, a controller 200, a PER mechanism 300, a host resource 400H, a guest resource 400G,
It comprises a recording control switching circuit 500, a resource switching unit 501, a virtual computer control program (VMCP) and a main storage device 800 on which a virtual computer (VM) operates.

When the instruction execution unit 100 executes the VMCP 802 (host program), the fact is transmitted as a control signal to the resource switching unit 501, so that the host resource 400H is selected and used as the resource of the instruction execution unit 10. You.
Further, when the instruction execution unit 100 executes the program of the virtual machine (VM) 803, the resource switching unit 50
1 is sent as a control signal to select and execute the guest resource 400G. Further, at this time, when operating the PER mechanism 300 for recording an event of the program, information for controlling the PER mechanism 300 is transmitted to the host resource 40 for the PER mechanism 300.
It is necessary to select from 0H or guest resource 400G. In that case, the recording control switching circuit 500 performs the second operation depending on the type of the program executed by the instruction execution unit 100.
Host resource 400H or guest resource 400G
Is selected and input to the PER mechanism 300. The PER mechanism 300
Is executed is sent to the control device 200 via the control line 17. The result is the instruction execution unit 100
Is reflected in

FIG. 3 is a diagram showing a specific circuit configuration example of the recording control switching circuit 500 in FIG.

The recording control switching circuit 500 includes latches 10 and 20, a multiplexer 1, an OR gate 19, and the like. The host resource 400H and the guest resource 400G are connected to a multiplexer.
12 and used by the instruction execution unit 100. As described above, this multiplexer 12 is controlled by the latch 10 indicating the operation of the virtual machine and the VMCP.

First, if VMCP uses the PER mechanism 300, host resources
400H is selected. Here, the host resource 400H that controls the PER mechanism 300 includes a PER control bit in the host PSW (HPSW).
R, NiA indicating the address of the next instruction and control register M,
There are S and E. The control register M stores (i) a branch success event,
(Ii) instruction read event, (iii) main memory update event, (i
v) A mask register for selecting a valid event among program events such as a general-purpose register update event.
The control registers S and E store the start address and the end address of the monitoring area to be monitored by the PER mechanism 300 on the main storage device. Information for controlling the PER mechanism 300 is input to the PER mechanism 300 through the signal line 15H and the signal line 15. Further, information relating to the execution of the instruction is input from the instruction execution unit 100 via the signal line 16. The PER mechanism 300 captures a program event based on this information and reports it to the control device 200 via the signal line 17.

The case where the virtual machine uses the PER mechanism 300 is basically the same as the case of the VMCP. However, as described in FIG. 2, the PER control bit R in the virtual machine PSW (guest PSW: GPSW) is used as it is for controlling the PER mechanism 300 in order to control the PER mechanism of the virtual machine from the VMCP side. Not used, and the logical sum of the control bit Ps (latch 20) provided by the VMCP for controlling the PER mechanism of the virtual machine and the OR gate 19 is sent to the PER mechanism 300. Therefore, the control bit
If Ps is in the ON state, the PER mechanism 300 can be made effective regardless of the state of the PER control bit R of the GPSW. The control bit Ps can be operated only by the VMCP, and is controlled by the instruction execution unit 100 via the signal line 18.

FIG. 4 is a diagram for explaining a method of generating the control bits Ps.

The PER control bit (Ps) 801 at the time of execution of the virtual machine stored in a specific location in the main storage device 800 is read from the main storage device 800 by the readout circuit 22 when an instruction to operate the virtual machine is executed. And set to latch 20. However, at this time, depending on the model of the computer, the control mechanism for operating the PER mechanism of the virtual machine from the VMCP side may not be incorporated in the system.
The AND gate 23 calculates the logical product of the latch 21 and the read circuit 22 indicating that the control mechanism is incorporated, and sets the logical product in the latch 20.

The information of the latch 20 is ORed with the PER control bit R of GPSW.
The logical sum is obtained by the gate 19 and input to the PER mechanism 300 through the multiplexer 1.

On the other hand, the PER control bit R of the HPSW is input to the PER mechanism 300 via the multiplexer 1 as it is. As described above, the multiplexer 1 is controlled by the latch 10 indicating the operation of the virtual machine and the VMCP.

FIG. 5 is an explanatory diagram relating to the address information input to the PER mechanism 300.

Logical address NiA of the next instruction to be executed in PSW401
Alternatively, the logical address of data created in the instruction execution unit 100 passes through signal lines 605 and 606, and the address translation mechanism 602
Through the signal line 608 to the buffer unit 101 which performs instruction fetch and data read / write. At this time, the address conversion mechanism 602 is controlled by an address conversion control bit T in the PSW 401, and when the control bit T is ON, a logical address is converted to a physical address. When the control bit T is OFF, the conversion to the physical address is not performed, and the logical address is output as the physical address.

When checking the PER event, the PER mechanism 300 needs the address of the main storage device 800. In this case, the logical address 609 before passing through the address translation mechanism 602 and the physical address 610 after passing are converted into a multiplexer 601. And input to the PER mechanism 300. This multiplexer 601
Is controlled by an address selection bit V newly provided in the control register (M) 402. Multiplexer 601
When the control bit V is ON, that is, when requesting that the control registers (S) 403 and (E) 404 storing the start address and end address of the monitoring area by the PER mechanism 300 be treated as a logical address, 609
Select Also, the control bit V is OFF, that is, PE
When the monitoring area of the R event is specified by the physical address, the physical address 610 after the end of the address conversion is selected.

Address selection bit V in control register (M) 402
Is specified by the V / R operand of the ADSTOP command shown in FIG. In the example of FIG. 6, I indicates designation of an address stop, S indicates designation of a store stop, V indicates designation of a logical address, and R indicates designation of a physical address. Therefore, in the case of an address stop, it is designated by "IV" or "IR", "stop address", and "OFF". Also,
In the case of a store stop, it is specified by "SV" or "SR", "start address", "end address / byte number", and "OFF".

FIG. 7 is a diagram for explaining the operation of the control device 200 when a program event occurs.

The program event generated from the PER mechanism 300 is sent to the control device 200 via the signal line 17. The control device 200 has a function of determining how to perform the processing for the report of the program event. Therefore, in the control device 200, G
In addition to the control bit Ps for controlling the PER mechanism of the virtual machine from the PER control bit R and VMCP of the PSW401G, it controls whether the PER event is reported to the program on the virtual machine by interruption or reported to VMCP by interception. The control word (IC) 702 to be input is input. Also, apart from the PER mechanism,
The control device 200 has a mechanism for monitoring the operation of the virtual machine and generating an interception according to the result of the operation of the virtual machine. For this reason, a program event and an interception may occur simultaneously, and a display unit (IS) 703 for reporting the event to the VMCP is provided.

The control device 200 comprehensively judges the above information, and sends the instruction execution unit 100 a signal 31 requesting generation of an interrupt and a signal 30 requesting generation of an interception.

Next, a control word (control bit) IC for controlling the interception and a display word (display section) IS indicating that the PER event and the interception have occurred at the same time are described in the eighth section.
This will be described with reference to FIGS.

FIG. 8 is a configuration diagram of a control word (IC) 702 for controlling the interception.

The control word 702 is a set of control bits for controlling whether or not to generate an interception. The control bits will be represented by IC (n) using the respective bit positions n.

The fields related to the processing of the PER event in the control word 702 are IC (0) for requesting interception when an instruction exception occurs on the virtual machine, IC (1) for requesting interception of privileged instruction exception, and instruction IC (2) that requests interception of program interrupts such as PER events, excluding exceptions, privileged instruction exceptions, and execution of instructions that unconditionally cause instruction interception, and condition code CC when executing TS, CS, and CDS instructions There are ICs (4), (5), and (6) that request an interception when is "1".
Here, if the bit is ON, an interception is generated when the event occurs, and a request is made to pass control to the VMCP. If the above bit is OFF, no interception occurs, and the processing is left to the virtual machine.

FIG. 9 is a diagram showing a configuration example of the display word (IS) 703. This indicates that the PER event and the interception have occurred at the same time. When the _If bit in the display word 703 is ON, it indicates that two events have occurred at the same time.

FIG. 10 is an explanatory diagram of the operation of the microprogram of the control device 200 relating to the PER event described in FIG. 7, and FIG. 10 shows branch numbers (a), (b), and (b), respectively.
(C) and (d) are shown separately.

First, when execution of an instruction is started, it is checked whether the instruction is an instruction causing an unconditional interception (step 1000). If the instruction causes an unconditional interception, a code "04" indicating that an unconditional interception has occurred is set in the interception code CODE (step 1001). Where the interception and PER
Check if events occurred simultaneously (step
1002). If the PER event has occurred at the same time, the display bit _If for displaying the event is turned ON (step 100).
3). If the PER event has not occurred, _If is turned OFF (step 1004), and the process proceeds to the interception process (step 1034) (see FIG. 10 (d)).

Next, if the instruction does not cause an unconditional interception, it is checked whether or not the instruction causes an instruction exception interception (step 1005). Here, if the instruction causes an instruction exception interception, it is checked whether or not a PER event has occurred simultaneously (step 100).
7). And an IC that controls instruction exception interception
(0) is checked (step 1008), and if the PER event is occurring simultaneously, if this bit is OFF, the interception code of the program interrupt (PER interrupt) is set (step 1009). Here, since the occurrence of the PER event is indicated by the interception code CODE, _If is kept OFF (step 10010). On the other hand, when IC (0) is ON, that is, when an instruction exception interception request is made, a code “44” indicating that an instruction exception interception has occurred is set in the interception code CODE. (Step 1011)
And an indication bit I indicating that a PER event has occurred simultaneously.
_f is turned ON (step 1012). Thereafter, the process proceeds to an interception process (step 1034).

If the PER event does not occur at the same time as the instruction causing the instruction exception interception (step 1
007) First, an IC that requests instruction exception interception
(0) is checked (step 1013), and if IC (0) is OFF, there is no need to generate an interception, so the processing is left to the virtual machine side (step 101).
Four). If IC (0) is ON, the code "44" of the instruction exception interception is set to CODE (step 1015).
_f is turned off (step 1015-1), and the process proceeds to the interception process (step 1034).

If it is determined in step 1005 that the instruction does not cause an instruction exception interception, it is checked whether the instruction causes a conditional interception (step 1006).
If the instruction causes a conditional interception,
The processing shown in FIG. 10 (b) is performed. If the instruction does not cause a conditional interception, the processing shown in FIG. 10 (c) is performed.

FIG. 10 (b) shows an outline of processing at the time of an instruction causing a conditional interception.

The conditional interception is an interception that occurs when an instruction that can control whether execution of an instruction is directly left to hardware or software simulation is performed by intervention of VMCP is executed.

The instructions for generating the conditional interception include an instruction to change the state of the system, an instruction related to timer control, an instruction used for serialization of resources, and the like. The control of the interception of these instructions
This is performed by each bit of the IC 702 in the figure.

First, TS instruction for performing serialization, CS
An instruction and a CDS instruction are executed, and if the condition code of the instruction is "1" (this indicates that the operation of the instruction has failed), it is checked (step 1016). If this condition is met and an interception is to be generated, it is further checked whether or not PER events are simultaneously occurring at this time (step 1017). Here, if the PER event occurs simultaneously, the instruction code indicating that the condition code becomes "1" by the TS instruction, CS instruction, and CDS instruction, and the program interrupt by the PER mechanism and the program interrupt interception The code "12" is set in CODE (step 1018).

If the PER event has not occurred simultaneously (step 1017), the interception code CODE is set to "04" (step 1019), and if the PER event has not occurred simultaneously, _If is turned off (step 1020).

Then, the process proceeds to the interception process (step
1034).

If an instruction other than that for performing serialization, such as a TS instruction, a CS instruction, or a CDS instruction, is executed in an instruction for generating a conditional interception, it is checked whether the interception condition is satisfied (step 10).
twenty one). If the condition is not satisfied, the instruction is directly executed (step 1022). If the condition is satisfied, the process proceeds from step 1016 to step 1023, where the interception code CODE is set to "04". It is checked whether they have occurred simultaneously (step 1024). Where PE
If the R event occurs simultaneously, turn on the display bit _If indicating that the program interrupt by PER has occurred at the same time.
(Step 1025), and the process proceeds to the interception process (step 1034). If the PER event has not occurred at the same time, the OFF and I _f (step 1026), the process proceeds to interception process (step 1034).

FIG. 10 (c) shows processing relating to execution when neither unconditional interception, interception other than instruction exception interception, or conditional interception occurs.

First, in this case, the control bit Ps for controlling the PER mechanism of the virtual machine is checked from the VMCP (step 102).
7) If this bit is ON, this interception and PER
Check whether the events occurred simultaneously (step 102
8) If the PER events occur simultaneously, set an interception code "08" indicating that a PER program interrupt has occurred (step 1029). If there is no PER event, the instruction is directly executed (step 1029-
1).

Even if the control bit P _s is OFF (step 1027),
Similarly, it is checked whether or not PER events have occurred simultaneously (step 1030).
The control flag IC (2) for controlling whether or not to intercept the ER event is checked (step 1031). If the bit is OFF, the event is reported to the virtual machine (step 1032). If the IC (2) is ON, the program interruption interception code "08" for indicating that the PER event has occurred is set in the interception code CODE (step 1033). Thereafter, the process proceeds to an interception process (step 1034). In step 1030, when there is no PER event, the instruction is directly executed (step 1033-1).

When the address of the virtual machine is stopped by the operation of the above embodiment, the control bit Ps for controlling the PER mechanism of the virtual machine is turned ON, and the PSW of the virtual machine is turned on.
It is no longer necessary to generate an interception for the instructions and events that cause the update of the. Here, the PSW update instruction and the interrupt event frequently occur during the operation of the virtual machine. The fact that this event can be directly executed without using software simulation by VMCP is a very great advantage in terms of system performance. is there.

〔The invention's effect〕

As described above, according to the present invention, during operation of a virtual machine, VMCP is performed without generating interception.
The PER mechanism of the virtual machine can be directly controlled from the side, and test debugging such as address stop / store stop can be performed without generating an interception for an instruction for updating the system mask portion of the PSW and an interrupt event.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall configuration diagram of an electronic computer system showing one embodiment of the present invention, FIG. 2 is a principle explanatory diagram of the present invention, and FIG. 3 is a recording control switching in FIG. FIG. 4 is a diagram showing a specific configuration example of a circuit, FIG. 4 is a diagram for explaining a control bit generation method of a PER mechanism of a virtual machine, FIG. Fig. 7 shows an example of a VMCP command for controlling the address check method.
Operation explanatory view of the control device for controlling the R event, FIG.
FIG. 9 is an explanatory diagram of control information of the PER mechanism, and FIG. 10 is a schematic diagram of a microprogram in the control device. 100: instruction execution unit, 200: control unit, 300: PER mechanism, 4
00H: host resource, 400G: guest resource, 500: recording control switching circuit, 501: resource switching unit, 800: main memory, 801: control bit, 802: virtual computer control program, 803: virtual computer, 10: virtual computer Latch indicating that is operating, 20: Control latch for controlling the PER mechanism of the virtual machine from VMCP.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Satoshi Seino 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside Hitachi, Ltd.System Development Laboratory Co., Ltd. (72) Hidenori Umeno 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Hitachi Systems Development Laboratory (72) Inventor Masatoshi Haraguchi 5030 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Software Factory (72) Inventor Hideo Sawamoto 1-Horiyamashita, Hadano-shi, Kanagawa Prefecture Hitachi, Ltd. (72) Inventor Norio Shiokawa 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Kosumi Koike 1015 Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor Yukio Ito 1-10-10 Nissincho, Fuchu-shi, Tokyo Japan Electric Co., Ltd. (56) References JP-A-62-114042 (JP, A)

Claims (4)

(57) [Claims] A plurality of virtual machines operating under control of a virtual machine control program (VMCP);
In an electronic computer system provided with a VMCP and an instruction event recording mechanism (PER mechanism) for monitoring a program event during operation of the virtual machine, a PER control bit R of a program status word PSW for the virtual machine when the virtual machine is operating According to the virtual machine for
A first means for operating a PER mechanism and operating the PER mechanism for VMCP in accordance with the PER control bit R of the program status word PSW for the VMCP during the operation of the VMCP; At the time of test debugging of the virtual machine, if a predetermined command for controlling the PER mechanism is specified from the VMCP including an address stop instruction or a store stop instruction specified by the VMCP, a PER control bit for the virtual machine Means for setting a control bit Ps for operating the PER mechanism for the virtual machine irrespective of R; in addition to the first means in addition to the first means according to the control bit Ps,
And a second means for operating the PER mechanism and sending the program event detected by the PER mechanism for the virtual machine to the VMCP. 2. The computer system according to claim 1, wherein said means for setting said control bit Ps is stored in a specific location in a main memory when an instruction to operate said virtual machine is executed. An electronic computer system comprising: means for reading the predetermined instruction; and means for latching the read predetermined instruction and sending the latched instruction to the second means. 3. The electronic computer system according to claim 1, wherein the operation of the virtual computer is monitored separately from the PER mechanism, and when a specific event occurs, the virtual computer is monitored. When the interception is performed to return the control to the VMCP by suspending the operation of the above, and when the interception and the detection of the program event by the PER mechanism according to the control bit Ps occur simultaneously, the fact is notified to the VMCP. An electronic computer system characterized by comprising means for performing. 4. The computer system according to claim 1, wherein the management area of the PER mechanism provided in the predetermined command from the VMCP is a physical address or a logical address. The identification information indicating which is designated is read, and based on the identification information, the PE
An electronic computer system comprising means for specifying an address of a main storage device required by an R mechanism.