JP2723700B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device, and more particularly to a structure of a peripheral circuit of a static random access memory (SRAM).

[0002]

2. Description of the Related Art Generally, a semiconductor memory device such as an SRAM includes a memory cell array region and a peripheral circuit such as a decoder circuit and a bit line potential supply circuit adjacent thereto. Of these peripheral circuits, specific peripheral circuits such as a bit line balancing circuit that balances a pair of bit lines constituting a memory cell array to the same potential, and a bit line potential supply circuit that supplies a potential to a pair of bit lines are bit lines. Must be installed for each pair. Therefore, these specific peripheral circuits are arranged along one side of the rectangular memory cell array region, that is, adjacent to one side of the peripheral portion of the memory chip. The gate electrodes of transistors (FETs, hereinafter the same) constituting these specific peripheral circuits are generally formed of a polysilicon film, and the pattern density thereof is extremely high.

[0003]

However, as described above, in a conventional semiconductor memory device including the above-mentioned specific peripheral circuit having such a configuration, wiring is formed in a predetermined pattern from the memory cell array region to other peripheral circuits. They are densely arranged. However, the outermost circuit of the peripheral circuits, that is, the circuit disposed at the outermost periphery of the memory chip (generally, a part of the above-described bit line potential supply circuit) has one side with less wiring. In contact with the outer peripheral portion of the memory chip that is not connected. At that portion, the wiring pattern changes from dense to sparse, and the regularity of the pattern is disturbed.

The width of the wiring near the region where the regularity of the formed pattern is disturbed in this way is larger than the design target value as compared with the wiring of the other region formed with the regularity. The inventors of the present invention have found that there is a tendency.
If the width of the wiring, particularly the wiring of polysilicon which becomes the gate electrode of the transistor, becomes larger than the design target value, as a result, the channel length of the transistor becomes longer than the design target value. For example, when the design target value of the polysilicon wiring width is 0.8 μm, 0.06 μm due to the above-described cause.
The width of the wiring is increased by about m, and the channel length of the transistor using the wiring as a gate electrode is increased accordingly.

It is considered that one of the reasons why the width of the wiring becomes larger than the design target value is as follows. If the regularity of the wiring formation pattern is disturbed,
In the lithography step for selectively removing the polysilicon film, that is, in the step of exposing with a predetermined mask pattern after applying a photoresist, the portion where the regularity is disturbed affects the diffraction of light, and Change the conditions. That is, the exposure condition changes in a direction in which the width of the selectively left polysilicon film becomes larger than the design target value.

As described above, the width of the wiring is larger than the design target value in the circuit arranged at the outermost periphery of the memory chip, and is generally a part of the bit line potential supply circuit. As the channel length of the transistor constituting this potential supply circuit increases, the transconductance of the transistor decreases accordingly, resulting in a reduction in the potential supply capability to the bit line.

[0007] The decrease in the potential supply capability to the bit line is as follows.
Since the potential change of the bit line at the time of signal reading or writing causes a delay, not only the reading / writing speed of the semiconductor memory device is remarkably reduced, but also a malfunction occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device which prevents a decrease in the mutual conductance of transistors forming a peripheral circuit, and prevents a reduction in writing / reading speed and a malfunction.

[0009]

According to the present invention, there is provided a semiconductor memory device having a memory cell array region formed in a substantially rectangular shape on the surface of a semiconductor substrate, and a predetermined arrangement arranged adjacent to a predetermined side of the memory cell array region. A bit line balancing circuit having a first wiring pattern, a bit line potential supply circuit having a predetermined second wiring pattern disposed outside the bit line balancing circuit when viewed from the memory cell array region, A first dummy wiring region which is arranged further outside the line potential supply circuit and has a pattern substantially similar to the first wiring pattern.

Further, the semiconductor memory device of the present invention further includes a second dummy wiring region having the second wiring pattern and disposed at both ends of each of the bit line potential supply circuits.

Preferably, the first and second dummy wiring regions are formed in the same manufacturing process as the wiring patterns of the bit line balancing circuit and the bit line potential supply circuit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.
Referring to FIG. 1, a semiconductor chip 6 constituting a semiconductor memory device according to an embodiment of the present invention includes a memory cell array region 4 in which memory cells are arranged in an array, and a row decoder for selecting a word line according to an input address. 5, a bit line balancing circuit 3 for balancing the bit line pairs to the same potential, and bit line potential supply circuits 1 and 2 for supplying a potential to the bit line pairs. Circuits are also provided, but other circuits are omitted for convenience of description).

Since the bit line balancing circuit 3 and the bit line potential supply circuits 1 and 2 are respectively connected to the bit line pairs forming the memory cell array region 4, they are arranged adjacent to the memory cell array region 4. More specifically, the bit line balancing circuits 3 are arranged along one side of each memory cell array region 4, and the bit line potential supply circuits 1, 2 are located outward from the memory cell array region 4 of the bit line balancing circuit 3. Is arranged.

Further, a dummy wiring region 7 is provided outside the bit line potential supply circuit 1 as viewed from the memory cell array region 4. This dummy wiring region 7 is formed of a polysilicon wiring layer having a shape similar to that of the polysilicon wiring of the bit line balancing circuit 3, as described later in detail.

Next, referring also to FIG. 2, a plurality of memory cells MC are arranged in an array to form a memory cell array region 4. Each of the memory cells MC has 1
Two word lines WL and two bit line pairs La and BLb (in FIG. 2, only the rightmost column has bit line pairs BLa, BLa,
BLb) are connected to each other. The number of bit line pairs is equal to the number of columns of memory cells forming memory cell array region 4. Each of these bit line pairs is connected to a bit line balancing circuit 3 and bit line potential supply circuits 1 and 2, respectively.

The bit line balancing circuit 3 includes a transistor M having a source / drain path connected to the bit lines BLa and BLb and a gate connected to the wiring 10 for supplying the control signal φ.
P30 is included by the number of bit line pairs.

The bit line potential supply circuits 1 and 2 have a source
A plurality of transistors MP each having a drain path connected to the power supply terminal Vcc and the bit line BLa and a gate connected to the ground power supply
10 and a plurality of transistors MP20 each having a source / drain path connected to the power supply terminal Vcc and the bit line BLb, and a gate connected to the ground power supply. Since the arrangement of the transistors MP10 and MP20 is limited by the chip surface area, a plurality of transistors M
The region in which P10 is formed is defined as a bit line supply circuit 1, and the region in which a plurality of transistors MP20 are formed is defined as a bit line supply circuit 2 in an alternately interlaced form as shown.

The dummy wiring region 7 is arranged adjacent to and further outside the bit line potential supply circuit 1 as described above.

In the read operation of the semiconductor memory device, one word line WL selected by row decoder 5 is activated. The storage contents of the plurality of memory cells MC connected to the word line WL are supplied to each bit line pair. Bit lines BLa and BLb forming a bit line pair
Either one of them becomes lower than the power supply potential in accordance with the stored contents of the memory cell MC, and the other bit line remains at the power supply potential. The potential difference between the two bit lines is amplified by a sense amplifier (not shown) and sent out to an output circuit (not shown) through one bit line pair selected by a column decoder (not shown). The read operation for the stored contents ends. By setting the control signal φ to an active level before the next read, the bit lines BLa and BLb are electrically connected, and the bit line potential supply circuits 1 and 2 further control the bit lines BLa and BLa.
Lb both restores the power supply potential.

As described above, the bit line potential supply circuits 1, 2
After the potentials of the two bit lines forming the bit line pair are both returned to the power supply potential by the bit line balancing circuit 3, the next read operation is performed.

FIG. 3 is a plan view showing the bit line potential supply circuits 1 and 2, the bit line balancing circuit 3 and the dummy wiring region 7 of the semiconductor memory device shown in FIG. The same components as those in FIG. 2 are given the same numbers.

The transistor MP10 is formed in the diffusion layer forming region 13, the gate electrode made of the polysilicon layer 8a is formed integrally with the polysilicon wiring 8a, and the source region is connected to the bit line BLa made of an aluminum film by a plurality of contacts. The drain region is connected to a power supply wiring 11 made of an aluminum film through a plurality of contact holes 12b.

A transistor MP20 constituting the bit line potential supply circuit 2 is also formed in the diffusion layer formation region 13,
A gate electrode made of polysilicon layer 9a is formed integrally with polysilicon wiring 9b, a source region is connected to bit line BLa made of an aluminum film through a plurality of contact holes 12a-2, and a drain region is common to transistor MP10. It is formed by a drain region and is connected to a power supply wiring 11 made of an aluminum film through a plurality of contact holes 12b.

The transistor MP30 constituting the bit line balancing circuit 3 is formed in the diffusion layer formation region 16, and its gate electrode is formed of three polysilicon wirings 10.
Source and drain regions are connected to bit lines BLa and BLb through contact holes 15, respectively.

The dummy wiring region 7 has a polysilicon wiring 10
And a plurality of polysilicon wirings 20 having the same number, wiring width and pitch, and are arranged apart from the bit line supply circuit 1 by a distance equal to the distance between the bit line potential supply circuit 2 and the bit line balancing circuit 3. I have.

Next, the manufacturing process of this embodiment will be described. The surface of the semiconductor substrate is selectively oxidized to partition the memory cell array region 4, the diffusion layer formation regions 13 and 16, and the like.
Next, a gate oxide film is formed in the diffusion layer formation regions 13, 16 and the like, and a 350 to 400 nm thick polysilicon film doped with phosphorus is deposited. Next, a positive photoresist film is applied, and the pattern on the photomask is transferred to the photoresist film. By this step, the dummy wiring region 7 is formed together with the gate electrode 8a of the bit line potential supply circuit 1, the polysilicon wiring 8b, the gate electrodes 9a and 9b of the bit line potential supply circuit 2, the gate electrode 10 of the bit line balancing circuit 3, and the like. Are also formed at the same time.

The polysilicon film is patterned by plasma etching using the photoresist film to which a predetermined pattern has been transferred as a mask to form gate electrodes 8a and 9a, polysilicon wirings 8b and 9b, and dummy wiring region 7.

FIG. 4 shows a wiring pattern of the polysilicon film formed in the same step. As shown in the figure, by providing the dummy wiring region 7, the gate electrodes 8a, 9
Patterns of three wirings 10 and 20 having the same wiring width and pitch are formed on the outside and inside of the semiconductor chip 6 around the pattern of a and the polysilicon wirings 9a and 9b. With such a configuration,
Gate electrodes 8a, 9a and polysilicon wirings 9a, 9
b, The dummy wiring region 7 can be formed in a pattern symmetrical with respect to a line (CL in FIG. 4) passing through the centers of the gate electrodes 8a and 9a.

Next, using the gate electrode 8a and the polysilicon wiring 8b as a mask, ions are implanted into the diffusion layer forming regions 13 and 16 to form source and train regions, and transistors MP10, MP20 and MP30 are formed.

Deposition of interlayer insulating film, contact holes 12, 1
After formation of 3 and 14, an aluminum film is deposited to form power supply wiring 11 and bit lines BLa and BLb.

Through the above steps, the semiconductor memory device according to the present embodiment is formed.

Referring to FIG. 5, the numbers of the gates 8a counted toward the left with the gate electrode 8a-1 at the right end of FIG. Is plotted on the vertical axis, the value of the width L of the gate electrode of the transistor MP10 of the bit line potential supply circuit 1 obtained by the present embodiment is indicated by a black dot, and the width L of the gate electrode according to the prior art is indicated by X. Have been. In this embodiment, the width L of the gate electrode 8a is 0.8 μm.
m (A in FIG. 5), and the pitch of the electrodes 8a is 5 μm.

As is apparent from FIG. 5, the width of the gate electrode of the semiconductor memory device according to the prior art has a design target value of 0.1.
In contrast to 8 μm, which is about 0.05 μm to 0.06 μm, the difference between the two in this embodiment is 0.1 μm.
It is less than 03 μm. The reason why the width of the gate electrode can be prevented from becoming larger than the design target value is that the formation pattern of the polysilicon layer including the gate electrodes 8a and 9a and the polysilicon wirings 8b and 9b is reduced. This is because the dummy wiring region 7 has the above-mentioned symmetry (see FIG. 4), so that the above-mentioned unevenness does not occur in the light diffraction at the time of mask pattern exposure for forming the polysilicon layer.

As described above, when the width of the gate electrode is increased, and as a result, the channel length is increased, the transconductance of the transistor is reduced.

In order to more quantitatively show the adverse effect of the reduction in the transconductance of the transistor, the time t is plotted on the horizontal axis, and the potential of the bit line and the read output are plotted on the vertical axis. The decrease in the mutual conductance of the transistor MP10 constituting the line potential supply circuit is as follows.
Since the potential change of the bit line changes from the solid line (1) a to the dotted line (1) b, which causes a delay, the rising of the read output of the semiconductor memory device also causes a delay from the solid line (2) a to the dotted line (2) b ( In the above conventional example, about 2 to 3 nsec) is generated.
These problems have been solved by the present embodiment.

In the above embodiment, the dummy wiring region 7
Has been described as a polysilicon wiring having a shape similar to that of the polysilicon wiring pattern 10, that is, the number of stripes, the width, and the pitch are substantially the same. It is not necessary to be exactly the same as 10, but it is sufficient if the above-mentioned symmetry is substantially maintained.

Apart from the increase in the width of the polysilicon wiring layer of the bit line potential supply circuit 1 arranged in the peripheral portion of the memory chip which the first embodiment is targeted for improvement, the wiring pattern of these polysilicon wiring layers is The inventor of the present invention has observed that the width of the wiring increases at both ends. This second embodiment provides a solution to this problem.

More specifically, the increase in the width of the polysilicon wiring layer occurs not only in the bit line potential supply circuits 1 and 2 near the periphery of the memory chip as viewed from the memory cell array region, but also in the bit line potential supply circuit. Since the same can be seen at the respective longitudinal ends of the polysilicon wiring patterns of the circuits 1 and 2, in order to cope with this, in the second embodiment, each of the bit line potential supply circuits 1 and 2 is provided. (See FIG. 7). In the second embodiment, components other than the dummy wiring region 17 are the same as those of the first embodiment. Therefore, in FIG. 7, those components are indicated by common reference numerals, and description thereof is omitted. I do.

FIG. 8 is a plan view showing the bit line potential supply circuits 1 and 2, the bit line balancing circuit 3 and the dummy wiring region 17 of the semiconductor memory device of FIG.

The patterns of the transistors MP10 and MP20 forming the bit line potential supply circuits 1 and 2 and the transistor MP30 forming the bit line balancing circuit 3 are the same as those shown in FIG.

The dummy wiring region 17 has the same pattern as the pattern of the gate electrode 8a and the polysilicon wiring 8b made of a polysilicon layer forming the bit line potential supply circuits 1 and 2. Are provided at both ends. As apparent from FIG. 9, which shows only the polysilicon wiring pattern extracted from this pattern configuration, the polysilicon layers 8a at the ends of the circuits 1 and 2
8b, the polysilicon wiring layer 18a,
18b are arranged. In this embodiment, the dummy wiring region 1
7 shows two polysilicon wirings 18a and these wirings 18
and a wiring 18b connected to the line 18a.

As shown in the graph of FIG. 10 showing the same physical quantities as those of FIG. 5 on the same scale on the horizontal axis and the vertical axis, the effect of the dummy wiring region 17 of the bit line potential supply circuits 1 and 2 according to this embodiment is It is remarkable compared to the case of technology (indicated by X). In this graph, as in FIG. 5, the width of the gate electrode 8a is 0.8 μm (A in FIG. 10), and the pitch between 8a is 5 μm.

As is apparent from FIG. 10, the width L of the polysilicon wiring is the second from the end of the pattern (the right end of the circuit pattern in FIG. 7), that is, the two wirings 18a-2 in the dummy wiring region 17. However, the third and subsequent polysilicon wirings, that is, the gate electrodes 8a-1 and 8b, have little difference from the design target value. Therefore, the present embodiment suppresses an increase in the width of the gate electrode of the transistor constituting the bit line potential supply circuits 1 and 2, and prevents a decrease in the transconductance of the transistor.

In this embodiment, the dummy wiring region 17 is composed of two polysilicon wirings 18b. However, if the number of the polysilicon wirings 18b is three or more, the gate electrode 8a,
The difference between the width of 8b and the design target value becomes smaller.

The gate electrode 10 of the transistor MP30 constituting the bit line balancing circuit 3 is also provided in the dummy wiring region 1.
By extending the lower part of FIG. 7 toward FIG. 8, it is possible to further suppress the variation of the gate electrode 8a and the polysilicon wiring layers 8b and 10 with respect to the design target value.

In this embodiment, as in the first embodiment, the wirings 18a and 18b forming the dummy wiring region 17 are formed.
It is not necessary that the values of the wiring width, the pitch width, and the like are exactly the same as those of the gate electrodes 8a and the wirings 8b. The patterns of the electrodes 8a and the wirings 8b and the wirings 18a and 18b of the dummy wiring region 17 are almost similar. In this case, the above-described effects can be obtained.

By implementing the second embodiment in conjunction with the first embodiment, the transistors in both the vertical and horizontal directions of FIG. 3 or FIG. 8 can be seen from the memory cell area of the bit line potential supply circuits 1 and 2. It will be apparent to those skilled in the art that the nonuniformity of the gate width can be eliminated, and the effect of preventing the writing and reading speeds from decreasing and malfunctioning can be improved.

In the first and second embodiments described above, the case where the gate electrode of the transistor is made of polysilicon has been described. However, the case where these gate electrodes are made of other materials such as aluminum may be used. It will be clear that the invention is equally applicable.

Further, the present invention is not limited to the SRAMs of the first and second embodiments, but includes a DRAM (dyna).
micRAM), mask ROM, PROM (progr)
ambleread only memory),
EPROM (erasablePROM), EEPROM
(Electrically erasable PR
OM), etc., as will be apparent to those skilled in the art.

[0050]

As described above, the semiconductor memory device of the present invention can prevent a decrease in the mutual conductance of the transistors forming the peripheral circuit, and can reduce the speed of writing and reading operations of the semiconductor memory device, and can reduce errors. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing an entire semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration of the semiconductor memory device shown in FIG. 1;

3 is a plan view schematically showing a wiring pattern of a part of a bit line potential supply circuit and a bit line balancing circuit of the semiconductor memory device shown in FIG. 1;

FIG. 4 is a plan view showing a wiring pattern of only a polysilicon wiring layer in the wiring pattern shown in FIG. 3;

FIG. 5 is a graph showing a variation of a gate width with respect to a design target value in a semiconductor memory device according to the present embodiment and a conventional technique.

FIG. 6 is a waveform diagram showing a voltage level waveform and an output waveform of a bit line of the semiconductor memory device.

FIG. 7 is a plan view schematically showing an entire semiconductor memory device according to a second embodiment of the present invention.

8 is a plan view schematically showing a part of a wiring pattern of a bit line potential supply circuit and a bit line balancing circuit of the semiconductor memory device shown in FIG. 7;

9 is a plan view showing a wiring pattern of only a polysilicon wiring layer among the wiring patterns shown in FIG. 7;

FIG. 10 is a graph showing a variation of a gate width with respect to a design target value in a semiconductor memory device according to the present embodiment and a conventional technique.

[Explanation of symbols]

 1, 2 bit line potential supply circuit 3 bit line balancing circuit 4 memory cell array area 5 row decoder 6 semiconductor chip 7 dummy wiring area

Claims (4)

(57) [Claims] 1. A memory cell array region formed substantially in a rectangular shape on a surface of a semiconductor substrate, and a bit line balancing circuit arranged adjacent to a predetermined side of the memory cell array region and having a first circuit layout pattern. A bit line potential supply circuit disposed outside the bit line balancing circuit as viewed from the memory cell array region and having a second circuit layout pattern; and the first layout pattern disposed further outside the bit line supply circuit. And a first dummy wiring region having substantially the same circuit layout pattern. 2. A memory cell array region formed in a substantially rectangular shape on a surface of a semiconductor substrate, a bit line balancing circuit arranged adjacent to a predetermined side of the memory cell array region and having a first circuit layout pattern, A bit line potential supply circuit disposed outside the bit line balancing circuit as viewed from the memory cell array region and having a second circuit layout pattern; and each disposed at both ends of the bit line potential supply circuit, 2. A semiconductor memory device comprising: a second circuit layout pattern and a second dummy wiring region having substantially the same circuit layout pattern. 3. The semiconductor memory device according to claim 1, wherein said first dummy wiring region is provided in the same manufacturing process as a predetermined wiring of said bit line potential supply circuit. 4. The semiconductor memory device according to claim 3, wherein said predetermined wiring of said bit line potential supply circuit is a polysilicon film.