JP2871994B2 - Semiconductor wafer production method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a semiconductor wafer, and more particularly to a method for controlling production of a semiconductor wafer production line which requires many processing steps.

[0002]

[Prior art]

(1) First, the flow of a semiconductor wafer between each step in a semiconductor wafer production line including a plurality of processing steps will be described. The semiconductor wafer production line has a very large number of processing steps of 300 to 500 steps, and the manufacturing equipment for each step is very expensive. Therefore, the equipment is not arranged in a line according to the processing procedure. Symbol C1 to C8
As shown in FIG. 1, the process is performed by repeatedly using the equipment in each step.

In addition, the processing conditions in the manufacturing apparatus change in each step according to the progress of the processing steps. Even when processing is performed in the same manufacturing apparatus, the processing conditions are different between the first processing and the second processing. .

In addition, the types of semiconductor wafers are very large, and the processing conditions are different for each type, and the number of processed semiconductor wafers per lot is also different.

[0005] Here, in the case where the own process is performed centering on the symbol C6 in FIG.
The process of symbol C2 and symbol C5, which is referred to as a post process, is symbol C2, symbol C3, symbol C4 and symbol C4.
This is the seventh step. Since these steps are complicatedly entangled and processed, it is difficult to synchronize the semiconductor wafer processing between the steps. Therefore, each process processes semiconductor wafers in an independent job shop format,
At the time when the process of the self-process is completed, the semiconductor wafer is sent out without being aware of the in-process state of the post-process, and the extrusion method for the post-process has been performed.

(2) Next, the flow of the semiconductor wafer in each step will be described. The symbol D1 in FIG. 4 is the time required to transport the semiconductor wafer between the semiconductor wafer storage shelf and the manufacturing apparatus, and the symbol D2 is the preparation and processing of the members required to process the semiconductor wafer. This is the time required for changing the conditions and installing the semiconductor wafer in the manufacturing apparatus, and the symbol D3 is the time required for processing. Symbol D6 is a time required for removing the semiconductor wafer from the manufacturing apparatus or cooling the semiconductor wafer after the processing of the semiconductor wafer is completed.
Is the time required to transport the semiconductor wafer to the next step. A lot to be processed with the highest priority is selected from a plurality of lots in process of the own process, and after the processing of the lot with the symbol L6 is completed as shown in FIG. 4 (the symbol D4), humans rely on intuition and experience. The processing was started by measuring the processing start timing of the lot indicated by symbol L7.

[0007]

The above-described conventional semiconductor wafer production has the following problems.
(1) Each process independently processes a semiconductor wafer,
Since the processing of the semiconductor wafer is not synchronized between the processes, it is not known when the semiconductor wafer is transferred from the previous process to the own process, and the manufacturing apparatus is vacant. Therefore, the operation rate is reduced even though the manufacturing apparatus is expensive. (2) If the processing capacity of the manufacturing equipment in all the processes of the semiconductor production line is equal and the semiconductor wafer can be processed in the same processing time, the in-process state of each process is always constant, so that the in-process There is no particular problem even if you are not aware of the state.

However, in actuality, the processing capacity of the manufacturing apparatus in each process is not uniform and the processing time is different. Further, there is a manufacturing apparatus in which the processing time varies depending on the number of semiconductor wafers.

Here, if the semiconductor wafer is transported to the post-process without being aware of the state of the work-in-process in the post-process, the difference in processing capability between the self-process and the post-process or the difference in the processing time causes the processing in the post-process. Even if the capacity is exceeded, the semiconductor wafer is transferred to a subsequent process, and the semiconductor wafer has a work in progress more than necessary.

If the number of processes in process continues to increase, this process becomes a bottleneck process in a semiconductor wafer production line, and the semiconductor wafer is not transferred to another process, so that the target production amount cannot be satisfied. (3) The timing of starting the processing of a plurality of semiconductor wafers in the process is qualitatively determined by human intuition and experience.

In addition, one worker performs post-processing after semiconductor wafer processing, transport to the next process, transport from a shelf to a manufacturing apparatus, and preparation before processing.

Accordingly, idle time is generated during the processing of the semiconductor wafer as shown by symbols D4 to D5 in FIG.

As a countermeasure against the above problem (2), semiconductor wafers are put into a production line in an amount equal to or greater than the required number of productions in order to obtain a sufficient number of processes in each process, and the operation rate of the manufacturing apparatus is maintained. Was.

For this reason, the number of processes in progress on the semiconductor wafer production line increases, and it takes time to process the semiconductor wafer, and the lead time from when the semiconductor wafer is loaded until it is stored is extended.

An object of the present invention is to provide a mechanism for reducing useless work in a semiconductor wafer production line and for shortening the transport time and setup time required for semiconductor wafer processing.
It is to improve production efficiency and shorten lead time.

[0016]

According to the semiconductor wafer production method of the present invention, the transfer time, the product processing time, and the setup time are quantitatively determined from past results, and a request from a post-process is triggered. At the start of processing, the computer automatically predicts the time at which semiconductor wafer processing will be completed in the manufacturing equipment, and by the predicted semiconductor wafer processing completion time, the transfer time of the next semiconductor wafer to be processed by the manufacturing equipment to the manufacturing equipment. Calculates the transfer start time by calculating the previous (outer) setup time and the time required for the pre-process from the predicted semiconductor wafer process end time, and transfers the semiconductor wafer during the semiconductor wafer process and then processes the semiconductor wafer Of the next semiconductor wafer can be started at the same time as the end of the process To so.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a process explanatory view for explaining a method of processing a semiconductor wafer by synchronizing two processes of a symbol K1 process and a symbol K2 process as one embodiment of the present invention. As shown in FIG. 1, a processing end trigger (symbol A6) of the semiconductor wafer is predicted by a processing start trigger from a processing apparatus with a symbol K2 at a symbol A1. The computer calculates this processing time based on the time (actual value) required for the past processing.

Next, the symbol K1 which is a pre-process of the symbol K2 process
A search is made for a semiconductor wafer that can be processed by the manufacturing apparatus notified of the start of the process in the process. Thereafter, the transfer time from the shelf (symbol A2), the setup before processing (symbol A3), the processing time (symbol A4), and the transfer time to the symbol K2 step (symbol A2) required for processing the semiconductor wafer in the symbol K1 step ( Symbol A
4) The total time required for the external setup before the process in the symbol K2 process is determined.

The computer also calculates individual times of transport, inner setup before processing, processing and outer setup before processing used at this time based on the time (actual value) required for past processing. Here, the predicted processing end time (symbol A6)
Then, a value obtained by subtracting the obtained total time from the above is set as the transfer start time. By starting the transfer at this transfer start time, the symbol K2
During the processing of the process, the symbol K1 which is a pre-process of the symbol K2
The process, transport, and setup of the process are completed, and the process of the next semiconductor wafer can be started at the process end time of the process of symbol K2 (symbol A6), so that the process of symbol K2 does not have an extra process. Semiconductor wafer production can be performed.

Here, the inner setup is a setup in which the manufacturing apparatus is occupied, so that the inner setup and the semiconductor wafer processing cannot be performed at the same time, and the outer setup can be performed without occupying the manufacturing apparatus. That is, it can be performed simultaneously with semiconductor wafer processing.

FIG. 2 is a view for explaining a flow of a semiconductor wafer when a transfer time is longer than a predicted end as another embodiment of the present invention. In order to simplify the description of the processing contents, the setup time is omitted and described. The processing start time (symbol B2) of the lot L1 is used as a trigger to predict the processing end time (symbol B2). At this time, the next lot L2 is determined. If the lot L2 is immediately started to be conveyed (symbol B3) but the processing end time of the lot L1 is not inquired (symbol B2), the lot L2 is conveyed as it is. The transport of the lot L3 is started (symbol B3) in time for the processing end time of L2 (symbol B2). The processing start time (symbol B2) of the lot L2 is used as a trigger to predict the processing end time (symbol B3) of the lot L3, and the processing end time (symbol B) of the lot L3.
Start transporting lot L4 in time for 2) (symbol B
3) Yes. Thereafter, with the start of the process as a trigger, the semiconductor wafers are transferred one after another, and the next semiconductor wafer can be processed simultaneously with the processing end time.

[0022]

As described above, the following effects can be obtained by the present invention. (1) An operation rate of the manufacturing apparatus can be improved by transporting a lot to be properly processed to the manufacturing apparatus. (2) Since the processes are not concentrated on the specific process of the semiconductor wafer production line, the semiconductor wafer is not conveyed to the specific process, and the required number of processes in each process can be performed, so that the target production amount can be satisfied. (3) Reduction of the waiting time of semiconductor wafers and reduction of the number of processes in process by optimizing the start timing of semiconductor wafer processing in the manufacturing apparatus (If the present invention is applied to all processes, the number of processes in each process is reduced to zero. Can reduce the time spent waiting for processing another semiconductor wafer, thereby reducing the production lead time of the semiconductor wafer.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an example of a case where an embodiment of the present invention is performed between two processes.

FIG. 2 is an explanatory diagram showing a countermeasure in a case where a transport time is longer than a predicted end processing time in another embodiment of the present invention.

FIG. 3 is a diagram showing a sequence of steps in a conventional semiconductor wafer production line.

FIG. 4 is a diagram showing a flow of a conventional semiconductor wafer through a processing step until processing is completed.

[Explanation of symbols]

 A1 Processing time A2 Transport time A3 Inner setup time before processing A4 Processing time A5 Outer setup time before processing A6 Processing end A7 Product flow A8 Actual time A9 Estimated time K1 to K2 Process B1 Processing start B2 Processing end B3 Transport start B4 Transport time B5 processing time B6 idle time L1 to L5 lot C1 to C8 process in1 input out1 receiving D1 transport time D2 pre-processing setup time D3 processing time D4 processing end D5 processing start D6 processing setup time D7 empty time D8 empty time L6-L7 Semiconductor wafer

Claims (1)

(57) [Claims] 1. In a semiconductor wafer production line comprising a plurality of processing steps, at the start of semiconductor wafer processing, the time at which the semiconductor wafer processing is completed by the manufacturing apparatus is set to the time (actual value) required for the past processing. Predict based on
By the predicted semiconductor wafer processing completion time, the next semiconductor wafer to be processed by the manufacturing equipment is transported to the manufacturing equipment, and necessary setup before and after the processing is completed. A semiconductor wafer production method characterized by optimally performing a flow of a semiconductor wafer in a semiconductor wafer production line by performing the above-mentioned processing.