JP2882612B2 - Synchronous circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous circuit used in a data recording / reproducing device such as a magneto-optical disk device.

[Prior Art] In recent years, data recording / reproducing apparatuses have been used for a wide range of applications. In particular, recently, the amount of data to be handled has been dramatically increased, and optical recording / reproducing devices capable of recording a large amount of data, such as optical disk devices, have been attracting attention.

By the way, data is recorded serially in the above-mentioned optical disk device and the like, and at the time of reproduction, this serial data is read out in synchronization with a synchronization signal of a synchronization area which is coded and recorded at the leading end of the data area. .

By the way, when these recorded data are reproduced,
Even slight misreading can often have serious adverse effects. For this reason, during recording, the data is rearranged and the CIRC (Cross Interleave Read Solomon Cod
An error correction code such as e) is added. On the other hand, when reading, an error in a specific section can be corrected through an error correction circuit (ECC circuit).

However, in the case of reading, the error may exceed the section of the error correction function due to, for example, the timing of the synchronization signal being shifted due to the eccentricity of the disk or the like.

For this reason, the first type disclosed in Japanese Patent Application Laid-Open No. 58-161111
In the conventional example, the part which is usually regarded as the data area also
Further, a synchronization signal (referred to as a resynchronization signal to distinguish it from a normal synchronization signal) is recorded, and at the time of reproduction, data is decoded using the resynchronization signal. The error in the specific section can be corrected by the error correction function.

In the first conventional example, error correction does not function properly if no essential synchronization signal is detected.

For this reason, more generally, when the synchronization signal is lost due to scratches, dust, or the like, the synchronization signal is supplemented so that even if an error occurs, the synchronization signal can be limited to a specific section. Error can be corrected by the error correction function.

FIG. 7 shows a second conventional example. In this figure,
When the digital signal A from the input terminal 1 is taken into the synchronous signal pattern detecting circuit 3 by the clock applied to the clock input terminal 2 in synchronization with the digital signal A, a signal indicating that the synchronous signal pattern has been detected. Is output. This is the pattern output 10 on the time chart shown in FIG.

The clock is N-ary counter 4 and M-ary counter 5
Is also supplied. Here, the values of N and M are set smaller than N and larger than M for one block B shown in FIG. 8E, that is, the value P obtained by adding the number of clocks of the synchronization signal S and the data signal D. Gate 4a of N-ary counter 4
Is opened before the synchronization signal pattern is output, and is output as a synchronization output if the synchronization signal pattern comes (see FIG. 8 (b)).

However, in the pattern output 10 of FIG. 8A, when the synchronization signal pattern is lost as shown by the dotted line 10a,
After the gate 4a of the N-ary counter 4 opens, the output of the M-ary counter 5 is output via the gate 5a as a supplement of the synchronizing signal, as indicated by 12 in FIG. 8 (c). When the synchronizing signal is output from the gate 5a, the N and M-ary counters 4, 5 are reset. This means that an N to M clock section window is opened for the synchronization signal pattern as shown in FIG. 8 (d), and if the synchronization signal pattern comes in this section, the synchronization signals 13a, 13b, 13
Output as c, if sync signal pattern 1
If 0a is lost, the operation is performed so as to replenish the synchronization signal 13m at the time of the last M clocks and prevent synchronization disturbance.

However, the second prior art has the following problems. In other words, when a digital signal is lost for a long period (a plurality of blocks) due to large dust or scratches, the position of the synchronous pattern detection window formed by the N-ary counter 4 and the M-ary counter 5 shifts with each refill. For this reason, when a correct synchronization pattern comes after replenishment a plurality of times, the position of the window is greatly displaced, so that the synchronization signal cannot be detected and the recovery of the synchronization signal is delayed. FIG. 9 shows this state in a time chart. In FIG. 9, reference numeral 14 denotes a pattern output, 15 denotes an open period of a synchronous pattern detection window, and 16 denotes a synchronous output. When the synchronization signal patterns 14a, 14b are lost as indicated by the dotted lines in the pattern output 14, the synchronization signals 16a, 16b supplemented at the ends 15a, 15b of the gate 5a of the M-ary counter 5
Is output. But in the fourth position the synchronization pattern
Outputs the 14 _2, but outputs a synchronizing signal 16c supplemented again since the shift position of the window 15 can not output a synchronization signal in the correct position until a synchronization signal pattern again to the position of the window 15. That is, it is slow to recover the output of the normal synchronization signal.

For this reason, Japanese Patent Publication No. 1-46938 solves this disadvantage.

[Problems to be Solved by the Invention] However, in Japanese Patent Publication No. 1-46938, even if the synchronization signal can be detected or not, basically, the window for detecting the next synchronization pattern has the same width. Therefore, this window is wide even when the synchronization signal is detected continuously, and if the input data to the synchronization signal pattern detection circuit is disturbed and the synchronization pattern is erroneously detected, the synchronization signal is detected at the wrong position. Is output.

On the other hand, if the window for detecting the synchronization pattern is set to be narrow, there is a disadvantage that the synchronization signal cannot be detected if the timing of detecting the synchronization pattern is shifted due to, for example, vibration or other disturbance.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a synchronization circuit capable of reducing erroneous detection of a synchronization signal and correctly reproducing a data signal.

[Means for Solving the Problems and Action] In the present invention, the synchronization pattern detection window generating circuit 51 having a configuration as shown in FIG. Even if the pattern is erroneously detected, the synchronization signal 53 is not output erroneously.

The digital signal A input from the data input terminal 1 is input to the synchronization pattern detection circuit 3 together with the clock applied to the clock input terminal 2, where the synchronization pattern is detected and output to the AND gate 4a. The clock is also input to the synchronization pattern detection window generation circuit 51, which outputs a normally narrow detection window signal 52 to the AND gate 4a.The output of the AND gate 4a is output to the OR gate 5a and the synchronization pattern detection window is output. When it is input to the generation circuit 51 and no synchronization pattern is detected, a supplementary synchronization signal is output to the OR gate 5a. Therefore, a synchronization signal is output from the synchronization signal output terminal 6 of the OR gate 5a.

When the synchronization pattern is lost, the synchronization pattern detection window generation circuit 51 widens the width of the next detection window to make it easier to detect the synchronization pattern. Further, the detection window generating circuit is provided by synchronizing a synchronization pattern and one block including data.
By controlling 51, even if digital data is continuously lost, the position of the detection window and the synchronizing signal pattern do not shift.

EXAMPLES Hereinafter, the present invention will be described specifically with reference to the drawings.

2 to 4 relate to a first embodiment of the present invention, FIG. 2 is a configuration diagram of a synchronization circuit of the first embodiment, and FIG. 3 is a configuration of a data recording / reproducing apparatus having the first embodiment. FIG. 4 is an explanatory diagram of the operation of the first embodiment.

As shown in FIG. 3, a data recording / reproducing apparatus 21 having the first embodiment has an optical head 24 disposed opposite an optical disk 23 as an optical recording medium which is driven to rotate by a spindle motor 22. A head feed mechanism such as a motor (abbreviated as VCM) 25 is movable in the direction T crossing the track (that is, the disk radial direction) so that information can be recorded or reproduced on an arbitrary track. .

A laser diode (semiconductor laser) 26 as means for generating a light beam is housed in the optical head 24 so that the optical disk 23 can be irradiated with the light beam via an objective lens 27. The light beam reflected by the optical disk 23 is received by a photodetector 28 via an objective lens 27 and a beam splitter (not shown), and the output of the photodetector 28 is input to a data recording / reproducing circuit 29, where a track error is detected. A signal and a focus error signal are generated, and the recording data recorded on the optical disk 23 is demodulated. In this demodulation, data is demodulated in synchronization with a fixed synchronization pattern provided at the head of each data area of the optical disc 23.

The detection of the synchronization signal used for demodulating this data is performed by the synchronization circuit 31 shown in FIG.

The same components as those in the conventional example shown in FIG. 7 are denoted by the same reference numerals.

The data A input to the data input terminal 1 of the synchronization signal pattern detection circuit 3 synchronizes with a clock applied to the clock input terminal 2 to determine whether the data A matches a predetermined synchronization signal pattern. Detection is performed, and an output signal 32 is output from the synchronization signal pattern detection circuit 3. This output signal 32 is output while the AND gate 4a is open,
When the signal is output when the Q output 34 of the JK flip-flop 33 is “H”, the signal is output as a synchronization signal 35.

For example, each data part in the data shown in FIG.
The synchronization signal patterns S1, S2, S3, ... at the beginning of D1, D2, D3, ...
Is detected, a signal 35 shown in FIG. FIG. 4B also shows a case where some of the synchronization signal patterns are not detected.

The clocks are an N'-ary counter 36, an M'-ary counter 37 and a P-ary counter 37 each having a reset input R.
It is input to each of the 38 clock input terminals.

The N 'base counter 36 and the M' base counter 37 change from N1 base to N2 base depending on the input level to the set terminal S, respectively.
Is a counter that can be switched from hexadecimal and M1 to M2, RS
The Q output 40 of the flip-flop 39 is applied to each set terminal S.

The reset terminal R of the flip-flop 39 receives the output of the gate 4a, that is, the synchronization signal 35, and the set terminal S receives the output 42 of the AND gate 41, that is, the supplementary synchronization signal.

For example, when the synchronizing signal 35 is output, the flip-flop 39 is reset, so that the Q output 40 is “L”.
Level, in this case N 'base counter 36 and M'
The ternary counter 37 operates as an N1-based and M1-based counter, respectively.

The N1-ary outputs a pulse output 43 which becomes “H” slightly before the timing at which the normal synchronization signal pattern is detected to the JK flip-flop 33, and at the rise of the pulse output 43,
The Q output 34 of the JK flip-flop 3 becomes "H", and opens the AND gate 4a.

In addition, the pulse in M1 is later than the opening timing in N1. For example, the pulse output 44 is output to the AND gate 41 at the end of the timing at which the normal synchronization signal pattern is detected or at a timing thereafter. Since the Q output 46 of the RS flip-flop 45 set by the output pulse 43 of the N 'base counter 36 is input to the AND gate 41, the output pulse 44 of the M' base counter 37 passes through the AND gate 41. The signal is input to the reset terminal R of the JK flip-flop 33, the Q output 34 is set to "L", and the AND gate 4a is closed.

That is, when the synchronization signal 35 is output, the Q output 34 of the JK flip-flop 33 is set to open with a narrow width before the timing when the synchronization signal pattern is normally detected and after the timing when the detection is completed. The detection operation of the next synchronization signal pattern is set to be performed in the narrow detection window. In this standby state, when the synchronizing signal 35 is output, the synchronizing signal 35 is applied to the K input terminal of the JK flip-flop 33 to close the Q output 34 which is a window signal for detecting the synchronizing signal pattern, 45 is reset, the AND gate 41 is closed, and the M'-adic counter 37
The output 44 is blocked by the AND gate 41, in which case the supplementary synchronization signal 42 is not output.

The synchronizing signal 35 is input to the reset terminals R of the N'-decimal counter 36, the M'-decimal counter 37, and the P-decimal counter 38 via the OR gate 47, and resets each.

The output 48 of the P-base counter 38 is also applied to the reset terminal R of each of the counters 36, 37, 38 via the OR gate 47. The P-ary counter 38 is set so as to output an output 48 for resetting at a time interval equal to the cycle of one block B. Even if the undetected state of the synchronization signal pattern continues, the detection window signal 34 and the synchronization signal The position of the pattern is not shifted.

On the other hand, when the synchronization signal 35 is not output, the flip-flop 45 is not reset, so that the N'-ary counter 36
After the timing at which the normal synchronizing signal pattern is to be detected, the output 44 of the M'-decimal counter 37 passes through the AND gate 41 and the supplementary synchronizing signal.
42 becomes a signal 49 through the OR gate 5a, and becomes a synchronous output terminal 6
To be output. This supplementary synchronization signal 42
Sets the flip-flop 39, sets its Q output 40 to the "H" level, and sets the N'-ary counter 36 and the M'-ary counter
37 is switched to N2 base and M2 base respectively.

The N2 base outputs the pulse output 43 before the N1 base, and the M2 base outputs the output 44 later than the M1 base. In other words, when the synchronization signal 35 is not output, it becomes a detection window signal for the synchronization signal pattern.
The Q output 34 of the JK flip-flop 33 is opened with a wide width so that the next synchronization signal pattern can be easily detected.

In the first embodiment configured as described above, when the synchronization signal 35 is detected, the detection window of the synchronization signal pattern is narrowed to prepare for the detection of the next synchronization signal pattern.
The possibility of erroneous detection is reduced. Further, when the synchronization signal pattern cannot be detected, the supplementary synchronization signal 42 is output, and the detection window is widened so that the synchronization signal pattern can be easily detected. Further, even when the synchronization signal pattern has not been detected by the P-ary counter 38, the timing at which the detection window signal 34 opens does not deviate from the synchronization signal pattern.

Next, the operation of the first embodiment will be described with reference to FIG.

When the data A as shown in FIG. 4A is input to the synchronization signal pattern detection circuit 3, slightly before the time when the synchronization signal pattern (for example, S1) is input (before the synchronization signal pattern S1). , The synchronization signal 35 is output), N ′
The decimal counter 36 outputs a pulse output 43 as shown in FIG.
The output 43 is input to the JK flip-flop 33, and the Q output 34 is set to "H" as shown in FIG. 11C to open the AND gate 4a. Therefore, when the synchronization signal pattern detection circuit 3 normally detects the synchronization signal pattern as shown in FIG. 4 (b), the output 32 passes through the AND gate 4a,
It becomes a synchronization signal 35 shown in FIG. 4D and is output from the output terminal 6 (and further through the OR gate 5a).

The synchronizing signal 35 is applied to the K input terminal of the JK flip-flop 33, and the Q output 34 is set to "L" at the falling edge as shown in FIG. 4 (c). The synchronizing signal 35 resets the flip-flop 39 and holds its Q output at "L" as shown in FIG.
The M′-adic counter 37 is kept at the N1 base and the M1 base, respectively. Further, the synchronizing signal 35 resets the counters 36, 37, and 38 and causes the counters 36, 37, and 38 to perform the timing operation again at the falling edge of the synchronizing signal 35, and detects the next synchronizing signal pattern. To start.

In this state, the counters 36 and 37 are N1 and M1 respectively.
And the detection window has a narrow time width.

For example, if the synchronization signal pattern detection circuit 3 fails to detect the next synchronization signal pattern, the circuit 3 does not output 32 (indicated by the dotted line in FIG. 4 (b)). However, before the time at which the sync signal pattern is normally detected, the N'-ary counter 36 outputs the pulse output 43 as shown in FIG.
And the flip-flop 45 is set, the Q output is set to "H" as shown in FIG.
Open 41, and then this flip-flop 45
The gate 41 is kept open without being reset by the above operation, and the output 44 of the M'-adic counter 37 shown in FIG. 4 (h) is passed through the gate 41 as a supplementary synchronization signal 42 shown in FIG. 4 (e). Output. This supplementary synchronizing signal 42 resets the JK flip-flop 33 and outputs the Q output as shown in FIG.
34 goes low, closes gate 4a and flip-flop
39 is set and its Q output 40 is set as shown in FIG.
Is set to "H", and an N'-ary counter is set as shown in FIG.
36 is converted to N2 base, and as shown in FIG.
To M2. In this state, the Q output 34 of the JK flip-flop 33 serving as a detection window opens before the time when the N'-ary counter 36 normally detects a synchronization signal pattern as an N2-ary counter, and the M'-ary counter 37 closes at a time later than the time when the detection of the synchronization signal pattern normally ends, so that the detection window of the synchronization signal pattern is widened, and the detection of the synchronization signal pattern becomes easy.
When the synchronization signal pattern is detected by the wide detection window, the flip-flop 39 is reset,
The N 'base counter 36 is switched to N1 base, and the M' base counter 37 is switched to M1 base. (FIG. 4 shows that the timing of opening the detection window does not shift even if the detection of the synchronization signal continues to fail.) According to the first embodiment, the synchronization signal pattern is detected at a predetermined timing. In this case, the time width of the detection window for detecting the next synchronization signal pattern is narrowed, so that false detection of the synchronization signal pattern due to noise or the like can be reduced. If no synchronization signal pattern is detected, the time width of the detection window for detecting the next synchronization signal pattern is widened. Operation can be recovered quickly. For this reason,
This is effective for data reproduction.

In the first embodiment, when the detection of the synchronization signal fails while the detection window is open, the two counters 36 and 37 are switched to widen the detection window. It is clear that the time width of the detection window may be widened by switching only the counter 36 or 37.

Further, even when the detection of the synchronization signal pattern fails and the detection window is widened, if the detection of the synchronization signal pattern fails, the time width of the detection window may be further increased.
In this method, a flip-flop (referred to as 39 ') is further provided, the Q output 40 of the flip-flop 39 is applied to the set terminal, the synchronization signal 35 is applied to the reset terminal, and the Q output is applied to the second output of the counters 36 and 37. When the input level to the first and second set terminals by the flip-flops 39 and 39 'is "H", the N'-ary counter is set to N3.
In advance, the M'-decimal counter 37 may be switched to M3.

In this way, when the detection of the synchronization signal pattern fails, the detection window may be sequentially widened. By doing so, it is possible to effectively cope with the initial operation and the like.

Next, a second embodiment of the present invention will be described below with reference to FIGS. In this embodiment, the part of the synchronization pattern detection window generating circuit is changed.

The recording format 63a shown in FIG. 6A includes a data portion composed of an ID (track or sector address) or read data, and a synchronization pattern for synchronizing the reading of the data portion. Here, 1T indicates one segment of data, which has a synchronization pattern at the beginning. As the synchronization pattern, a pattern that does not occur in the data is used. However, there are cases where the synchronization pattern cannot be detected due to a defect or dust on the medium, and cases where the same pattern as the synchronization pattern occurs in the data.

In FIG. 6 (a), the first, third and fourth are cases where the synchronization pattern cannot be detected. In the first and fourth cases, the same pattern as the synchronization pattern except for where the synchronization pattern is written is used. This is the case when detecting.

This circuit detects a synchronization pattern from a PLL circuit 64 that generates a data clock for detecting data from an input signal and a synchronization pattern from the input signal. When the input signal matches a predetermined synchronization pattern, a synchronization pattern detection signal 65a is generated. A synchronous pattern detection comparator 65 to be output, a timing generation counter 66 for generating various timings in accordance with the beginning of data, a window generation circuit 67 for generating a window for synchronous pattern detection determination, the (synchronous pattern) detection A synchronization detection determination circuit 68 for determining the detection of a synchronization pattern from the signal 65a and the window signal 67a output from the window generation circuit 67, and a synchronization signal detection determination circuit 68a output from the synchronization detection determination circuit 68 Down count that outputs a determination signal as to whether or not a synchronization signal has not been detected during the signal 67a 69, the down-counting by the synchronization signal detection determination signal 68a, composed of the window width counter 70. which is preset by the synchronization signal non-detection signal 69a output from the down counter 69.

The PLL circuit 64 generates a clock 64a synchronized with the input signal reproduced from the recording format on the recording medium (see FIG. 6 (a)). Output to counter 66. The synchronization pattern detection comparator 65 detects the synchronization pattern by comparing the input signal fetched via a shift register or the like (not shown) in synchronization with the clock 64a with the data of the synchronization pattern, and FIG. 6 (b). The synchronization pattern detection signal 65a shown in FIG. The timing generation counter 66
Is preset at the beginning of the data by the synchronization signal detection determination signal 68a, and by counting the clock 64a,
The number of data bits is counted from the beginning of the data, the timing of various signals is generated, and output data 66 a is output to the window generating circuit 67.

The window generating circuit 67 includes a window width counter
The window width is determined by the window width count value 70a of 70, and the output data 66 of the timing generation counter 66 is determined.
According to a, the position of the synchronization pattern of the next data is predicted from the beginning of the previous data (when the synchronization pattern is detected), and the window signal 67a shown in FIG. Output to That is, the window signal 67a functions as a gate that opens before the predicted position of the synchronization pattern of the next data and closes after the predicted position.

The synchronization detection determination circuit 68 determines whether the window signal 67a
When the sync pattern detection signal 65a is input during the period when the sync signal is output, the sync signal detection determination signal 68 shown in FIG.
Outputs a. The synchronization signal detection determination signal 68a is applied to the reset terminal of the down counter 69, and the window signal
When the synchronization signal detection determination signal 68a is input during the period 67a, the signal is cleared. Conversely, when the synchronization signal detection determination signal 68a is not input during the window signal 67a, the carry output is performed as shown in FIG. ) Is output to the window width counter 70. The window signal 67a is applied to the load terminal of the down counter 59. While the window signal 67a is "L", the window signal is output from the window width counter 70, and the preset data applied to the preset terminal is loaded. When the count reaches 0, the countdown is performed from the preset data. When the count value reaches 0, the carry output, that is, the synchronization pattern undetection signal 69
a is output to the window width counter 70. This preset data is variably set to match the window width of the window signal 67a. (Thus, the down counter
The count operation of 69 is indicated by "H" in FIG. 6 (f). However, when the count operation is performed after being cleared once, no carry output is made. The window width counter 70 outputs the synchronization pattern undetected signal.
Preset data is preset in 69a, and the synchronization signal detection determination signal 68a is counted down. Therefore, every time the synchronization signal detection determination signal 68a is continuously input, the sixth
As shown in FIG. 9G, the window width count value 70a, which becomes smaller sequentially, is output to the window generation circuit 67.
Preset data corresponding to the reduced window width count value 70a is output to the down counter 69. When the synchronization signal detection determination signal 68a continues several times, the window width becomes the minimum, and further, the synchronization signal detection determination signal 68a
, The minimum window width is maintained.
(Indicated by min in FIG. 6 (g).) On the other hand, when the synchronization pattern non-detection signal 69a is input, the window width counter 70 counts the maximum window width as shown in FIG. 6 (g). The value 70a will be preset. According to this embodiment, when the synchronization signal is detected, the window width for detecting the next synchronization signal is sequentially reduced, and
In addition to preventing erroneous detection of the synchronization signal, when the detection of the synchronization signal fails, the window width is maximized so that the next synchronization signal can be reliably detected.

In the second embodiment, when the detection of the synchronization signal fails, the window width is maximized. However, the window width may be sequentially increased each time failure occurs.

[Effects of the Invention] As described above, according to the present invention, when a synchronization signal is detected, a narrow detection window is used to prevent erroneous detection of the synchronization signal, and the synchronization signal pattern is set within the time when the detection window is open. If the detection of the synchronization signal pattern fails, the time width of the detection window for detecting the next synchronization signal pattern is set to be wide. Signal pattern detection can be performed quickly,
The reliability of the operation of reproducing recorded data can be improved.

[Brief description of the drawings]

FIG. 1 is a conceptual configuration diagram of the present invention, FIGS. 2 to 4 relate to the first embodiment of the present invention, FIG. 2 is a specific configuration diagram of the first embodiment, and FIG. FIG. 4 is a schematic configuration diagram of a data recording / reproducing apparatus having an embodiment, FIG. 4 is a timing chart for explaining the operation of the first embodiment, and FIGS.
5 is a block diagram of the second embodiment, FIG. 6 is a timing chart for explaining the operation of the second embodiment, FIG. 7 is a block diagram of a conventional example, and FIG. 8 is FIG. Operation explanatory diagram, ninth
FIG. 7 is an explanatory diagram for explaining the drawbacks of the conventional example of FIG. 1 Data input terminal 2 Clock input terminal 3 Synchronous signal pattern detection circuit 4a, 5b Gate 6 Synchronous output terminal 33, 39, 45 Flip-flop 36, 37, 38 Counter 51: Synchronous pattern detection window generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 7/08

Claims (1)

(57) [Claims] A synchronization signal pattern arranged at regular time intervals in continuous digital data is detected and a synchronization signal is output. When the synchronization signal is lost, a supplementary synchronization signal for supplementing the synchronization signal is output. A synchronization circuit for outputting, comprising: a pattern detection means for detecting the synchronization signal pattern; and a gate circuit provided at an output of the pattern detection means, wherein the first time is earlier than a timing at which the synchronization signal is generated. After the gate is opened, a synchronization signal is derived when an output of the pattern detection means is derived after the gate is opened, and a synchronization signal pattern for closing the gate at a second time later than the first time is detected. Output means for outputting a window signal, wherein the output means is reset at a gap of the synchronization signal, and the output of the pattern detection means is detected after the gate is opened. Synchronizing circuit, characterized in that the in the detection window signals and wide of the detection window signal in the absence.