JP2886976B2 - Quality class control method in the communication path of ATM exchange - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a quality class control method in a communication path of an ATM switch having a buffer memory in a switching element connecting a plurality of input / output highways, independently controlling a discard characteristic and a delay characteristic. ATM whose characteristics are not affected by cells of lower priority than its own cell
Aiming to provide a quality class control method in the communication path of the exchange, assigning multiple quality classes corresponding to the combination of the discard characteristic class and the delay characteristic class to the cell, and corresponding to the discard characteristic class to the input highway A plurality of individual buffer memories each corresponding to a class of the delay characteristic, and a plurality of individual buffer memories each corresponding to a class of the delay characteristic. A buffer amount measuring means for measuring the buffer usage of each individual buffer memory corresponding to each delay characteristic class is provided, between the input highway and each individual buffer memory provided corresponding to the discard characteristic class. A discarding means is provided for each discard characteristic class to discard cells, and the discarding control unit When the input cell is written into the individual buffer memory corresponding to the class of the discard characteristic, if the buffer usage from the buffer amount measuring means exceeds a preset threshold value for each class of the discard characteristic, the cell of the class is discarded. A delay control unit for performing discard control and outputting a cell to the output highway is provided, and the delay control unit is configured to perform priority control of a reading order from a plurality of buffer memories according to a class of delay characteristics.

[Industrial Application Field] The present invention relates to a quality class control method in a communication path of an ATM switch provided with a buffer memory in a switching element connecting a plurality of input / output highways.

In ATM exchanges, delay-sensitive communications such as voice and discard-sensitive communications such as data are centrally handled. On the other hand, there has been known an ATM exchange in which a switching element having a buffer memory is provided at each intersection of a plurality of input / output highways and a switching path is driven to form a communication path.

In the communication path of such an ATM exchange, the cell discard can be reduced by increasing the capacity of the buffer memory, but the delay increases. Conversely, if the capacity of the buffer memory is reduced, the delay is reduced, but there is a trade-off relationship such as increased cell discarding, and it has been difficult to process all communications centrally. Therefore, it is desired to control cell discarding and delay according to the characteristics of the cell.

[Prior Art] FIG. 6 is an explanatory diagram of a conventional example.

A in FIG. 6 shows the configuration of the ATM switch. A buffer memory 60 is provided at each intersection of a plurality of input highways (HW) # 1 to #P and a plurality of output highways (HW) # 1 to #Q. Output HW that identifies destination information (VPI / VCI, etc.) included in the header of a cell (usually composed of a header part of 5 bytes and a data part of 48 bytes) input from the input HW and corresponding output HW
The cells are stored in the buffer memory 60 connected to. The buffer memory 60 is provided for preventing collision when cells from a plurality of input HWs to the same output HW are input simultaneously, and the cells stored in the buffer memory are sequentially read out by the selector 61 corresponding to the output HW. Output to output HW.

In the conventional ATM switching system described above, the capacity of the buffer is limited. For example, when many cells are concentrated in one output HW, when cells cannot be stored in the buffer memory, the cells are discarded, and the buffer memory is lost. When a large number of cells are accumulated, the delay time of the cells increases. A conventional priority control method used in such a case is shown in FIG.

In this example, priority information indicating whether the priority is high or low is added to the header of the cell, and the buffer memory 60 corresponding to the input HW includes the high priority cell buffer memory 601 and the low priority cell buffer memory 602. It is composed of two parts. Input H
When a cell is input from W, the priority information of the cell is determined and stored in one of the two buffer memories 601, 602 depending on whether the cell is a high priority cell or a low priority cell. The stored cells are read by the read control unit 62 in the high-priority cell buffer memory.
Selector 6 is controlled so that 601 is read out first.
Output from 1. Therefore, in the conventional system,
As shown in C., when the delay amount is the vertical axis and the discard amount is the horizontal axis, the high priority cell has a small delay amount and a small discard amount, and the low priority cell has a large delay amount and a large discard amount. You will be under control.

[Problems to be Solved by the Invention] In the above-mentioned conventional method, since the discard characteristic and the delay characteristic cannot be controlled independently, only one-dimensional control of a high-priority class with a small discard and a small delay and a low-priority class on the contrary is possible. Since there is no control, there is a problem that control such as a small delay and a large amount of discard cannot be performed. Also, for example, if a low priority cell occupies the buffer memory, it is discarded even if the next high priority cell arrives. There was a problem that characteristics were affected.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a quality class control method in a communication path of an ATM exchange in which a discard characteristic and a delay characteristic can be independently controlled and the characteristic is not influenced by a cell having a lower priority than the own cell.

[Means for Solving the Problems] FIG. 1 (a) is a diagram of a first principle configuration of the present invention, FIG. 1 (b) is an operation explanatory view of the first principle configuration, and FIG. It is a 2nd principle block diagram.

In FIG. 1 (a) and FIG. 2, 1-1 to 1-n and 1'-1 to 1'-n are assigned to discarding means, and 2-1 to 2-n are assigned to each discarding class. Each area in the buffer memory, 3-1 to 3-n are buffer amount measuring means for measuring the buffer amount actually used in each area, 4, 4 'are discard control units, 5 is a delay control unit, 6 is a selector, 7 is a discard class identification means, and 8 is a class comparison means.

According to the present invention, a cell is provided with a class of discard and a class of delay, and a first configuration is to store one buffer memory provided at a position connecting an input highway to an output highway in a variable area allocated for each class. By changing the discard class of cells to be discarded in accordance with the buffer memory usage rate at that time, cells with a high discard class are protected, and reading with a higher delay class is prioritized. In the second configuration, when the buffer memory is full, if there is a class lower than the class of the input cell, the cell is discarded from the area of the lower class and the input cell is stored in an empty area.

[Operation] In FIG. 1 (a), as shown in B. in the input cell, a delay class (one of 1 to m) indicating the delay quality and a discard class (one of Is set in advance and input, and CL (m, n) is used to input 2
A class representing one quality is expressed. In this case, if the number representing the first delay class is small, the priority is high (the delay is small), and if the number representing the later discard is small, the priority is high (the discard is small). Each area 2 in the buffer memory
-1 to 2-n are used by physically dividing one buffer memory logically into n discard classes, and each area is further divided into m corresponding to the delay class.

Cells input from the input HW are supplied to the discarding means 1-1 to 1-n according to the discarding class. At this time, the discard control unit 4
Can be used to obtain the amount of use of each buffer memory from the buffer amount measurement means 3-1 to 3-n. On the other hand, the discard control unit 4
A table for discard control is provided as shown in A.
The discard control unit 4 performs discard control according to this table.

This table shows that the buffer usage is Q1 (usage rate 100%
), The input cells of all classes (1 to n) are discarded, and if the usage is Q2 (corresponding to a usage rate of 90%), cells of classes 2 to n are discarded (only class 1 is stored). ), And in the case of a used amount Qn (corresponding to a usage rate of 70%), only class n is discarded. The discard control unit 4 supplies the result of the judgment (whether or not to discard) to one of the discarding units 1-1 to 1-n corresponding to the input cell. If not discarded, the input cell is stored in the corresponding buffer memory area 2-1.
２−2-n. The delay control unit 5 assigns the area divided into the delay classes (1 to m) in each of the areas 2-1 to 2-n to a high priority class (numerical) as shown in B of FIG. ) Is read out with priority.

Next, the operation of the second principle configuration shown in FIG. 2 will be described.
2-n has the same configuration as that of FIG. 1, and the operation of storing the input cells from the input HW in the divided areas 2-1 to 2-n of the buffer memory corresponding to the discard class is performed. At this time, the discarding control unit 4 ′ is configured to perform
Check the amount of buffer memory where cells are stored from n
It is determined whether or not the buffer is full in which cells are stored in the entire buffer memory. As a result, if it is found that the buffer is full, then the discard class of the input cell is identified by the discard class identifying means 7, and it is determined whether or not a cell lower than the class is in the buffer. Discarding means 1'-1 corresponding to discarding the class
1'-n. In this way, a vacant space is created in the buffer memory, and the vacant area is used as a discard class area of the input cell and stored. If there is no cell of a class lower than the discard class of the input cell in the buffer, the input cell is discarded.

[Embodiment] FIG. 3 is a block diagram of the first embodiment, FIG. 4 (a) is a block diagram of the principle of a buffer memory according to the present invention, and FIG. 4 (b) is control of cell discard and delay in the first embodiment. FIG. 5 is a configuration diagram of the second embodiment.

First, the principle configuration of the buffer memory according to the present invention will be described with reference to FIG. In this example, the classes are CL1 to CLn
Here is an example.

The buffer memory 42 performs writing and reading of cells. In the free address queue 40, addresses of an area of one cell in which no cell in the buffer memory 42 is stored (free state) are sequentially stored as a queue. Further, a class 1 cell use address queue 41-1 to a class n cell use address queue 41-n are provided for each class, and the addresses of the cells which have been written in the buffer memory 42 are queued for each class.

In the operation of writing a cell into the buffer memory 42, when a cell is input, the class is identified and the empty address queue
If an empty address at the head of 40 (address 3 in the example in the figure) is assigned and writing is possible next (by discard control), the input cell is written to the assigned empty address in the buffer memory 42, and the identified class is The write address is stored in the cell use address queue 41 corresponding to.

The read operation is controlled so as to give priority to the delay priority class. For example, if priority is given to class 1, the address stored at the head of the class 1 (CL1) cell use address queue 41-1 (address 2 in the example of the figure). ) Is read from the buffer memory 42 as a read address. The read address 2 is stored in the free address queue 40.
Is stored at the back end.

Next, a first embodiment shown in FIG. 3 will be described. In the figure, 2
0 is a buffer memory, 21 is a quality class identification circuit, 22 is a cell arrival detection circuit, 23 is an empty address queue, 24 is a buffer usage measuring circuit, 25 is a class 1 (CL1) cell address queue, and 26 is a class 2 (CL2) ) Cell address queue, 27-1, 27
-2 is a comparison circuit, 28 is a read queue selection unit, and 29 is a read control unit.

In the first embodiment, a configuration relating to a buffer memory of one switching element in a communication path of an ATM exchange is shown. In this example, there are two quality classes. In this case, the delay of class 2 is smaller than that of class 1 but discarded less.

FIG. 4 (b) illustrates the control characteristics of cell discard and delay in this embodiment. When the use amount of the buffer memory 20 is 100%, both cells of class 1 and class 2 are discarded. In the case of%, cells of class 2 are discarded.
As for the delay priority, the cell of class 2 is read out prior to the cell of class 1.

The buffer memory 20 of the first embodiment is controlled according to the same principle as that of FIG. 4A, and the operation of FIG. 3 will be described below.
When a cell is input from the input HW, when the cell arrival is detected by the cell arrival detection circuit 22, the head address of the empty cell area in the buffer memory 20 is taken out from the empty address queue 23, and the arrival cell is transferred to the buffer memory 20 from that address. Attempt to write. At this time, the write decision is made according to the fourth
This is performed based on the discard characteristics shown in FIG. That is, the buffer usage measuring circuit 24 measures the current usage (usage) of the buffer memory 20, and supplies the usage to the comparison circuits 27-1 and 27-2. 100% is input to the comparison circuit 27-1 as the usage amount Q1 from another input terminal, and the usage amount is input to the comparison circuit 27-2.
80% is entered as Q2. As a result, the comparison circuit 27
If the used amount has not reached 100%, "1" is generated. In the case of a class 1 cell, "1" is generated from the AND circuit A1 and supplied to the buffer memory 20 as a write control signal to perform writing. Is performed, and at the same time, the CL1 cell address queue 25
Is stored with the write address (empty address) of the cell. When the used amount reaches 100%, the writing of the cell CL1 (and the cell CL2) is prohibited (0 "is generated from the comparison circuit 27-1).

When the used amount is 80% or less, the comparison circuit 27-2 generates “0”, and the AND circuit A2 generates a class 2 (CL2) cell write control signal. When the write address of the cell is stored and the used amount is 80% or more, "1" is generated from the comparison circuit 27-2 and the AND circuit
A2 is prohibited and class 2 cells are not written (discarded). Thus, the discard of the class 1 cell is reduced.

CL1 cell address queue 25, CL2 cell address queue 26
Is provided with an empty flag, and if at least one queue is stored, the flag is set to "1".
The read control unit 29 performs reading when a read enable signal (a control signal input at a timing when cell output is allowed in this switch) is input. First, the read control unit 29 monitors the empty flag of the cell address queue for each class by the read queue selecting unit 28, and if both classes 1 and 2 are written in the buffer memory, reads the class 2 cell first. . In this case, the head address of the queue is taken out from the CL2 cell address queue 26 and supplied to the buffer memory 20 via the gate G2 as a read address. The read cell is output to the output HW. The read address at this time is written in the free address queue 23 under the control of the read control unit 29.

In addition to the above, as the read control, a method of changing the read frequency between classes without assigning an absolute read priority for each class can be adopted.

 Next, the configuration of the second embodiment shown in FIG. 5 will be described.

In FIG. 5, reference numerals 20 to 23, 25, 26, 28 and 29 correspond to the respective devices having the same reference numerals shown in FIG. 3, and have the same names.

Also in the case of the second embodiment, as in the first embodiment, there are two quality classes. Class 2 is discarded more than class 1 but the delay is smaller, and class 1 delay is larger than class 2 but less discarded. Is the case.

The operation will be described below.
When the arrival of a cell is detected from the empty address queue 23, an attempt is made to write the cell that has arrived from the empty address queue 23 to the buffer memory 20. The determination of writing at this time is performed as follows. That is,
First, the quality class of the arriving cell is determined by the quality class identification circuit 21.
In addition to the above, a signal indicating whether or not the buffer memory is full from the free address queue 23 is taken out, and the full state of the buffer memory 20 input to the AND circuits A3 and A4 is determined when the free address is stored in the free address queue 23. This is indicated by a signal (empty flag) indicating that nothing is stored. If the signal indicating the full state is "1", the AND circuit A4 is inhibited and writing of the class 2 cell cannot be performed (discarded). However, if the input cell is class 1, if the buffer memory is full, and if a class 2 cell has already been written to the buffer memory 20 (the empty flag of the CL2 cell address queue is "1"), The read control unit 29 reads C from the read signal line 290
A read signal is output to the L2 cell address queue 26. As a result, the address (head of the queue) is read from the CL2 cell address queue 26 (the corresponding cell of class 2 is discarded), and written as a free address to the free address queue 23 via the OR circuit OR1 (the full state is released). ). Thus, the input class 1 cell is written to the position in the buffer memory 20 indicated by the empty address read from the empty address queue 23, and the address is stored in the CL1 cell address queue 25 at the same time. Thus, the discard of the class 1 cells is reduced.

At the time of reading, the read control unit 29 monitors the empty flags of the address queues 25 and 26 for each class, and if both classes 1 and 2 are written in the buffer memory 20, delay control for reading the class 2 cells first. I do. As a result, the delay of class 2 can be reduced.

[Effects of the Invention] According to the present invention, since the discard characteristic and the delay characteristic can be controlled independently, it is possible to realize control of various quality classes such as a class with a large number of discards but a small delay and a class with the opposite, for example. By limiting or discarding low-priority cells depending on the amount of buffer memory used or discarding them, the characteristics of the class are not affected by the influence of cells of a class having a lower priority than the input cell.

[Brief description of the drawings]

FIG. 1 (a) is a diagram showing the first principle of the present invention, FIG. 1 (b) is an explanatory diagram of the operation of the first principle, FIG. 2 is a diagram showing the second principle of the present invention, FIG. The figure shows the configuration of the first embodiment.
FIG. 1A is a diagram showing the principle configuration of a buffer memory according to the present invention.
FIG. 4B is a diagram showing control characteristics of cell discarding and delay in the first embodiment, FIG. 5 is a configuration diagram of the second embodiment, and FIG. 6 is an explanatory diagram of a conventional example. In FIG. 1 (a) and FIG. 2, 1-1 to 1-n: discarding means 1'-1 to 1'-n: discarding means 2-1 to 2-n: Each area 3-1 to 3-n: buffer amount measurement means 4, 4 ': discard control unit 5: delay control unit 6: selector 7: discard class identification means 8: class comparison means

Continuation of the front page (56) References JP-A-1-236843 (JP, A) JP-A-4-306031 (JP, A) IEICE technical report SE 87-75 IEICE technical report SE 87-92 (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 12/28 H04L 12/56

Claims (1)

(57) [Claims] 1. A quality class control method for a communication path of an ATM switch having a buffer memory in a switching element connecting a plurality of input / output highways, the cell corresponding to a combination of a class of a discard characteristic and a class of a delay characteristic. A plurality of quality classes are provided, a plurality of individual buffer memories corresponding to the class of the discard characteristic are provided on the input highway, and each of the plurality of buffer memories is a plurality of individual buffer memories respectively corresponding to the class of the delay characteristic. Buffer amount measuring means for measuring the buffer usage of each individual buffer memory corresponding to the delay characteristic class of each of the plurality of individual buffer memories corresponding to the discard characteristic class. Between each individual buffer memory provided for the class of discard characteristics Discarding means for discarding cells provided for each class of discarding characteristics is provided, and the discarding control unit converts input cells to the class of delay characteristics in the buffer memory corresponding to the class of discarding characteristics. When the buffer usage from the buffer amount measuring means exceeds the threshold set in advance for each class of the discard characteristic when writing to the individual buffer memory, control is performed to discard the cells of the class and the cells are output to the output highway. A delay control unit for outputting the priority class, wherein the delay control unit performs priority control of an order of reading from a plurality of buffer memories in accordance with the class of the delay characteristic. control method.