JP2820054B2 - Bus interface device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface device for performing an interface between a system bus and an input / output bus, and more particularly to a bus interface device for efficiently performing a write transaction from a processor on the system bus to an input / output device on the input / output bus. The present invention relates to a bus interface device for performing the operation.

[0002]

2. Description of the Related Art A bus interface device for connecting a system bus and an input / output bus may be divided into a plurality of units, such as an address system and a data system, depending on mounting requirements. That is, there are restrictions on the mounting units such as boards and LSIs on the area and restrictions on the number of input / output pins. If these are not satisfied, the mounting units must be divided. Although the mounting units divided in this way are usually in some form of synchronization, a slight shift may occur due to clock skew or the like. Therefore, data from a plurality of mounting units may collide on the bus. Such a collision of data transmitted from drivers on a plurality of mounting units on a bus is called bus fight. When this bus fight occurs, the driver that sends out data on the bus may be destroyed. On the other hand, in the related art, the bus fight is avoided by waiting for transmission of data for a certain period (hereinafter, referred to as "dead cycle").

Referring to FIG. 7, in the prior art,
When the I / O bus is an address / data bus,
By providing a dead cycle (A2) between the transmission of the address (A1) and the transmission of the data (A3) on the bus, a write transaction is executed on the input / output device while avoiding the bus fight. I have. If the input / output device does not receive the write transaction, a retry response indicating this is made (B1), whereby the address is again sent to the input / output bus (A1).
4), a dead cycle (A5), and data transmission (A6) are performed.

Further, Japanese Patent Publication No. 4-61387 discloses that
There is described a technique for reducing the dead cycle to half of one cycle to speed up data transfer. In this technique, the dead cycle is reduced by transmitting the output permission timing half a cycle after the bus use permission signal by the data transmission period generating means.

[0005]

When the above-mentioned prior art is used, a dead cycle must be provided in order to avoid a bus fight when outputting to an address / data dual-purpose bus. There is a problem that the occupation time increases and the data processing time of the input / output device increases. Further, since a dead cycle is also provided at the time of a retry response, there is a problem that the occupation time of the input / output device is increased, the occupation period of the input / output bus is lengthened, and the load on the input / output bus is increased.

Further, in the technology described in the above publication, although the dead cycle is shortened, there is still a problem that the dead cycle is still required and cannot be solved fundamentally.

An object of the present invention is to solve the above-mentioned problems, eliminate the need for a dead cycle for avoiding bus fights, and improve the use efficiency of an input / output device.

Another object of the present invention is to improve the efficiency of use of an input / output device or an input / output bus at the time of a retry response.

Another object of the present invention is to improve the transfer throughput by preparing in advance for the next use of the I / O bus even when the I / O bus is in use.

[0010]

In order to solve the above-mentioned problems, a bus interface device according to the present invention comprises a first bus for connecting a first processing device for instructing writing, and a bus for writing by the first processing device. A bus interface device that mediates with a second bus that connects the second processing device to be instructed, a first interface unit that mediates some information on the first bus, A second interface means for mediating information of the remaining part of the partial information on a bus, and a transfer path connecting between the first interface means and the second interface means, The first interface means transfers the partial information to the second interface means via one of the second bus and the transfer path, and transfers the partial information to the second interface means. Scan means outputs the first said part of the information received from the interface means and its remaining information sequentially to the second bus.

In another bus interface device of the present invention, a first bus for connecting a first processing device for designating an address by designating an address and data is provided, and a write is designated by the first processing device. A bus interface device that mediates an address for connecting a second processing device to be used and a second bus that also serves as data, wherein address interface means for mediating an address from the first bus; and And data transfer means for transferring an address from the address interface means to the data interface means, the address interface means comprising: a first interface for storing an address from the first processing device. Before the address held by the first address holding circuit. A bus control circuit for controlling the transfer to the data interface means and controlling the output of the address and data from the data interface means to the second bus, wherein the data interface means comprises: , A second address holding circuit for holding an address from the address interface means, and sequentially storing the address held in the second address holding circuit and the data held in the data holding circuit. And a selector for outputting to the second bus, when a write is instructed from the first processing device to the second processing device, the bus control circuit from the first address holding circuit to the An address is added to the second address holding circuit via one of the second bus and the address transfer means. To transfer a scan.

Further, another bus interface device of the present invention includes a first bus connecting a first processing device for designating an address by designating an address and data, and an instruction for writing by the first processing device. A bus interface device that mediates an address for connecting a second processing device to be used and a second bus that also serves as data, wherein address interface means for mediating an address from the first bus; and And data interface means for mediating the data of
A first address holding circuit for holding an address from the first processing device, and controlling a transfer of the address held by the first address holding circuit to the data interface means; A bus control circuit for controlling the output of addresses and data to the second bus, wherein the data interface means holds a data from the first processing device, and holds an address from the address interface means A second address holding circuit, and a selector for sequentially outputting the address held in the second address holding circuit and the data held in the data holding circuit to the second bus, Transfer for transferring an address from the address holding circuit to the second address holding circuit Further comprising a stage, wherein when writing is instructed from the first processing device to the second processing device, if the second bus is not blocked, via the second bus, If the second bus is blocked, the address is transferred via the address transfer means.

In another bus interface device according to the present invention, the address transfer means has a transfer width narrower than that of the second bus, and the address interface means holds the data in the first address holding means. Means for dividing the divided address, and the data interface means further includes means for returning the divided address transferred by the address transfer means to a state before the division.

In another bus interface device according to the present invention, upon receiving a retry response from the second processing device, the bus control circuit receives the address and the data held in the second address holding circuit. The data stored in the holding circuit is controlled to be sequentially output to the second processing device via the second bus.

Further, in another bus interface device according to the present invention, when the bus control circuit receives a retry response from the second processing device, the bus control circuit stores the address and the data held in the second address holding circuit. The data stored in the holding circuit is controlled to be sequentially output to the second processing device via the second bus.

[0016]

Next, a first embodiment of the bus interface device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a bus interface device according to an embodiment of the present invention connects a system bus 110 and an input / output bus 410. The system bus 110 (hereinafter, also referred to as an S bus) is a split bus including an address and control signal bus 111 and a data bus 112, to which the processor 100 is connected.
An input / output bus 410 (hereinafter, also referred to as an IO bus) is a multiplexer bus for both address and data, to which the input / output device 400 is connected.

The S bus interface control unit 220
From the S bus address command buffer 210 to the signal line 21
1. Check the address and command of the S bus input by 1. As a result, if the command is a write transaction, the S bus address command buffer 210,
Address transfer cycle indicator 230, DMA transfer counter 290, data bus interface device 300
Of the S bus data buffer 310,
1, 225, 226 and the data fetch notification line 22
9 to notify.

I / O bus interface control section 270
Is the address transfer cycle indicator 2 by the signal line 232
30, an instruction from the DMA transfer counter 290 via the signal line 296, and an instruction from the address output cycle indicator 240 via the signal line 245. Thereby, the notification to the IO bus address buffer 260 through the signal line 271 and the address transfer cycle notification line 274
To the address / data input / output selector 340 of the data bus interface device 300 via the address output cycle notification line 273 and the data bus interface device 3 via the address division transfer cycle notification line 275.
00 is notified to the write address selector 350.

The DMA transfer counter 290 is a counter that sets the transfer length of a burst DMA transaction from the input / output device 400 as an initial value, and thereafter decrements that value each time transfer in clock units is completed.

The address transfer path 269 is connected to the IO bus 41
It is composed of the number of bits obtained by dividing the bit width of 0 into four. As a result, the address bus interface device 200 transfers the four divided write addresses to the data bus interface device 300 via the address transfer path 269. The address division circuit 265 divides this address.

When the IO bus interface control unit 270 notifies the I / O device 400 of a retry response via the signal line 272, the retry response control unit 250 sends the signal to the address output cycle indicator 240 via the signal line 255. A notice to that effect is given. Here, the retry response is a response indicating that the input / output device 400 is busy and cannot receive the requested transaction.

Address / data input / output selector 340
Responds to an instruction from the address transfer cycle notification line 274 and the address output cycle notification line 273, and outputs the write address buffer 330 or the IO data buffer 32
The value held at 0 is selected and output to the IO bus 410.

The write address selector 350 sequentially transfers the four divided addresses from the address transfer path 269 to the write address buffer 330 in response to an instruction from the address division transfer notification line 275.

Next, the operation of the present invention will be described with reference to FIGS.

From the processor 100 to the S bus 110,
When the address, the command, and the data are output, the address-related bus interface device 200
The above address and command are held in the S bus address command buffer 210. Further, the data bus interface device 300 holds data on the signal line 301 in the S bus data buffer 310.

The S bus interface control unit 220
The address and command held in the bus address command buffer 210 are monitored by a signal line 211, and when it is determined that the request of the S bus 110 is a write transaction to the input / output device 400, the DMA transfer counter 290 is controlled by a signal line 226. Read the count value (J
1). At this time, it instructs the S bus address command buffer 210 to transfer to the IO bus address buffer 260 using the signal line 211.

S bus address command buffer 210
Transfers the address held by the instruction from the S bus interface control unit 220 to the IO bus address buffer 260 via the signal line 212, and holds the address in the IO bus address buffer 260.

The S bus interface control unit 220
Indicates that the cycle is a data fetch cycle by the data fetch notification line 229.
Tell 00.

When the S bus data buffer 310 of the data bus interface device 300 receives a data fetch cycle instruction from the data fetch notification line 229, it uses the signal line 315 to output the IO bus data buffer 32.
0, and the data is held in the IO bus data buffer 320.

Next, when a write transaction is issued to the input / output device 400, the count value (J1) of the DMA transfer counter 290 read from the signal line 226 to the system bus interface control unit 220 is 2 or less. The operation in the case (step 601) will be described with reference to FIGS. 1 to 3 and FIG.

Address transfer cycle indicator 230 checks the value of DMA transfer counter 290 when signal S 225 informs I / O device 400 that the transaction is a write transaction via signal line 225. When the value of the DMA transfer counter 290 is 0
If it is larger than 0, wait until it becomes 0 or less (step 60)
2). If the value of the DMA transfer counter 290 is 0 or less, the address transfer cycle notification line 274 is asserted by the signal line 232 via the IO bus interface control unit 270 (step 603).

The IO bus interface control unit 270
The address transfer cycle notification line 274 is asserted, and an address is transmitted to the IO bus address buffer 260 via the signal 271 so as to output the address to the IO bus 410.

The IO bus address buffer 260 outputs an address to the IO bus 410 according to an instruction from the signal line 271 (L1, step 604).

In the data bus interface device 300, when the address / data input / output selector 340 recognizes that an address transfer cycle is instructed by the address transfer cycle notification line 273, the address is input from the IO bus 410 and the signal line 335 is input. Is stored in the write address buffer 330 (step 605).

When the address output cycle indicator 240 is informed of the address transfer cycle by the signal 231 from the address transfer cycle indicator 230, the address output cycle indicator 240 notifies the IO bus interface controller 270 by the signal 245, and The address output cycle notification line 273 is asserted via the control unit 270 (M1, step 606).

In the data bus interface device 300, when notified of the address output cycle, the address / data input / output selector 340 first selects the address held in the write address buffer 330 and sends it to the IO bus 410. Output (L2, step 60
7) Then, the data held in the IO bus data buffer 320 is selected and output to the IO bus 410 (L3,
Step 608). As a result, a write transaction to the input / output device 400 is executed.

When the retry response control unit 250 receives a retry response from the input / output device 400 via the IO bus interface control unit 270 (step 609), the address output cycle indicator 240 is notified by using the signal line 255. Tell Address output cycle indicator 230
Asserts the address output cycle notification line 273 via the IO bus interface control unit 270 via the signal line 245, and notifies the data bus interface device 300 of the address output cycle (M2, step 606).

In data bus interface device 300, address / data input / output selector 340, upon receiving an address output cycle notification according to an instruction from address output cycle notification line 273, selects an address held in write address buffer 330. IO bus 4
10 (L5, step 607), and then the data held in the IO bus data buffer 320 is transferred to the signal line 32.
5 to the IO bus 410 (L6, step 608). As a result, the address bus interface device 200 is moved from the data bus interface device 300
The address transfer cycle to the I / O device 40 is omitted.
A write transaction to 0 is performed.

Next, when a write transaction is issued to the input / output device 400, the count value (J1) of the DMA transfer counter 290 read from the signal line 226 to the system bus interface control unit 220 is 3 or more. The operation in the case of (Step 601) will be described with reference to FIGS. 1 and 4 to 6.

The DMA transfer counter 290 is connected to the signal line 22
6, when the write transaction is transmitted from the S bus interface control unit 220 to the input / output device 400, the address division transfer cycle notification line 275 is asserted via the IO bus interface control unit 270 by the signal line 296 (step). 611).

The IO bus interface control unit 270
The address division transfer cycle notification line 275 is asserted, and the divided four addresses are transmitted to the IO bus address buffer 260 via the signal line 271 so as to be sequentially output to the address transfer path 269.

The IO bus address buffer 260 sequentially outputs addresses to the address transfer path 269 in accordance with an instruction from the signal line 271 (step 612). On this occasion,
The address division circuit 265 divides an address into four.

In the data bus interface device 300, when the write address selector 350 recognizes that the cycle is an address division transfer cycle according to the instruction of the address division transfer cycle notification line 275, the address transfer path 2
Addresses are sequentially received from 69 and held in the write address buffer 330 via the signal line 355 (step 613).

The address output cycle indicator 240
The count value of the MA transfer counter 290 is monitored by a signal line 295, and when the count value becomes 1 or less (J2, step 614), a notification is sent to the IO bus interface control unit 270 by a signal line 245. In response, IO bus interface control section 270 asserts address output cycle notification line 273 (step 6).
06).

In data bus interface device 300, address / data input / output selector 340 selects an address held in write address buffer 330 when recognizing that it is an address output cycle according to an instruction from address output cycle notifying line 273. Then, the data stored in the IO bus data buffer 320 is selected and output to the IO bus 410 (L6, step 60).
8). As a result, a write transaction to the input / output device 400 is executed.

When the IO bus interface control unit 270 notifies the I / O device 400 of a retry response from the retry response control unit 250, the count value of the DMA transfer counter 290 is set to 2 or less. Similarly to the operation in a certain case, the address-based bus interface device 200
The write transaction to the input / output device 400 is executed by omitting the address division transfer cycle.

In the present embodiment, the number of divisions of the address has been described as four. However, it is needless to say that the number of divisions can take an arbitrary value according to the requirements of the system.

As described above, according to the bus interface device of the first embodiment of the present invention, the address to the input / output device 400 is transferred to the address bus interface device 200.
, The address and data are continuously output from the data bus interface device 300 to avoid a dead cycle. Thus, the input / output device 400 can be used efficiently. In addition, since the address transfer from the address bus interface device 200 to the data bus interface device 300 can be performed by the address transfer path 269, even if the input / output bus 410 is in use, the address can be stored in the data bus interface device in advance. The address can be transferred to the device 300, and the throughput of the address transfer can be increased.

[0050]

As is apparent from the above description, according to the present invention, an address to an input / output device is generated once between an address and data by temporarily transferring the address to a data bus interface device. A dead cycle can be avoided, and the use efficiency of the input / output device can be improved.

In the retry process, the address transferred before the retry is used again, so that the address transfer to the data bus interface device is not performed again, and the efficiency of use of the input / output bus is improved. Can be done.

Further, by providing the dedicated path for address transfer, the address can be transferred to the data bus interface device in advance even when the input / output bus is in use, thereby increasing the address transfer throughput.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a bus interface device according to the present invention.

FIG. 2 is a time chart illustrating an operation when a DMA counter value of the bus interface device according to one embodiment of the present invention is 2 or less.

FIG. 3 is a time chart showing details of an operation when a DMA counter value of the bus interface device according to one embodiment of the present invention is 2 or less.

FIG. 4 is a time chart showing an operation when the DMA counter value of the bus interface device according to the embodiment of the present invention is 3 or more.

FIG. 5 is a time chart showing details of the operation when the DMA counter value of the bus interface device according to the embodiment of the present invention is 3 or more.

FIG. 6 is a flowchart illustrating a flow of an operation of the bus interface device according to the embodiment of the present invention.

FIG. 7 is a time chart illustrating an operation of the bus interface device according to the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 processor 110 system bus 200 address bus interface device 210 system bus address command buffer 220 system bus interface control unit 230 address transfer cycle indicator 240 address output cycle indicator 250 retry response control unit 260 input / output bus address buffer 265 address division circuit 269 Address transfer path 270 Input / output bus interface controller 280 DMA address buffer 290 DMA transfer counter 300 Data bus interface device 310 System bus data buffer 320 Input / output bus data buffer 330 Write address buffer 340 Address data input / output selector 350 Write address selector 360 DMA data buffer 400 I / O device 4 0 input and output bus

Claims (6)

(57) [Claims] An intermediary is provided between a first bus connecting a first processing device instructing writing and a second bus connecting a second processing device instructing writing by the first processing device. A first interface means for mediating a part of information on the first bus, and a second interface for mediating information of the remaining part of the partial information on the first bus. Interface means, and a transfer path connecting between the first interface means and the second interface means, the first interface means, the part of the information and the second bus and Transferring to the second interface means via one of the transfer paths, the second interface means, the partial information received from the first interface means Bus interface unit and outputs the rest of the information sequentially to the second bus. 2. A first bus for connecting a first processing device that instructs writing by designating an address and data, and a second processing device for which writing is instructed by the first processing device. In a bus interface device that mediates an address and a second bus that also serves as data, an address interface unit that mediates an address from the first bus, a data interface unit that mediates data from the first bus, Address transfer means for transferring an address from the address interface means to the data interface means, the address interface means comprising: a first address holding circuit for holding an address from the first processing device; Controlling the transfer of the address held in the address holding circuit to the data interface means A bus control circuit for controlling an output of an address and data from the data interface unit to the second bus; a data holding circuit for holding data from the first processing device; A second address holding circuit for holding an address from the interface means, and a selector for sequentially outputting the address held in the second address holding circuit and the data held in the data holding circuit to the second bus When writing is instructed from the first processing device to the second processing device, the bus control circuit sends the second address holding circuit from the first address holding circuit to the second address holding circuit. A bus interface for transferring an address via one of two buses and the address transfer means. Esu apparatus. 3. A first bus for connecting a first processing device that instructs writing by designating an address and data, and a second processing device for which writing is instructed by the first processing device. In a bus interface device that mediates an address and a second bus that also serves as data, an address interface unit that mediates an address from the first bus, and a data interface unit that mediates data from the first bus The address interface means controls a first address holding circuit for holding an address from the first processing device, and a transfer of the address held in the first address holding circuit to the data interface means. Bus control for controlling the output of addresses and data from the data interface means to the second bus A data holding means for holding data from the first processing device, a second address holding circuit for holding an address from the address interface means, and a second address. A selector for sequentially outputting the address held in the holding circuit and the data held in the data holding circuit to the second bus, and an address from the first address holding circuit to the second address holding circuit. Further comprising an address transfer means for transferring the second processing device, if the first processing device is instructed to write to the second processing device, if the second bus is not blocked, Transferring an address via a bus, if the second bus is blocked, via the address transfer means. Face equipment. 4. The address transfer means has a transfer width narrower than the second bus, and the address interface means further comprises means for dividing an address held by the first address holding means. 4. The data interface unit according to claim 3, further comprising a unit for returning the divided address transferred by the address transfer unit to a state before the division.
A bus interface device as described. 5. The bus control circuit, upon receiving a retry response from the second processing device, sequentially stores the address held in the second address holding circuit and the data held in the data holding circuit. The bus interface device according to claim 2 or 3, wherein the bus interface device controls output to the second processing device via a second bus. 6. When the bus control circuit receives a retry response from the second processing device, the bus control circuit sequentially stores the address held in the second address holding circuit and the data held in the data holding circuit. 5. The bus interface device according to claim 4, wherein the bus interface device controls output to the second processing device via a second bus.