JP2821613B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2821613B2 JP2821613B2 JP1062581A JP6258189A JP2821613B2 JP 2821613 B2 JP2821613 B2 JP 2821613B2 JP 1062581 A JP1062581 A JP 1062581A JP 6258189 A JP6258189 A JP 6258189A JP 2821613 B2 JP2821613 B2 JP 2821613B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- manufacturing
- semiconductor
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 238000000034 method Methods 0.000 title claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 239000010936 titanium Substances 0.000 description 27
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 24
- 229910052719 titanium Inorganic materials 0.000 description 24
- 238000005530 etching Methods 0.000 description 13
- 239000000758 substrate Substances 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 229910021341 titanium silicide Inorganic materials 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000002542 deteriorative effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- -1 ammonia peroxide Chemical class 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】 以下の順序に従って本発明を説明する。DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.
A.産業上の利用分野 B.発明の概要 C.従来技術［第３図］ D.発明が解決しようとする問題点 E.問題点を解決するための手段 F.作用 G.実施例［第１図、第２図］ H.発明の効果 （A.産業上の利用分野） 本発明は半導体装置の製造方法、特に表面に形成した
金属膜を部分的にシリサイド化し、その後該金属膜の未
反応部分を除去する半導体装置の製造方法に関する。A. Industrial application fields B. Summary of the invention C. Prior art [Fig. 3] D. Problems to be solved by the invention E. Means to solve the problems F. Function G. Example [No. FIGS. 1 and 2] H. Effects of the Invention (A. Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, in particular, a method of partially silicidizing a metal film formed on a surface, and then forming the metal film on the surface. The present invention relates to a method for manufacturing a semiconductor device for removing a reaction portion.
（B.発明の概要） 本発明は、上記の半導体装置の製造方法において、 金属膜の部分的シリサイド化後、未反応部分の除去前
に金属膜の表面が劣化することを防止するため、 部分的シリサイド化と未反応部分の除去を連続的に行
うようにしたものである。(B. Summary of the Invention) The present invention provides a method for manufacturing a semiconductor device according to the above, further comprising: preventing partial deterioration of the surface of the metal film after partial silicidation of the metal film and before removing unreacted portions. In this method, the silicidation and the removal of the unreacted portion are continuously performed.
（C.従来技術）［第３図］ LSIの高集積化のための半導体素子が微細化の一途を
辿っているが、それに伴ってソース、ドレイン等半導体
領域あるいは半導体層のシート抵抗値の低減化、コンタ
クト抵抗の低減化を図る必要性が高まっている。(C. Conventional technology) [Fig. 3] Semiconductor devices for high integration of LSIs are continually miniaturized, and the sheet resistance of semiconductor regions or semiconductor layers such as sources and drains is reduced accordingly. There is an increasing need to reduce the contact resistance.
そのため、半導体領域あるいは半導体層表面の絶縁膜
にコンタクト孔を形成し、次いで配線金属を被着し、そ
の後その配線金属をパターニングし、しかる後半導体と
金属との電気的結合を良好にするための熱処理を行うと
いう従来の技術に代わる新しい技術の出現、確立が望ま
れている。とういのは、このような従来の技術では通常
配線金属として用いられる１〜２％のシリコンを含有し
たアルミニウム中のシリコンが上記熱処理によりコンタ
クト部に析出し、良好なオーミックコンタクトがとれな
くなるという問題があるからである。Therefore, a contact hole is formed in a semiconductor region or an insulating film on the surface of a semiconductor layer, a wiring metal is applied, and then the wiring metal is patterned, and thereafter, the electrical connection between the semiconductor and the metal is improved. The emergence and establishment of a new technology that replaces the conventional technology of performing heat treatment is desired. The problem with this conventional technique is that silicon in aluminum containing 1 to 2% of silicon, which is usually used as a wiring metal, is deposited on the contact portion by the above-described heat treatment, and a good ohmic contact cannot be obtained. Because there is.
そして、新しい技術の開発が着実に進行し、その成果
が例えば特開昭63−12154号公報によって公表されてい
る。そして、かかる新技術の中で特に注目を浴びている
のはSALICIDE（Selfalingend−Silicide）技術である。The development of new technologies has been steadily progressing, and the results have been disclosed, for example, in Japanese Patent Application Laid-Open No. 63-12154. Among these new technologies, the SALICIDE (Selfalingend-Silicide) technology has received particular attention.
第３図（Ａ）乃至（Ｃ）はSALICIDE技術による半導体
装置の製造方法を工程順に示す断面図である。3A to 3C are cross-sectional views showing a method for manufacturing a semiconductor device by the SALICIDE technology in the order of steps.
（Ａ）半導体基板１の表面部を選択酸化してフィールド
絶縁膜２を形成し、半導体基板１のフィールド絶縁膜２
が形成されていない部分の表面にゲート絶縁膜３を形成
し、該ゲート絶縁膜３上にシリコンゲート電極４を形成
し、該ゲート電極４をマスクとして半導体基板１の表面
部に不純物を軽くイオン打込みし、該ゲート電極４の側
面に絶縁物からなるサイドウォール５を形成し、該サイ
ドォール及びゲート電極４をマスクとして半導体基板１
の表面部に不純物をイオン打込みすることによりソース
６、ドレイン７を形成し、その後、スパッタリング装置
によりチタン膜８を全面的に形成する。第３図（Ａ）は
チタン膜８形成後の状態を示す。(A) The field insulating film 2 is formed by selectively oxidizing the surface portion of the semiconductor substrate 1, and the field insulating film 2 of the semiconductor substrate 1 is formed.
A gate insulating film 3 is formed on the surface of the portion where no is formed, a silicon gate electrode 4 is formed on the gate insulating film 3, and impurities are lightly ionized on the surface of the semiconductor substrate 1 using the gate electrode 4 as a mask. Implantation is performed to form a sidewall 5 made of an insulator on the side surface of the gate electrode 4, and the semiconductor substrate 1 is formed using the sidewall and the gate electrode 4 as a mask.
The source 6 and the drain 7 are formed by ion-implanting an impurity into the surface of the substrate, and then a titanium film 8 is entirely formed by a sputtering apparatus. FIG. 3A shows a state after the titanium film 8 is formed.
（Ｂ）次に、IRアニール装置により800℃の温度で加熱
処理すると、第３図（Ａ）に示すようにチタン膜８の半
導体基板１と接する部分がシリサイド化し、チタンシリ
サイド膜8aとなる。8bはチタン膜８のシリサイド化しな
かった部分、即ち未反応部分を示す。(B) Next, when a heat treatment is performed at a temperature of 800 ° C. by an IR annealing apparatus, a portion of the titanium film 8 that is in contact with the semiconductor substrate 1 is silicided as shown in FIG. 3 (A) to form a titanium silicide film 8a. Reference numeral 8b denotes a portion of the titanium film 8 that has not been silicided, that is, an unreacted portion.
（Ｃ）次に、上記チタン膜８の未反応部分8bをアンモニ
ア過水等を用いて同図（Ｃ）に示すようにエッチング除
去する。(C) Next, the unreacted portions 8b of the titanium film 8 are removed by etching using ammonia peroxide as shown in FIG.
このような半導体装置の製造方法によれば、フォトリ
ソグラフィ技術を用いなくてもソース６、ドレイン７上
に選択的にチタンシリサイド膜8aを形成することがで
き、しかもチタンシリサイド膜8aは耐熱性に優れ且つシ
リサイド中で最も低抵抗であるので、ソース、ドレイン
の抵抗、コンタクト抵抗の低減という要請に応えること
ができ得る。その点で優れているといえる。According to such a method of manufacturing a semiconductor device, the titanium silicide film 8a can be selectively formed on the source 6 and the drain 7 without using the photolithography technique, and the titanium silicide film 8a has heat resistance. Since it is excellent and has the lowest resistance in silicide, it can meet the demand for reduction of source and drain resistance and contact resistance. In that respect it can be said that it is excellent.
（D.発明が解決しようとする問題点） ところで、第３図に示した技術には、金属膜の選択的
シリサイド化の後未反応部分をエッチングにより除去す
るまでの間にチタンシリサイド膜の膜質が低下するとい
う問題があった。というのはその間に半導体ウエハが大
気に晒されるからである。(D. Problems to be Solved by the Invention) By the way, the technique shown in FIG. 3 includes the film quality of the titanium silicide film until the unreacted portion is removed by etching after the selective silicidation of the metal film. However, there was a problem that was reduced. This is because the semiconductor wafer is exposed to the air during that time.
本発明はこのような問題点を解決すべく為されたもの
であり、金属膜の部分的シリサイド化後、未反応部分の
除去前に金属膜の表面が劣化することを防止することを
目的とする。The present invention has been made to solve such a problem, and has as its object to prevent the surface of a metal film from deteriorating after partial silicidation of the metal film and before removal of an unreacted portion. I do.
（E.問題点を解決するための手段） 本発明半導体装置の製造方法は上記問題点を解決する
ため、金属膜の形成と、金属膜の選択的シリサイド化
と、未反応部分の除去を被処理半導体装置を一つの装置
内に止め外に晒すことなく連続的に行うことを特徴とす
る。(E. Means for Solving the Problems) In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention requires forming a metal film, selectively siliciding the metal film, and removing an unreacted portion. It is characterized in that processing semiconductor devices are continuously carried out without being stopped in one device and exposed to the outside.
（F.作用） 本発明半導体装置の製造方法によれば、金属膜の形
成、金属膜の選択的シリサイド化、及びその後の未反応
部分のエッチングを連続的に行うのでその間半導体装置
を大気に晒されない。従って、金属膜のシリサイド化部
分の膜質の低下を防止することができる。(F. Function) According to the method for manufacturing a semiconductor device of the present invention, the formation of the metal film, the selective silicidation of the metal film, and the subsequent etching of the unreacted portion are performed continuously, so that the semiconductor device is exposed to the air during that time. Not done. Therefore, it is possible to prevent the film quality of the silicided portion of the metal film from deteriorating.
（G.実施例）［第１図、第２図］ 以下、本発明半導体装置の製造方法を図示実施例に従
って詳細に説明する。(G. Embodiment) [FIGS. 1 and 2] Hereinafter, a method for manufacturing a semiconductor device of the present invention will be described in detail with reference to illustrated embodiments.
第１図及び第２図（Ａ）乃至（Ｃ）は本発明半導体装
置の製造方法の一つの実施例を説明するためのもので、
第１図は製造に用いる装置の模式的断面図、第２図
（Ａ）乃至（Ｃ）は第１図に示した装置内で行われる半
導体装置の製造方法を工程順に示す半導体装置の断面図
である。FIGS. 1 and 2 (A) to 2 (C) are for explaining one embodiment of the method of manufacturing a semiconductor device of the present invention.
FIG. 1 is a schematic cross-sectional view of a device used for manufacturing, and FIGS. 2A to 2C are cross-sectional views of a semiconductor device showing a method of manufacturing a semiconductor device performed in the device shown in FIG. It is.
第１図において、９は半導体ウエハ、10はチャンバー
で、該チャンバー１内においてチタン膜の形成、選択的
シリサイド化及び未反応部分のエッチングが行われる。
11はチャンバー10のウエハ導入口、12はチャンバー10外
部から導入された半導体ウエハ９を支持してチャンバー
10内の所定位置まで運ぶ導入アーム、13はチャンバー10
の側壁に形成された窓で、チャンバー10外部のエキシマ
レーザ14からのレーザ光15を透過させる。In FIG. 1, reference numeral 9 denotes a semiconductor wafer, and reference numeral 10 denotes a chamber in which formation of a titanium film, selective silicidation, and etching of an unreacted portion are performed.
Reference numeral 11 denotes a wafer inlet of the chamber 10, and 12 denotes a chamber for supporting the semiconductor wafer 9 introduced from outside the chamber 10.
Introductory arm which carries it to a predetermined position in 10, 13 is chamber 10
The laser beam 15 from the excimer laser 14 outside the chamber 10 is transmitted through a window formed on the side wall of the chamber 10.
16、17は外部からチャンバー10内へガスを導くガス管
である。Reference numerals 16 and 17 denote gas pipes for guiding gas into the chamber 10 from the outside.
次に、第１図に示すチャンバー10内での製造を第２図
（Ａ）乃至（Ｃ）によって工程順に説明する。Next, manufacturing in the chamber 10 shown in FIG. 1 will be described in the order of steps with reference to FIGS. 2 (A) to 2 (C).
（Ａ）ソース６、ドレイン７の形成を終えた半導体ウエ
ハ９をチャンバー10内に入れた後、例えばTi（C5H5）２
ガスをガス管例えば17を通じてチャンバー10内に供給す
る。それと共にガスTi（C5H5）２を励起させる波長のレ
ーザ光（具体的には240mnかそれ以下の波長の光）をエ
キシマレーザ17から発射させてガス励起を行う。(A) After the semiconductor wafer 9 on which the source 6 and the drain 7 have been formed is put into the chamber 10, for example, Ti (C 5 H 5 ) 2
A gas is supplied into the chamber 10 through a gas pipe, for example, 17. At the same time, laser light (specifically, light having a wavelength of 240 mn or less) that excites the gas Ti (C 5 H 5 ) 2 is emitted from the excimer laser 17 to excite the gas.
すると、第２図（Ａ）に示すように基板１表面上にチ
タン膜８が全面的に形成される。尚、ソース６、ドレイ
ン７の形成までのプロセスは第３図に示した製造方法の
（Ａ）の工程のところで説明済であるのでその説明は省
略する。Then, a titanium film 8 is entirely formed on the surface of the substrate 1 as shown in FIG. 2 (A). The process up to the formation of the source 6 and the drain 7 has already been described in the step (A) of the manufacturing method shown in FIG. 3, so that the description is omitted.
（Ｂ）上述したようにしてチタン膜８が形成されるが、
それと共に励起用エシシマレーザ光により半導体基板１
の表面部が加熱され、その熱によりチタン膜８の半導体
基板１の露出部（ソース６、ドレイン７と接する部分）
がシリサイド化してチタンシリサイド膜8aとなる。8bは
チタン膜８のシリサイド化しない部分、即ち未反応部分
である。(B) The titanium film 8 is formed as described above.
At the same time, the semiconductor substrate 1 is excited by an excitation Esima laser beam.
Is heated, and the heat causes the exposed portion of the titanium film 8 on the semiconductor substrate 1 (the portion in contact with the source 6 and the drain 7).
Is silicided to form a titanium silicide film 8a. Reference numeral 8b denotes a portion of the titanium film 8 that is not silicided, that is, an unreacted portion.
尚、この場合、レーザ光により加熱されるのは半導体
基板の表面部だけなので下層への熱的悪影響は全くな
い。In this case, since only the surface of the semiconductor substrate is heated by the laser beam, there is no thermal adverse effect on the lower layer.
このチタン膜の成長［第２図（Ａ）］とシリサイド化
［同図（Ｂ）］とは図面では恰も別工程であるかのよう
に示したが本実施例では略同時に進行する。The growth of the titanium film [FIG. 2 (A)] and the silicidation [FIG. 2 (B)] are shown in the drawings as if they were separate processes, but in the present embodiment, they proceed almost simultaneously.
（Ｃ）チタンシリサイド膜ａの膜厚が所定の厚さになっ
たら上記工程に引き続いて、即ち半導体ウエハ９を装置
外部へ出して大気に晒すことなく、チタン膜８の未反応
部分8bの光エッチングを行う。具体的には、上記レーザ
光15の照射は継続し、ガスTi（C5H5）２は排気し、そし
てチタン膜８（の未反応部分8b）に対するエッチングガ
スであるCHF3あるいはBCl3等をガス管例えば16からチャ
ンバー10内へ供給する。すると、このエッチング用ガス
はレーザ光15によって励起されて第２図（Ｃ）に示す様
にチタン膜８の未反応部分8bを除去する。即ち、光エッ
チングをする。(C) When the thickness of the titanium silicide film a reaches a predetermined thickness, the above process is continued, that is, without exposing the semiconductor wafer 9 to the outside of the apparatus and exposing the unreacted portion 8b of the titanium film 8 to the air. Perform etching. More specifically, the irradiation with the laser beam 15 is continued, the gas Ti (C 5 H 5 ) 2 is exhausted, and CHF 3 or BCl 3 which is an etching gas for the (unreacted portion 8b of) the titanium film 8 is used. Is supplied into the chamber 10 from a gas pipe, for example, 16. Then, the etching gas is excited by the laser beam 15 to remove the unreacted portion 8b of the titanium film 8 as shown in FIG. 2 (C). That is, light etching is performed.
本半導体装置の製造方法によれば、チタン膜の形成
と、選択的シリサイド化と、未反応部分のエッチングと
を同じチャンバー10内で連続的に行い、その間装置外部
に出して大気に晒すことはないので、チタン膜の表面が
酸化したり、チタンシリサイド膜の膜質が劣化したりす
る虞れはなく、コンタクト部の低抵抗化を容易に為し得
る。According to the manufacturing method of the present semiconductor device, the formation of the titanium film, the selective silicidation, and the etching of the unreacted portion are continuously performed in the same chamber 10, and during that time, it is possible to take out the device and expose it to the atmosphere. Therefore, there is no fear that the surface of the titanium film is oxidized or the quality of the titanium silicide film is degraded, and the resistance of the contact portion can be easily reduced.
即ち、従来のようにチタン膜８をスパッタリング装置
においてスパッタリングにより形成し、IRアニールによ
りチタン膜９のソース６、ドレイン７と接する部分をシ
リサイド化し、その後チタン膜８の未反応部分8bをアン
モニア過水等を用いてウエットエッチングにより除去し
た場合は、先ずチタン膜８形成後IRアニール前に半導体
ウエハをスパッタリグ装置から出すのでそのとき大気に
晒される。その結果、シリサイド化前のチタン膜の表面
が酸化され、表面の平坦性が損なわれるし、低抵抗化が
若干阻まれる。また、IRアニールによるチタン膜の選択
的シリサイド化後未反応部分のエッチング前にも大気に
晒されるのでチタンシリシド膜の膜質低下が生じるが、
本半導体装置の製造方法によれば、半導体ウエハがチタ
ン膜の形成から選択的シリサイド化を経て未反応部分エ
ッチングを終えるまで装置内に留まり大気には晒されな
いので従来の問題点を回避することができるのである。That is, the titanium film 8 is formed by sputtering in a sputtering apparatus as in the prior art, the portion of the titanium film 9 in contact with the source 6 and the drain 7 is silicified by IR annealing, and then the unreacted portion 8b of the titanium film 8 is treated with ammonia peroxide. In the case where the semiconductor wafer is removed by wet etching using the method described above, the semiconductor wafer is first taken out of the sputter rig after the formation of the titanium film 8 and before the IR annealing. As a result, the surface of the titanium film before silicidation is oxidized, the flatness of the surface is impaired, and the lowering of the resistance is somewhat hindered. Also, after the selective silicidation of the titanium film by IR annealing, it is exposed to the atmosphere even before the etching of the unreacted part, so that the quality of the titanium silicide film deteriorates.
According to the method of manufacturing a semiconductor device of the present invention, the conventional problem can be avoided because the semiconductor wafer stays in the device and is not exposed to the atmosphere until the unreacted partial etching is completed through the formation of the titanium film and the selective silicidation, thereby avoiding the conventional problems. You can.
また、本半導体装置の製造方法によればチタン膜の形
成から未反応部分のエッチングを同一装置内において行
うのでスループットが著しく向上し、製造コストの低減
を図ることができる。特に、装置内で同時に処理する半
導体ウエハの枚数を多くする程製造コストの低減を図る
ことができる。Further, according to the method of manufacturing a semiconductor device, since the etching of the unreacted portion is performed in the same device from the formation of the titanium film, the throughput is significantly improved, and the manufacturing cost can be reduced. In particular, as the number of semiconductor wafers simultaneously processed in the apparatus increases, the manufacturing cost can be reduced.
（H.発明の効果） 以上に述べたように、本発明半導体装置の製造方法
は、部分的に半導体が露出する面上への金属膜の形成
と、該金属膜の部分的シリサイド化と、該金属膜の未反
応部分の除去を、被処理半導体装置を一つの装置内に止
め外に晒すことなく連続的に行うことを特徴とするもの
である。(H. Effects of the Invention) As described above, the method of manufacturing a semiconductor device of the present invention includes forming a metal film on a surface where a semiconductor is partially exposed, partially silicidizing the metal film, The removal of the unreacted portion of the metal film is performed continuously without stopping the semiconductor device to be processed in one device and exposing the semiconductor device to the outside.
従って、本発明半導体装置の製造方法によれば、金属
膜の形成、金属膜の選択的シリサイド化、及びその後の
未反応部分のエッチングを連続的に行うのでその間半導
体装置を大気に晒さない。従って、金属膜のシリサイド
化部分の膜質の低下を防止することができる。Therefore, according to the method for manufacturing a semiconductor device of the present invention, the formation of the metal film, the selective silicidation of the metal film, and the subsequent etching of the unreacted portion are continuously performed, so that the semiconductor device is not exposed to the air during that time. Therefore, it is possible to prevent the film quality of the silicided portion of the metal film from deteriorating.
第１図及び第２図は本発明半導体装置の製造方法の一つ
の実施例を説明するためのもので、第１図は製造に用い
る装置の模式的断面図、第２図（Ａ）乃至（Ｃ）は製造
方法を工程順に示す断面図、第３図（Ａ）乃至（Ｃ）は
従来例を工程順に示す断面図である。 符号の説明 １、６、７……半導体、８……金属膜。1 and 2 are views for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention. FIG. 1 is a schematic cross-sectional view of an apparatus used for manufacturing the semiconductor device, and FIGS. 3C is a cross-sectional view showing the manufacturing method in the order of steps, and FIGS. 3A to 3C are cross-sectional views showing the conventional example in the order of steps. DESCRIPTION OF SYMBOLS 1, 6, 7 ... semiconductor, 8 ... metal film.
Claims (1)
の形成と、該金属膜の部分的シリサイド化と、該金属膜
の未反応部分の除去を、被処理半導体装置を一つの装置
内に止め外に晒すことなく連続的に行う ことを特徴とする半導体装置の製造方法An object of the present invention is to form a metal film on a surface where a semiconductor is partially exposed, to partially silicide the metal film, and to remove an unreacted portion of the metal film. A method for manufacturing a semiconductor device, wherein the method is performed continuously without exposing the inside of the device to the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1062581A JP2821613B2 (en) | 1989-03-15 | 1989-03-15 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1062581A JP2821613B2 (en) | 1989-03-15 | 1989-03-15 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02241033A JPH02241033A (en) | 1990-09-25 |
| JP2821613B2 true JP2821613B2 (en) | 1998-11-05 |
Family
ID=13204431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1062581A Expired - Fee Related JP2821613B2 (en) | 1989-03-15 | 1989-03-15 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2821613B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100690996B1 (en) * | 2000-12-28 | 2007-03-08 | 주식회사 하이닉스반도체 | Method of manufacturing gate of semiconductor device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3003608B2 (en) * | 1997-01-23 | 2000-01-31 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP3129232B2 (en) * | 1997-05-08 | 2001-01-29 | 日本電気株式会社 | Method for manufacturing semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01109766A (en) * | 1987-10-22 | 1989-04-26 | Nec Corp | Manufacture of semiconductor device |
-
1989
- 1989-03-15 JP JP1062581A patent/JP2821613B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100690996B1 (en) * | 2000-12-28 | 2007-03-08 | 주식회사 하이닉스반도체 | Method of manufacturing gate of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02241033A (en) | 1990-09-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5948702A (en) | Selective removal of TixNy | |
| KR100302894B1 (en) | Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture | |
| US6475893B2 (en) | Method for improved fabrication of salicide structures | |
| JPH0581664B2 (en) | ||
| JP2002314076A (en) | Method of forming metal gate | |
| JPH10173179A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JP3104689B2 (en) | Method for forming silicide layer and method for manufacturing semiconductor device | |
| JP3009979B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2821613B2 (en) | Method for manufacturing semiconductor device | |
| JP3163996B2 (en) | Method for manufacturing semiconductor device | |
| JP2638573B2 (en) | Method for manufacturing semiconductor device | |
| KR100215528B1 (en) | Method of manufacturing salicide structure semiconductor device | |
| JP4095760B2 (en) | Manufacturing method of semiconductor device | |
| KR100628225B1 (en) | Manufacturing method of semiconductor device | |
| KR100462667B1 (en) | Semiconductor device and method of manufacturing the same | |
| US20070032073A1 (en) | Method of substrate processing and apparatus for substrate processing | |
| JP2003077901A (en) | Method for manufacturing semiconductor device | |
| JP2004119754A (en) | Wiring, method of manufacturing wiring, semiconductor device and method of manufacturing the same | |
| JPH06124959A (en) | Method for manufacturing semiconductor device | |
| KR100291180B1 (en) | Method for forming gate-electrode in semiconductor device | |
| JPH0669168A (en) | Manufacture of semiconductor device | |
| KR100779394B1 (en) | Semiconductor device manufacturing method | |
| JP2002093744A (en) | Method for manufacturing semiconductor device | |
| JPH11135789A (en) | Semiconductor device and manufacturing method thereof | |
| KR20060071941A (en) | Gate Forming Method of Semiconductor Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |