JP2837609B2 - Power control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply control method for a portable electronic device having a battery charge / discharge function.

In recent years, portable electronic devices such as notebook personal computers (personal computers), word processors, and the like, in which battery charge / discharge control is controlled by a one-chip microcomputer, have been widely used. Such an electronic device includes a rechargeable secondary battery as a battery. When the battery is discharged by operating the electronic device using the battery as a power source, charging control can be performed when an AC power source is connected. Since the battery of such an electronic device deteriorates due to overcharging or affects peripheral circuits due to heat generation, it is desired to accurately control the charge and discharge of the battery.

[0003]

2. Description of the Related Art FIG. 20 is a diagram showing a configuration example of battery charge / discharge control of an electronic device. When using the power supply of an electronic device such as a notebook personal computer by connecting it with an AC power supply,
In the AC adapter 90, the input AC voltage (for example, AC1
00V) is converted into a DC (direct current) voltage, input to a DC-DC converter 91, and converted into a voltage required by a system circuit (not shown) of the electronic device and output. When the electronic device is carried and used, a battery 92 such as a nickel-cadmium battery or a nickel-metal hydride battery is discharged to generate a power supply voltage from the DC-DC converter 91.

When discharging the battery 92, a discharge switch SW2 is turned on via a drive circuit 93 under the control of a control circuit 95 constituted by a one-chip microcomputer (microcomputer) or the like. Here, the driving circuit 93
Is driven by a high withstand voltage element whose battery voltage that is turned on and off by the switch SW2 is higher than the voltage handled by the control circuit 95.
Because it cannot be controlled directly from the

When the electronic device is operating using the output of the AC adapter 90 as a power supply, the battery 92 can be charged. This charging operation is performed by the
-A change in the output of the DC converter 91 is detected, the battery is fully charged, and the drive circuit 93 is controlled to turn off the charging switch SW1.

A control circuit 95 for a one-chip microcomputer is also provided.
Must operate by detecting the power supply from the DC-DC converter 91 before the system circuit operates. Therefore, the reset circuit 96 for resetting the system circuit so that the system of the electronic device does not operate at the time of power supply is provided. Is provided.

[0007]

As described above, conventionally, when the power supply of an electronic device such as a notebook personal computer is controlled by a one-chip microcomputer, many analog circuit components are required externally. As the number of points increases, the mounting area of the substrate on which they are mounted increases, and the weight also increases. Therefore, there is a problem that it is difficult to reduce the size and weight of the electronic device and the cost increases.

Further, if analog parts are scattered, a malfunction may occur due to clock noise on signals between the analog parts. Furthermore, when a plurality of analog components (for example, operational amplifiers) are used as individual components, there is a problem that the operation accuracy of the device is deteriorated because the accuracy varies among the analog components.

In addition, when the battery is discharged under the control of the control circuit to operate the system circuit of the electronic device, if the battery voltage drops too much, there is a problem that overdischarge occurs and the battery is deteriorated. Further, if the microcomputer of the control circuit runs away during the charging operation of the battery, the battery may be overcharged and the battery may be ignited due to overheating.

A first object of the present invention is to provide a power supply control system capable of reducing the size of a peripheral circuit for power supply control and improving accuracy in an electronic device such as a notebook personal computer having a battery charge / discharge control function. And the second
A second object of the present invention is to provide a power supply control method capable of preventing a battery from being over-discharged or over-charged by a control circuit.
The purpose of.

[0011]

FIG. 1 is a block diagram showing a first principle of the present invention, and FIG. 2 is a block diagram showing a second principle of the present invention. 1 and 2, reference numeral 1 denotes a power supply controller, 2 denotes a peripheral circuit for one-chip power supply control, 3 denotes a battery, 4 denotes a DC-DC converter, and 5a denotes charging for switching on / off a charging operation of the battery. A switch (represented by a charge SW); 5b, a discharge switch (represented by a discharge SW) for switching on / off of a discharge operation from the battery 3; 6, a control data line; 7, a signal line for clearing a watchdog timer; The reset line 9 is a system voltage detector for detecting a system voltage of an electronic device (not shown).

Reference numeral 10 in the power supply controller 1 denotes a processing unit for performing processing according to a program, and reference numeral 11 denotes a transfer control unit for setting control data to each unit in the peripheral circuit 2 and receiving a signal detected by the peripheral circuit 2. , 12 are reset units for resetting each unit such as the processing unit 10 by a signal input from the outside.

The peripheral circuit 2 is mainly composed of an analog circuit which operates by an analog signal with an external device to be controlled, and transmits and receives a control signal and detection data to and from the power supply controller 1 via a transfer control unit 20. Done. In the first principle configuration of FIG. 1, 2a to 2e are provided as a circuit using an analog signal with the outside of the peripheral circuit 2, and 2a is a DC for detecting the voltage of the DC-DC converter.
A voltage detection unit, 2b is a DC control unit that generates a control output of the DC-DC converter, 2c is a charge switch (SW) control unit that controls the charge SW 5a, 2d is a discharge switch (SW) control unit that controls the discharge SW 5b, 2e is a battery voltage detecting unit. In the second principle configuration of FIG.
DC voltage detector 2a related to control of DC converter 4
And the DC control unit 2b is not provided.

Also, 20 to 22 in the peripheral circuit 2 of FIG.
Is a configuration for transmitting and receiving signals to and from the power supply controller 1, 20 is a transfer controller for exchanging data with the power supply controller 1, 21 is a watchdog timer (WDT), and 22 is a power supply. Control controller 1
And a reset output section for internally generating a reset signal. The peripheral circuit 2 of FIG. 2 is provided with a transfer control unit 200 to which charge / discharge control data is input from the power supply controller 1 via the control data line 6. A watchdog timer (WDT) 210 is provided in the same manner as in FIG. The reset output unit 220 is also driven by detection of a drop voltage from the system voltage detection unit 9 or detection of a voltage higher than a certain level.

According to the present invention, the peripheral circuit for power supply control of an electronic device such as a notebook personal computer is integrated into one chip and controlled by a power supply controller, thereby saving space, cost and accuracy of the peripheral circuit for power supply control. It will improve. In addition, the power supply controller is reset when the power is turned on or when an abnormality in the voltage level is detected, and a watchdog timer is provided externally to reset the power supply controller when an abnormality occurs. This is to prevent runaway due to.

[0016]

In the first principle configuration shown in FIG. 1, whether the DC-DC converter 4 is supplied with DC power from the AC adapter,
Alternatively, when the voltage of the battery 3 is input when the discharge switch 5b is driven ON, the DC-DC conversion is performed, and the DC output is supplied to a system circuit (not shown) of the electronic device. The discharge switch 5b is connected to the power controller 1
Is transmitted from the transfer control unit 11 to the transfer control unit 20 of the peripheral circuit 2 via the control data line 6, and is supplied to the discharge switch control unit 2d from there to be turned on. DC-D
The output voltage of the C converter 4 is detected by the DC voltage detector 2a, and the detected value is transmitted from the peripheral circuit 2 to the power supply controller 1
Is sent through the control data line 6 to the DC-D
The control signal to the C converter is sent from the power supply controller 1 to the peripheral circuit 2 through the reverse path,
b to the DC-DC converter 4 to perform the control operation.

For charging the battery 3, when a control signal for turning on the charge switch 5a is sent from the power supply controller 1, the charge switch control section 2c of the peripheral circuit 2 operates to drive the charge switch 5a on. When the charging is performed, the charging voltage of the battery 3 is detected by the battery voltage detecting unit 2 e of the peripheral circuit 2, and is transmitted from the transfer control unit 20 to the transfer control unit 11 of the power supply controller 1. Processing unit 10
When a change in charging voltage is identified and full charge is detected, a control signal is sent to the peripheral circuit 2, and the charge switch control unit 2c of the peripheral circuit 2 is driven to turn off the charging SW 5a.

The watchdog timer 21 is started by a pulse signal sent from the power supply controller 1 to the signal line 7, and the timer is reset when a pulse signal is input from the power supply controller 1 to the signal line 7 at a constant period. When the processing unit 10 of the power supply controller 1 does not input at a fixed cycle due to an abnormal operation due to runaway or the like, the time is over and the reset output unit 22 is driven. The reset output unit 22 is driven when a voltage that is equal to or higher than a certain level or drops from a certain level is detected from the battery voltage detection unit 2e. The reset output unit 22 generates a reset signal from the reset line 8 to the power supply controller 1 and the system circuit of the electronic device when driven. At this time, the reset output unit 22 masks the input function in the transfer control unit 20.

When a reset signal is input from the reset line 8 to the reset unit 12 of the power supply controller 1, the power supply controller 1 including the processing unit 10
Resets each part inside to stop runaway and to prevent malfunction of the system circuit. When the reset unit 12 is driven, the output line of the transfer control unit 11 saves power.

Next, the second principle configuration of FIG. 2 is different from the configuration of FIG. 1 in the point that the peripheral circuit 2 does not include a configuration for controlling the DC-DC converter 4. 2a and 2b shown in FIG. 1 are not provided. Since the control of the power supply controller 1 does not control the DC-DC converter 4, the load is reduced. The other configuration of the peripheral circuit 2 and the basic configuration of the power supply controller 1 are shown in FIG.
The description is omitted because it is the same as.

[0021]

FIG. 3 is a block diagram of an embodiment of the present invention, which corresponds to the first principle configuration shown in FIG. 1, but has the same functions as those of the second principle configuration shown in FIG. It can be implemented by the configuration.

In FIG. 3, reference numeral 30 denotes an AC adapter for inputting AC power and converting a DC voltage, 31 to 34 correspond to 1 to 4 in FIG. 1, and 35a and 35b correspond to 5a and 5b in FIG. , 36 to 38 respectively correspond to 6 to 8 in FIG. That is, 31 is a power supply controller composed of a microcomputer (microcomputer) and each control unit having an interface with the outside, 32 is a peripheral circuit for power control, 33 is a battery, 34 is a DC-DC converter, and 35a is A charge switch (SW), 35b is a discharge switch (SW), 36 is a control data line for transmitting serial control data, and 37 is a watchdog timer (WD).
T) a signal line for transmitting a pulse, and a reset line 38 for transmitting a signal for resetting the computer of the power supply controller 31. Reference numeral 39 denotes a system circuit for performing logical processing in an electronic device such as a notebook personal computer, and reference numeral 40 denotes a display unit such as a liquid crystal to which power is supplied from a power supply controller 31. Reference numeral 9 denotes a system similar to that shown in FIGS. It is a voltage detector.

In the power supply controller 31, 31
0 indicates a peripheral circuit control unit (the transfer control unit shown in FIG. 1) which identifies the charge voltage of the battery 33 detected by the peripheral circuit 32 and the detection value of the output voltage of the DC-DC converter 34, and generates and transmits corresponding control data. Part 11). 311
Denotes a system power control unit, which controls power supply to the system circuit 39 of the electronic device in accordance with ON / OFF input of a power switch (SW) 41 and a clock power supply 42.
To control the driving and stopping of the clock oscillator 43,
Further, the output of the system reset to the system circuit 39 is controlled. The data check unit 312 is a circuit that checks whether or not the transmission has been normally performed by comparing the loopback data from the loopback data unit 32f of the peripheral circuit 32 with the data transmitted from the peripheral circuit control unit 310 to the peripheral circuit 32. .

Reference numerals 32a to 32d in the peripheral circuit 32 correspond to 2a to 2d in FIG. 1, 32e is an A / D converter for converting a battery voltage into a digital signal, and 32f is a return data unit. When the data sent from the power supply controller 31 is received by the transfer control unit 320, the return data unit 32f transfers the content to the return data unit, and from there, returns the data of the power supply controller 31 via the return line. The data is transmitted to the check unit 312. Transfer controller 320, watchdog timer (WD
T) The monitoring unit 321 and the reset circuit 322 are 20 to
22.

The DC-DC converter 34 is a DC power supply from the AC adapter 30 or a discharge SW3 from the battery 33.
5b, the generated DC power is supplied to the power controller 31, the peripheral circuit 32, and the system circuit 39. The DC voltage is detected by the voltage detector 32a of the peripheral circuit 32, and the transfer controller 320 ( 1 of FIG.
0), power supply controller 31 via control data line
The control data is sent to the peripheral circuit control unit 310 to generate control data so as to have a predetermined DC voltage. The control data is serially transmitted to the transfer control unit 320 of the peripheral circuit 32 via the control data line 36. Is sent to the DC controller 32b to generate a signal for controlling the output voltage of the DC-DC converter 34.

The charging and discharging operations of the battery 33 are performed by transmitting control data from the peripheral circuit control unit 310 of the power supply controller 31 to the transfer control unit 320, thereby driving the charge control unit 32c or the charge control unit 32c. The charging SW 35a or discharging SW 35b to be turned on is switched on. The voltage of the battery 33 at the time of charging is converted into a digital signal by the A / D converter 32e, sent to the transfer controller 320, and then sent to the power controller 31 to perform charging control.

When a voltage drop (−ΔV) during battery charging is detected in the charging operation of the battery 33, it is determined that the battery is fully charged, and the charging SW 35a is turned off. Reset circuit 322
Generates a reset signal based on the output from the WDT monitor 321 and generates a reset signal based on the detected output when the system voltage detector 9 detects that the system voltage has dropped below a certain level. The reset signal is sent to the power supply controller 31 and also supplied to the system circuit 39 to reset each of them. At this time, a signal indicating the type of reset is generated.

The power supply controller 31 includes a peripheral circuit 32
When a reset signal is received from the controller, the internal control units (microcomputers) are reset to stop the runaway state, stop overcharging during charging, and stop overdischarging during discharging.
At the same time, the charging SW 35a or the discharging SW in the peripheral circuit 32
Clear the register that controls 35b, and switch SW35a,
Turn off 35b. Further, the output port of the control data line 36 of the peripheral circuit control unit 310 is set to a high impedance state by receiving the reset signal.

FIG. 4 shows a configuration of a control data line between the power supply controller and peripheral circuits. The control data line 36 is provided between the peripheral circuit control unit 310 in the power supply controller 31 of FIG. 3 and the transfer control unit 320 of the peripheral circuit 32, and serial data is written in the transfer control unit 320 (peripheral). A register 320a for writing from the circuit control unit 310 to the transfer control unit 320 and a register 320b for reading (reading data of the transfer control unit 320 into the peripheral circuit control unit 310) are provided.

The control data line 36 is connected to four of 36a to 36d.
The line 36a is a serial synchronous clock line, 36b is a serial write data line, 36c is a serial data latch line for transmitting a timing signal for setting write data to a register 320a in the transfer control unit 320, and 36d is a serial data latch line. This is a serial read data line for transferring data from a peripheral circuit to the power supply controller.

FIG. 5 shows an example of the waveform of each line shown in FIG. 4. When the serial synchronous clock shown in (2) is sent from the peripheral circuit control unit 310 via the serial synchronous clock line 36a, the transfer control unit 320 Is transmitted via the serial read data line 36d as shown in FIG. 5 (1). The data write operation is performed when the 8-bit data shown in (3) of FIG. 5 is transmitted via the serial write data line 36b in synchronization with the serial synchronization clock shown in (2).
At the rising edge of the serial synchronous clock, the data is fetched and sequentially input to the register 320a, and the register 3a is input at the rising edge of the serial data latch signal shown in FIG.
8-bit data is set in 20a. The data to be set include data for setting the operation state of each part of the peripheral circuit, commands for instructing the operation of the peripheral circuit, and the like.

Power supply controller (peripheral circuit controller 3)
Data (including commands) for setting the state of the peripheral circuit (transfer control unit 320) from 10) will be described. In this embodiment, the data to be set is 8 bits, and is transmitted as the serial write data shown in (3) of FIG.
It is supplied to one of the circuits shown in FIG.
For example, it is data that turns on or off the charge SW 32c or the discharge SW 32d, or specifies and operates one of the A / D conversion circuits when a plurality of A / D conversion circuits are provided.

FIG. 6 shows a configuration example of 8-bit data sent from the power supply controller to the peripheral circuit. In this example, the lower 4 bits of bits 0 to 3 are a data address, which indicates the address of the data to be set (setting destination or meaning), and the upper 4 bits of bits 4 to 7 are data contents. Indicates the content (function) to be performed.

FIG. 7 shows the data transfer order. As shown in the figure, the least significant bit (bit indicated by LSB)
The data address is sent up to bit 3 starting with 0), and then bits 4 to 7 of the data are sequentially transferred. The data set in the register 320a of the transfer control unit 320 of the peripheral circuit is decoded and the corresponding processing is performed.

When the data of the AD conversion function (command) shown in FIG. 6 is set from the power supply controller to the peripheral circuit, all the lower 4 bits (bit0 to bit3) are set to "0" (0h: h is hexadecimal display). ) Represents the A / D conversion function, and b in the upper 4 bits (bit 4 to bit 7)
It4 is set to "1" to start the A / D conversion.
The AD conversion circuit is selected by each bit of bit5 to bit7. The order of the eight bits transferred in this case is shown in FIG. Shown in

When the "charging control" shown in FIG. 6 is set, the lower 4 bits are set to 2h to indicate that the charging is controlled, and the upper 4 bits control the plurality of charging switches "charging 1 to charging 4". Which of the switches is turned on or off is represented by "1" or "0" of each bit. The dummy code is described later (described with reference to FIG. 8).
it3) is 1h (h is a hexadecimal notation) to indicate a Dami code, and all upper 4 bits are set to "1".
Similarly, various other functions such as “clock control” can be set.

FIG. 8 is a diagram showing a signal structure when data of a peripheral circuit is read from the power supply controller. In the case of reading, the data control lines 36a-3a shown in FIGS.
6d is used, and FIG. 8 shows the signals of the two lines therein, a. Is serial write data (line 36b), b. Is serial read data (line 36d).

When the power supply controller reads the state in the peripheral circuit 32 (for example, the converted value of the A / D converter), a read command is first transferred to the peripheral circuit from the power supply controller side on the serial write data line. . In the read command, a function of the command (in this case, read) and a circuit to be read (for example, which AD conversion circuit) is specified. The peripheral circuit (the transfer control unit 320) that has received this sets the conversion value of the corresponding A / D conversion circuit in the register 320b.

Thereafter, a. When a dummy command (this content has no meaning as a command) is transmitted from the power supply controller as serial write data as shown in FIG. The D-converted value is output as read data to the serial read data line and transferred to the power supply controller. At this time, the dummy command and the read data are the same as those in FIG.
As shown in (1), transmission and reception are performed in synchronization with the serial synchronization clock.

Next, the relationship between the watchdog timer (WDT) and the reset of the power supply controller will be described with reference to FIG. FIG. Is a watchdog timer (W
DT), and this pulse is supplied from the power supply controller 31 of FIG. 3 to the watchdog timer (WD).
T) For the monitoring unit 321, a constant pulse width t1 (for example,
50 μs) and a constant interval t2 (for example, 200 ms)
Is output. The WDT monitoring unit 321 of the peripheral circuit 32
It is monitored whether or not the pulse is output normally. If the output is not generated normally, b. A reset signal is generated as shown in FIG. This reset signal is generated by driving the reset circuit 322 by an output generated when the WDT monitor 321 in FIG. 4 detects that the pulse interval has exceeded the time t2. B of FIG. Is a reset signal generated from the reset circuit 322. The power supply controller 31 is reset by this reset signal. At this time, the signal (status signal) indicating the type of reset output from the reset circuit 322 in FIG. As shown in FIG.

In the case of a reset output at power-on, the status signal indicating the type of reset is low.
(Low) level. As a result, it is possible to analyze the cause when the power supply controller 31 is reset.

The reset signal generated from the reset circuit of the peripheral circuit 32 shown in FIG. 3 is also output to the system circuit 39 of the electronic device to initialize the system circuit. Upon receiving this reset signal in the power supply controller 31, the output port in the peripheral circuit control section 310 (output port to the control data line to the peripheral circuit) is made high impedance by the configuration shown in FIG.

That is, FIG. 10 shows the configuration of the output port of the power supply controller. The same circuit is provided corresponding to a plurality of lines (control data lines 36a to 36d in FIG. 4) connected to the peripheral circuit. . In the figure, DV is a driver for outputting a signal a to the line, and G is a gate for controlling the driver. FF is a flip-flop circuit, which is set by the input of a reset signal. When the set output is input to the gate of the driver DV, the driver DV is set to a high impedance state. As a result, the current from the power supply (5 V) supplied to the line via the resistor R is reduced, and power consumption is suppressed.

Also, the clock oscillation is stopped by reset control of the system power control unit (311 in FIG. 3) in the power control controller 31 by the reset signal to suppress power consumption, and the system is controlled even when the power control controller goes out of control. Minimize damage.

FIG. 11 is a signal waveform diagram of each part in the power supply controller when the system is started by pressing the power switch. D of FIG. Power as
When the switch is pressed, a. The system reset signal having the waveform shown in the figure is generated at the timing shown in FIG. 3 by the system power controller 311 of the power controller 31 (see FIG. 3).
Arising from The system reset signal causes the system circuit 39 to be in a reset state for a certain period of time. As shown in (1), the clock oscillating unit 43 starts oscillating. When the oscillation of the clock oscillator 43 is stabilized, a. Is released, and the system circuit 39 can be started up normally.

FIG. 12 is a diagram showing the timing relationship of the return check of serial write data. From the power supply controller 31 to a. In synchronization with the serial synchronization clock of b. Is transferred to the peripheral circuit 32, the signal received by the transfer control unit 320 in the peripheral circuit 32
2f to FIG. Is supplied as a signal as shown in FIG. Are set in the transfer control section 320 and the return data section 32f by the serial data latch signal shown in FIG. When the data of the return data section 32f is supplied to the data check section 312 of the power supply controller 31, the data check section 312 can check whether the write data and the return data have been transferred normally by collating the write data with the return data.

FIG. 13 shows another configuration example of the peripheral circuit. This configuration corresponds to the peripheral circuit in the second basic configuration of the present invention shown in FIG. 2 and shows the main part thereof. FIG.
3, reference numerals 200, 210, 220, and 9 correspond to the circuits having the same reference numerals in FIG.
Denotes a watchdog timer (WDT), 220 denotes a reset output unit, and 9 denotes a voltage detection unit (corresponding to the system voltage detection unit in FIG. 2). Reference numeral 201 in the transfer control unit 200 denotes a data conversion circuit, and reference numeral 202 denotes a register.

The transfer control unit 200 receives control data for setting the charging / discharging state from the power supply controller, as shown in FIG.
6a to 36d, the respective signals of the serial synchronization clock, serial write data, and serial data latch are received via the control data line.
01, and is converted to serial / parallel.
Set to 2.

FIG. 14 shows an example of the configuration of the charge / discharge control unit.
FIG. 14 shows a configuration in which charging / discharging is performed by data set by the configuration of FIG. When the data from the power supply controller is set in the register 202 shown in FIG. 14, the flip-flop circuits FF1 and FF2 are set or reset in synchronization with the clock (CK) signal according to the content of each bit. Flip-flop circuits FF1, FF
2 is set, the corresponding discharge SW (5b in FIG. 2) or charge SW (5 in FIG.
a) is driven on to start a discharging operation or a charging operation. When charging or discharging is stopped, control data for stopping the charging or discharging is set in the register 202 from the power supply controller. Each of the flip-flop circuits FF1 and FF2 is connected to a reset output unit (22 in FIG. 13).
0) is reset regardless of the state of the register by the reset signal (RST) generated from
Is turned off.

FIG. 15 shows an example of the configuration of the data input section of the peripheral circuit, which is provided on the input side of the conversion circuit 201 in FIG.
This is one of a plurality of circuits provided corresponding to each line (control data line) for data input from the power supply controller.

RV1 to RVn are receivers for receiving signals from the power supply controller, and DT is a rise detection circuit. The receiver RV1 receives the first input pulse after resetting the pulse (for the watchdog timer) input from the power supply controller at a fixed cycle, and the receivers RV2 to RVn control the control data lines (serial synchronous clock line, serial data write). Line, serial data latch line, etc.). The reset circuit (2 in FIG. 13) is connected to the input floating terminal of the receiver RV1.
When the reset signal is supplied from 20), the receiver RV
1 is masked.

That is, a signal is supplied to each input floating terminal of each of the receivers RV2 to RVn by reset, and masking is performed. In this masked state, reception becomes impossible, but after the reset signal is released, the first pulse from the power supply controller is output to the receiver RV1.
, The rising edge of the pulse is detected by the rising edge detection circuit DT, and the detection output indicates that the receiver RV2
~ RVn is released and data can be received.

FIG. 16 is a waveform diagram of the output of the DC power supply and the voltage detector. FIG. Is a DC power supply (DC-D in FIG. 2)
(DC voltage output from the C converter)
The vertical axis is DC voltage, and the horizontal axis is time. b. Represents a detection waveform of the system voltage detection unit, the vertical axis represents a reset drive signal (a signal of which polarity is represented by * RST inverted), and the horizontal axis represents time. When the DC voltage rises at time t0 and becomes the voltage V1, the reset drive signal from the voltage detector rises at time t1. When the DC drive voltage rises to a predetermined voltage V2 (> V1), the reset signal disappears. Thereafter, when the DC voltage drops and becomes lower than the voltage V2, a reset drive signal is generated during that period (time t3 to t4).

FIG. 17 is a configuration diagram of the reset circuit. The reset circuit (220 in FIG. 13) is provided with the reset drive signal a shown in FIG. 16 from the system voltage detector (DC detector) and a watchdog timer (WDT in FIG. 13).
Receiving the reset drive signal b from the OR circuit 221,
When a reset drive signal is generated from any of them, a first reset signal indicated by RST1 is output to the system circuit (electronic device) to reset the system circuit. The output (RST1) of the OR circuit 221 is input to the counter 223, where it is delayed for a certain time. Therefore, OR circuit 2
Since the signal RST1 and the output of the counter 223 are input to 22, a second reset signal RST2 wider than the signal RST1 is generated. This reset signal RST2 is
It is sent to the power supply controller and works to reset the internal microcomputer.

Next, FIG. 18 is a flowchart showing the operation of the peripheral circuit for issuing a reset by monitoring the above-described watchdog timer (WDT) and monitoring the DC power supply. When the power is first turned on (S1 in FIG. 18), the reset of the peripheral circuit is released once (S2). Thereafter, a reset signal for resetting the microcomputer of the power supply controller (RST in FIG. 17)
2) is issued as a single-shot signal (S in FIG. 18).
3)).

On the other hand, in parallel with the issuance of the reset signal, DC
Power supply monitoring (by the system voltage detector 9) is performed, and D
It is determined whether there is a drop of the C power supply (S in FIG. 18).
25). If a drop is detected, a reset is issued to the power supply control circuit (S16), and monitoring is performed thereafter.

In step S3, the power supply controller is reset once, and the reset is released after a lapse of a predetermined time, and a pulse (for WDT) from the power supply controller is issued.
It is determined whether or not has been input (S4), and if it has been input, the input port is opened (S5) and data input is started (S6). Thereafter, it is determined whether or not there is a data input (S7), and if so, a data command based on the data input (ON or OFF of the charge SW and discharge SW).
(S8) and returns to S7 to wait for another data input.

In step S4, when there is a pulse input, a watchdog timer (WDT) is also started at the same time, and it is determined whether a timer interrupt is generated from a timer provided in the peripheral circuit and generating an output at regular intervals. (Figure 1
8 S9). When this interrupt occurs, the counter of the watchdog is incremented by 1 (S10). When there is no timer interrupt and after incrementing the counter of the watchdog timer by 1, it is determined whether there is a pulse (for WDT) input from the power supply control circuit (S11). If there is a pulse input, the counter of the watchdog is cleared, and subsequently (even when there is no pulse input), it is determined whether or not the counter of the watchdog has exceeded a preset predetermined value (S13). If not, the process returns to S9. If the value exceeds the certain value, a reset is issued due to time-out (S14). Thereafter, the process shifts to the process of S4, and monitoring by the watchdog timer is continuously performed.

FIG. 19 is a timing chart for issuing a reset in each state of the operation of the WDT and the voltage reduction when the power is turned on. a. When the DC power supply is turned on and the voltage starts increasing as shown in b. A reset drive signal (* RST signal same as b. In FIG. 16) having a waveform represented by (1) of FIG. As shown in (1), reset signals (RST1 and RST2 in FIG. 17) are generated when the power supply rises. After the reset signal is released, d. Pulse input from power supply controller as shown in (for WDT)
, P1 and P2 are input. While this pulse is input, g. The watchdog timer (WDT) shown in FIG. When there is a data input (from the power supply controller) shown in FIG. In the example shown,
When data indicated by D1 is input first, f. The operation for controlling the charge / discharge SW instructed by the data is performed as shown in FIG.

In the example shown in FIG. 19, if a pulse from the power supply controller is not inputted for a predetermined time after P2 is inputted, g. Watchdog timer (WD)
An output is generated from T). With this output, b. of 2)
The reset drive signal (* RST signal) shown in
c. Therefore, a reset signal is generated. The generation of this reset signal causes f. Charge / discharge SW shown in
Is reset (open), and the charging or discharging operation is stopped (the data input is also stopped).

After the reset signal is released, D
If the voltage of the C power supply is a. As shown at the back of the figure, if the voltage falls down to a certain level or less for a short time, b. The reset drive signal shown in (3) is generated. Correspondingly, c. A reset signal shown in FIG. Therefore, e. Stops the operation of data input indicated by D2, and f. Charge / discharge SW shown in
Is reset.

The configurations shown in FIGS. 13 to 19 can be applied to the case where the first principle configuration shown in FIG. 1 is implemented. Similarly, the configurations shown in FIGS. 3 to 12 are shown in FIG. Obviously, it can be applied to the case where the second principle configuration is implemented.

[0063]

According to the present invention, in an electronic device having a battery charge / discharge function, such as a notebook personal computer,
By configuring a circuit around the power supply as a one-chip circuit and controlling the circuit by a power supply controller configured by a microcomputer, it is possible to realize a reduction in size, space, and cost of the entire apparatus. In addition, erroneous control of noise in charge / discharge control is not performed, and variation in accuracy of the analog circuit can be reduced.

Further, in a power supply control device which performs charge / discharge control of a battery by a program, resetting is performed when the DC voltage drops or the power supply control device runs away, thereby preventing the system from running away and overcharging and overcharging the battery. Discharge can be prevented to prevent battery deterioration and ignition.

Further, even if the output port from the control device becomes unstable immediately after the reset of the control device, the input from the peripheral circuit is masked so that the data from the control device is not erroneously recognized.

[Brief description of the drawings]

FIG. 1 is a first principle configuration diagram of the present invention.

FIG. 2 is a second principle configuration diagram of the present invention.

FIG. 3 is a configuration diagram of an embodiment of the present invention;

FIG. 4 is a diagram showing a configuration of a control data line between a power supply controller and peripheral circuits.

5 is a diagram illustrating an example of a signal waveform of each line illustrated in FIG. 4;

FIG. 6 is a diagram illustrating a configuration example of 8-bit data sent from a power supply controller to a peripheral circuit.

FIG. 7 is a diagram showing a data transfer order.

FIG. 8 is a diagram showing a signal configuration when reading data of a peripheral circuit from a power supply controller.

FIG. 9 is a diagram illustrating a relationship between a WDT and a reset of a power supply controller.

FIG. 10 is a configuration diagram of an output port of a power supply controller.

FIG. 11 is a signal waveform diagram of each unit in the power supply controller when the system is started by pressing the power switch.

FIG. 12 is a diagram showing a timing relationship of a return check of serial write data.

FIG. 13 is a diagram illustrating another configuration example of the peripheral circuit.

FIG. 14 is a diagram illustrating a configuration example of a charge / discharge control unit.

FIG. 15 is a diagram illustrating a configuration example of a data input unit of a peripheral circuit.

FIG. 16 is a waveform diagram of an output of a DC power supply and a voltage detection unit.

FIG. 17 is a configuration diagram of a reset circuit.

FIG. 18 is an operation flow of issuing a reset by monitoring WDT and DC power of peripheral circuits.

FIG. 19 is a timing chart of reset issuance in each state of the operation of the WDT and the voltage drop when the power is turned on.

FIG. 20 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Power supply controller, 10 Processing part 11 Transfer control part 12 Reset part 2 Peripheral circuit for power supply control 20 Transfer control part 2a DC voltage detection part 2b DC control part 2c Charge switch (SW) control part 2d Discharge switch (SW) control Unit 2e battery voltage detection unit 3 battery 4 DC-DC converter 5a charge switch (SW) 5b discharge switch (SW) 6 control data line 7 pulse (for watchdog timer) 8 reset line 9 system voltage detection unit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tsuyoshi Morita 4-49 Fukami Nishi, Yamato-shi, Kanagawa Prefecture PF Yamato Plant Co., Ltd. (72) Takaaki Morimura 4-49 Fukami Nishi, Yamato-shi, Kanagawa Prefecture No. 56 Inside the PF Yamato Plant (56) References JP-A-4-107716 (JP, A) JP-A-7-5958 (JP, A) JP-A-5-103429 (JP, A) Jpn. 88426 (JP, U) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 1/26-1/32 H02J 7/00-7/12 H02J 7/34-7/36

Claims (6)

(57) [Claims] 1. A power supply control method for a portable electronic device having a battery charge / discharge function, comprising: a DC-DC converter driven by an external power supply or a battery for supplying power to the electronic device; And DC-
A power supply controller for controlling each of charging of the battery by the output of the DC converter; a charge / discharge switch control unit connected to the power supply controller and the control data line for controlling a switch for charging / discharging the battery;
A battery voltage detection unit for detecting a voltage of a battery; and a one-chip power supply control peripheral circuit including a register for receiving control data sent from the power supply controller and setting an operation state of each unit, A power supply control method, comprising: setting control data from the power supply controller to the peripheral circuit to perform charge / discharge control of a battery. 2. A power supply control method for a portable electronic device having a battery charge / discharge function, comprising: a DC-DC converter driven by an external power supply or a battery for supplying power to a system circuit of the electronic device; DC-D
A power supply controller that controls the voltage of the C converter and controls each of the discharging of the battery and the charging of the battery by the output of the DC-DC converter; and a DC-DC connected to the power supply controller and a control data line.
A DC voltage detector of the converter, a DC controller for outputting a signal for controlling the DC-DC converter, a charge / discharge switch controller for controlling a battery charge / discharge switch, a battery voltage detector for detecting the voltage of the battery; One-chip peripheral circuit including a transfer control unit that receives control data sent from the power supply controller, sets an operation state of each unit, and sends a detection value of the DC voltage detection unit to the power supply controller. And a power supply controller that sets a state of each part of the peripheral circuit from a peripheral circuit and controls conversion of a DC-DC converter and control of charging and discharging of a battery. 3. The watchdog timer according to claim 1, wherein the peripheral circuit receives a pulse signal generated at a constant cycle from the power supply controller, and generates an output if the pulse signal is not input at a fixed cycle. A reset output unit for generating a reset signal in accordance with one of an output from the watchdog timer and a detection signal of a voltage drop of a battery, and generating a signal indicating a type of reset. A power supply control method, wherein the circuit is reset by the reset signal. 4. The system circuit according to claim 3, further comprising a power switch provided outside the power control controller, wherein when the power is turned on by the power switch, a reset signal is supplied from the power control controller to a system circuit of the electronic device. A power supply control method characterized in that a reset is released after a certain period of time when the clock oscillation operation of the clock becomes stable. 5. The control circuit according to claim 3, wherein the peripheral circuit supplies a reset signal generated from the reset output section to the transfer control section to mask a signal from an input power supply controller via the control data line. And a power control controller masking a signal output from the control data line to the peripheral circuit by a reset signal from the peripheral circuit. 6. The power supply controller according to claim 1, further comprising a data check unit provided in the power supply controller, a data return unit connected to a transfer control unit in the peripheral circuit, and a connection between the data return unit and the power supply controller. Power supply control means, wherein the power supply controller checks the return data from the peripheral circuit via the connection means in the data check unit when the power supply controller transmits setting data to the peripheral circuit.