JP2940895B2 - Clock recovery circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase modulation signal clock recovery circuit suitable for use in digital radio communication.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration example of a conventional baseband digital clock recovery circuit for a π / 4 shift QPSK modulation signal. Further, an example in which the received signal sample rate is a double symbol rate will be described. The modulation signal phase detection circuit 10 detects the modulation signal phase of the received π / 4 shift QPSK modulation signal A.

Here, an example of detection of a modulation signal phase will be described with reference to FIG. First, the modulation signal A is converted into an intermediate frequency in the modulation signal phase detection circuit 10, band-limited through a band-pass filter, and then amplitude-limited. FIG. 8A shows an intermediate frequency signal waveform, and FIG. 8B shows an amplitude-limited intermediate frequency signal waveform. By the way, π / 4 shift Q
In the PSK modulation method, the carrier envelope has a baud timing frequency component. Therefore, the baud timing is obtained by detecting this baud timing frequency component and inputting it to the phase locked loop. The baud timing signal rises at the baud timing t ₀ shown in FIG. (D).

Next, the modulation signal phase detection circuit 10 is provided with a phase counter which is reset in synchronization with the baud timing t ₀ and counts a predetermined clock signal. ). After detecting the baud timing t ₀ , the modulation signal phase detection circuit 10 detects the closest rising time t ₁ of the baud timing signal. Then, the time from the baud timing t ₀ to the rising time t ₁ , that is, the relative phase of the intermediate frequency signal is detected based on the output of the phase counter.

[0005] The above-described modulation signal phase detection technique uses:
For example, Tomita et al., “Digital Intermediate Frequency Demodulation Method”,
B-299, 1990 IEICE Autumn National Convention ". Instead of this, the one described in “Yamamoto et al.,“ A Study of π / 4 Shift QPSK Baseband Delay Detector ”, B-342, 1992 IEICE Spring National Convention” may be used. .

A modulation signal phase detection circuit 10 outputs a modulation signal phase B at a double symbol rate by using a clock signal L2 and a clock having a phase difference of a half symbol. However, here, the clock phase has a uniformly random value. The one-symbol difference circuit 20 outputs a difference signal C between the signal B and a signal obtained by delaying the signal B by one symbol period. Next, the zero-cross detection type clock phase advance /
The delay detection circuit 90 performs zero-cross detection using the signal C, and outputs a signal Q corresponding to the advance or delay from the discrimination point of the clock phase.

Here, the time series of the signal C is represented by Ci = C (i
× T / 2), (i = 0, 1, 2,...), T is a symbol period, and an even-numbered subscript i is a signal to be used as a discrimination point timing. First, the zero cross C _i × C _{i + 2} <0 of the signals C _i and C _{i + 2} is detected. Next examine the signal C _{i + 1} of the polarity relationship between the polar and C _i and C _{i + 2} of the signal Ci,

When C _{i + 1} × C _i > 0 Equation (2), clock phase advance is detected, and when C _{i + 1} × C _i <0 Equation (3) is detected, clock phase delay is indicated. The signal Q is output.

The signal Q is input to a digital filter 101 having a variable number of filter stages and filtered to become a signal R2 for providing a clock correction direction. The clock generator reproduces the clock by advancing or delaying the clock phase according to the signal R2. In the case of initial clock synchronization, a method of reducing the number of filter stages of the digital filter to increase the frequency of occurrence of the signal R2 for providing a clock correction direction, or reducing the frequency division ratio of the reference signal U and increasing the clock phase correction width. In this case, a method of hastening the initial synchronization of the clock is used.

[0010]

However, in the conventional clock recovery method, the clock is recovered by feedback in principle, and even if a method of speeding up the clock initial synchronization is used, it is necessary for the clock initial synchronization. There was a limit to the reduction of redundant bits. Also, when a carrier frequency error exists, the jitter at the zero-cross point increases in the zero-cross method, and the reproduction clock error increases. The present invention has been made in view of the above circumstances, and has as its object to provide a clock recovery circuit capable of performing clock phase initial synchronization using short redundant bits.

[0011]

Means for Solving the Problems] In the arrangement according to claim 1 for solving the above problems, one differential signal of the phase
The component crosses the zero point alternately for each symbol and the polarity is reversed.
The difference between a modulation phase detection circuit that outputs a phase of a received phase modulation signal in a digital phase modulation signal demodulation circuit that operates on the synchronized preamble signal and a signal delayed by one symbol period is represented by k (k ≧ 2). ) times out and k times the difference circuit to force said k times the difference circuit and the clock phase estimation integrating circuit to obtain a signal used to clock phase estimation based on the output, the initial clock position Aijo report from the integral circuit output said clock phase estimate And a clock timing selection circuit for selecting a clock timing based on the clock signal. Further, in the configuration of claim 2, prior
The first difference calculation result by the k-th difference circuit is used as an input.
To perform zero-cross detection and advance or delay the clock phase.
A zero-cross detection type clock phase advance / delay detection circuit for detecting the
Clock correction based on detection result by delay detection circuit
A digital filter for outputting a signal indicating a direction , wherein the clock timing selection circuit includes
Clock phase information estimated by the lock phase estimation circuit
Information and an output signal of the digital filter.
It is characterized in that clock timing is selected .

[0012]

According to the configuration of the first aspect, in the demodulation circuit of the digital phase modulation signal, the modulation signal phase detection circuit alternately cancels the phase component of the differential signal once for each symbol.
A preamble signal for synchronization whose polarity crosses the point
And outputs the phase of the received phase-modulated signal. The k-th difference circuit calculates the difference from the signal delayed by one symbol period as k
(K ≧ 2) times and outputs. Next, in the integrating circuit for clock phase estimation, a signal used for clock phase estimation is obtained based on the output of the k-th difference circuit. The clock phase estimating circuit estimates the initial clock phase from the output of the clock phase estimating integration circuit. Then, the clock timing selection circuit selects a clock timing based on the clock phase information estimated by the clock phase estimation circuit. Further, in the configuration according to the second aspect, the zero-cross detection type clock phase advance / delay detection circuit further receives the first difference calculation result by the k-th difference circuit as an input.
Performs zero-cross detection to detect the leading / lagging of the clock phase, and the digital filter performs filtering.
Thus, a signal indicating the clock correction direction is output . And ku
Clock phase estimation in lock timing selection circuit
The clock phase information estimated by the circuit and the digital
Clock timing based on the output signal of the
Is selected, the advance or delay of the clock timing of the reproduced clock is detected, and the clock timing is adjusted according to the detection result.

[0013]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention for a π / 4 shift QPSK modulation signal. In this example, the reception signal sample rate is twice the symbol rate, and the k-time difference circuit uses a 2-time difference circuit. Receiving π / 4
The shift QPSK modulation signal A is output from the modulation signal phase detection circuit 10.
The modulation signal phase is detected at (see the section of the prior art). The modulation signal phase detection circuit 10 outputs the clock signal L1
And a modulated phase signal B is output at a double symbol rate by a clock having a clock phase difference of a half symbol from L1. However, here, the clock phase has a uniformly random value.

The signal B is a difference signal Ci = C from the signal delayed by one symbol period by the one-symbol difference circuit 20.
(I × T / 2), (i = 0,1,2, ...) becomes, in the case of clock initial synchronization is sent by the switch 30 to the one-symbol differential circuit 40, further, one symbol period delayed signal And a difference signal Di = D (i × T /
2), (i = 0, 1, 2,...). Twice the difference signal Di is SP converted by the serial-parallel converter _{50, E j = D 2j,} Fj = D 2j + 1, (j = 0,1,2, ...), a (see FIG. 3). Signal E _j, F _j is respectively inputted to a clock phase estimator for integrating circuit 60 and 61, the signal E _j, F _j of M every other symbol signal divided by M After inverting integrating a sign G, and H Become. That is, the signals G and H are as shown in the following equations (4) and (5).

[0015]

(Equation 1)

(Equation 2)

The clock phase estimating circuit 70 outputs signals G, H
Is used to estimate the clock phase. π / 4 shift QPSK
In the modulation method, the values of the signals G and H when the (1,0,0,1,1,0, ..) sequence of alternating signals (see FIG. 3) are input are shown in FIG.
Shown in Variables Ej and Fj in equations (4) and (5)
Corresponds to the two-time difference values Ej and Fj shown in FIG.
Then, the difference value twice in FIG. 3 is sampled twice (symbol
(2 times the speed). Given by equation (4)
The value of G is sampled twice when there is no noise.
It corresponds to the first value of the obtained sample values. As well
In addition, the value of H obtained by equation (5) is
To the second value from the beginning of the sample value obtained by ringing
Equivalent to. For example, at the beginning Ej in FIG.
E0) means that the clock phase on the horizontal axis is 8, and the phase on the vertical axis is
When the value is 160 deg. And the next place of Ej + 1 (E1)
The phase value is -160d obtained by inverting the sign of the phase value of E0.
eg. It is. The phase values of E0 and E1 are expressed by equation (4).
Substituting, G = 160 deg. Is obtained. This value
Is G when the clock phase on the horizontal axis is 8 shown in FIG.
With the phase value of. Actual circuits have noise
Then, in order to average this noise component, using equation (4)
The average of the M phase values is taken, but the signs of the phase values are alternately reversed.
Since rolling, in the formula (4), the Ej the (-1) ^j
Multiply, equalize the sign of each phase value, take the sum,
The sum is divided by the number M of samples. For equation (5),
The same is true. As can be seen from FIG.
To combine G and H obtained by (5)
This makes it possible to uniquely determine the clock phase.
Based on this principle, the clock phase shift is estimated. What
In FIGS. 3 and 4, the clock phase is 0 or 32.
Is defined as an identification point, that is, a point with zero clock error
Have been. The clock phase estimating circuit 70 can be realized by calculating the values of the signals G and H corresponding to the clock phase and writing the values to the ROM having the signals G and H as addresses.
An effective method for reducing the ROM capacity will be described. The clock timing has an accuracy of 1/32 of one symbol period (N = 3
The case where the estimation is performed in 2) will be described as an example.

First, the absolute values of the signals G and H are compared and the smaller value is selected, and then the k value corresponding to the selected value is selected according to the rule shown in FIG. Further, using the k value, the calculation shown in FIG. 7 is performed based on the magnitude relationship and the sign relationship between the signals G and H, and the clock phase is estimated. Above
As described above, it is calculated by the equations (4) and (5).
By combining G and H, the clock phase
The estimation is based on the rule shown in FIGS. 6 and 7.
It is performed according to. In this rule, the clock estimation
Clock phase is divided into 8 to facilitate
ing. This division is indicated by a broken line in FIG.
ing. Then, min indicated by a thick line in FIG.
(| G |, | H |) to the rule shown in FIG.
Get the value of k. The obtained value of k is converted into the rule shown in FIG.
Fit and estimate the clock phase. Note that FIG.
At the top of the graph,
The calculation formula based on the rule shown in FIG. 7 is described. This method
The clock phase is estimated using the value of the thick line portion in FIG. 4, and the selection of the k value can be easily realized by a ROM having a small capacity as compared with the method using the signals G and H as addresses.
The sampling timing selecting circuit 80 selects a clock signal corresponding to the signal J indicating the clock phase output from the clock phase estimating circuit 70 from among the clock signals having different phases generated by the N-times symbol rate oscillator. The reproduction clock L1 is output. FIG. 5 shows an example of the clock phase estimation error.

If the clock phase error gradually occurs due to the symbol rate of the received signal and the frequency error of the clock signal generated by the reference signal generator after the initial synchronization of the clock, the zero-cross detection type clock phase advance / delay described in the conventional method. A detection circuit and a circuit using a digital filter are added, and a sampling timing selection circuit 80 selects a clock signal having a leading / lagging clock phase as compared with the clock signal reproduced by the above-described method to maintain clock synchronization. I do. Although the present embodiment has been described with reference to a π / 4 shift QPSK modulation signal as an example, the present invention is similarly applicable to other phase modulation methods such as QPSK.

As described above, according to the clock recovery circuit of the present invention, it is possible to perform the initial phase synchronization with a shorter redundant bit than the conventional one by estimating the clock phase at the initial phase synchronization. It is. Further, the clock initial phase estimation circuit enables stable clock phase initial synchronization regardless of the presence or absence of the carrier phase frequency error of the received signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment.

FIG. 2 is a block diagram of a conventional clock recovery circuit.

FIG. 3 is an explanatory diagram of a clock phase signal.

FIG. 4 is an explanatory diagram of an estimated clock phase.

FIG. 5 is a diagram illustrating a clock phase estimation error.

FIG. 6 is a diagram showing a phase estimation rule.

FIG. 7 is a diagram illustrating a phase estimation rule.

FIG. 8 is a diagram illustrating the operation of a conventional clock recovery circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Modulation signal phase detection circuit 20 1 symbol difference circuit 30 Switch 40 1 symbol difference circuit 50 Serial / parallel conversion 61, 62 Clock phase estimation integration circuit 70 Clock phase estimation circuit 80 Clock timing selection circuit 90 Zero cross detection type clock phase advance / delay Detection circuit 100 Digital filter 101 Filter stage variable digital filter 110 Frequency division ratio variable clock signal generator 120 Reference signal generator

──────────────────────────────────────────────────続 き Continuation of the front page (56) References IEICE Technical Report, RC S93-58 (58) Fields surveyed (Int.Cl. ⁶ , DB name) H04L 27/00-27/38 H04L 7 / 00 H04L 7/10

Claims (2)

(57) [Claims] 1. The phase component of a one-time differential signal is one symbol
Synchronous pre-aer, which alternately crosses the zero point and inverts the polarity every time
A modulation phase detection circuit that operates on a demodulation signal of a digital phase modulation signal and outputs a phase of a reception phase modulation signal, and calculates a difference between a signal delayed by one symbol period k (k ≧ 2) times
And k times the difference circuit to output force, said k times the clock phase estimation integrating circuit to obtain a signal used to clock phase estimation based on the difference circuit output, initial clock <br/> position phase than for the integrating circuit output said clock phase estimate the clock recovery circuit and a clock timing selection circuit for selecting a clock timing based on information. 2. The first difference calculation by the k-th difference circuit.
Performs zero-cross detection using the output
A zero cross detection type clock phase lead / lag detection circuit for detecting a leading or lagging phase, the zero-cross detection type clock phase lead / lag detection circuit
Signal indicating the clock correction direction based on the detection result by
Comprising a digital filter for outputting the items, the black
A clock timing selection circuit.
Clock phase information estimated by the
Clock signal based on the output signal of the digital filter.
The clock recovery circuit according to claim 1, wherein the clock recovery is selected .