JP2944412B2 - Data transfer method and data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method and a data transfer method, and more particularly to a synchronization method and a synchronization method for transferring a large amount of data in parallel.

[0002]

2. Description of the Related Art In a conventional data transfer system, when transferring a plurality of bits of information, a plurality of bits to be transferred on a single transmission line are used in order to increase the usage rate of the transmission line and reduce the cost. In general, a method of converting all data into serial data and transferring the data is performed. However, in a mainframe that needs to send a large amount of data at high speed, a method is used in which the transfer data is divided into a certain number of bits and transferred in parallel via a plurality of transmission paths.

[0003]

The above-mentioned conventional method of parallel transfer of large-capacity data has a problem in that the transmission delay in each transmission line depends on the performance variation of the driver that outputs to each transmission line on the transmission side. Due to the variation, when data is fetched on the receiving side, synchronization is not guaranteed with a uniform clock, so that various synchronization assurance circuits are required and the cost is increased.

[0004]

According to a first aspect of the present invention, in a data transfer method between frames or between devices, a plurality of transmission paths are provided, and a transmission side counts up a transfer request from a higher-level device and performs the transfer. When the requested transfer data is equally divided into the plurality of transmission paths and transferred as serial data together with the count-up information, the receiving side converts the serial data from the plurality of transmission paths into parallel data. Originally, only when the count-up information included in each of the parallel data coincides, the transfer data requested to be transferred is constituted from the divided transfer data included in each of the parallel data. And

In a second aspect of the present invention, in a data transfer method between frames or between devices, a predetermined data width n (n
Is a positive integer), a transfer data register for storing transfer data, a transfer counter for counting up the transfer request from the host device to the transfer data register and outputting the transfer request as transfer count information, The data width n of the transfer data stored in the data register is set to L (L
Is a positive integer, L ≦ n), and the L sending-side conversion modules that output each part of the n / L width as serial data together with the transfer count information of the transfer counter are prepared in advance. The L transmission paths, the L receiving conversion modules that receive the serial data from the L transmission paths and output the data as parallel data, and output from each of the L receiving conversion modules. A transfer number check circuit that outputs a predetermined signal only when all of the transfer number information in the parallel data match, and the parallel data output from each of the L receiving conversion modules. The data width for storing the transfer data having the n / L width only when the output of the transfer count check circuit is the predetermined signal is n. Only the side data register, characterized in that it comprises a retry request circuit requesting retransmission from the sender module in cases other than when the transfer count information matches all.

[0006]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the data transfer system of the present invention.

In FIG. 1, in the data transfer method of this embodiment, data to be transferred is temporarily stored in a sending data register 1 having an n-byte width (n is a positive integer), and then the data is transferred into L data registers. (L is a positive integer), and each is sent to the sending-side conversion module (3-1 to 3-L). Normally, the total transfer amount is n bytes × m times (m is a positive integer).

Assuming that L = 2, m = 1, and n = 2, the number of transfers is 1, so that the number-of-times-of-transfer counter 2 outputs "1" and the sending-side data register 1 stores 2 bytes of data. Each of the transmission-side conversion modules 3-1 and 3-2 receives 1-byte data and the output "1" from the transfer number counter 2.

[0010] Generally, when the basic data width n transfers m times, m ₁ (m ₁ ≦ m) times the feed side converter module in the transfer-th (3-1 to 3-L), the sender data register and n / L bytes of data from one, and sets the m ₁ is the output of the transfer counter 2. Here, it is assumed that the data of n / L bytes from the transmission side data register 1 and the information on the number of transfers, which is the output of the transfer number counter 2, are synchronized. Each sending-side conversion module (3-1 to 3-
L) is a set of n / L bytes of data and information m ₁ of the number of transfers, which is converted into serial data. If the transmission line 105 is an optical fiber, E → O conversion (conversion of an electric signal to an optical signal) After that, the data is output to the transmission path 105.

Receiving-side conversion module (4-1 to 4-L)
Input serial data from the transmission path 105,
After the O → E conversion, serial-parallel conversion is performed. Each of the receiving-side conversion modules (4-1 to 4-L) inputs information on the number of transfers from the serial-parallel converted data to the number-of-transfers check circuit 7.

The transfer number check circuit 7 sets GOOD when all the L transfer number information matches, and BAD when there is a mismatch among the L transfer number information.
As a predetermined signal, for example, GOOD = 1, B
AD = 0 is input to the AND circuit 6.

In the AND circuit 6, each data which has been serial-parallel converted by the L receiving-side conversion modules (4-1 to 4-L) is combined as one input, and data having a data width of n bytes is input. You. When the output of the transfer number check circuit 7 is GOOD, the n-byte data is stored in the receiving data register 5 having an n-byte width. When the output of the transfer count check circuit 7 is BAD, writing to the receiving data register 5 is suppressed, and a retry request is output to the transfer source by the retry request circuit 8.

The check by the transfer number check circuit 7 and the control of writing to the receiving side data register 5 are performed m times, which is the transfer number.

According to the above-mentioned method, a large amount of data can be efficiently transferred by using a plurality of serial transfers without performing complicated synchronization control.

FIG. 2A is a diagram for explaining the operation of the transfer counter 2 and the sending-side conversion modules (3-1 to 3-L). The transfer number counter 2 is connected to the REQ buffer and the AN.
Consists D gates and counters, as shown in the time chart of FIG. 2 (b), when receiving a transfer request signal from the application program (REQ signal) at T ₀ timing, the ON signal by the AND gates by T ₁ time Output, which resets the counter. Thereafter, the count is incremented every cycle.

On the other hand, the data of n-byte width is output m times from the transmission side data register 1 at each timing of T ₂ , T ₃ , T ₄ ,.
Each data n / L byte width is inputted together with the value of the counter at T ₃ and subsequent timings.

FIG. 3 is a diagram showing a general configuration of the transfer count check circuit 7, which transfers data from L receiving conversion modules each outputting N-bit transfer count information and n / L-bit data. N EXOR (exclusive or) circuits for inputting only the number of times information bit by bit,
AND output of inverted polarity from N EXOR circuits
And one AND circuit. And AND
When the output signal of the circuit is 1, it is determined that the number of transfers matches, and when it is 0, it is determined that the number of transfers does not match. However, in this embodiment, it is assumed that L is an even number, and when L is an odd number, the purpose can be similarly achieved with another circuit configuration.

FIG. 4 is a diagram for explaining the operation of suppressing writing to the data register 5 on the receiving side.

Each of the receiving side data registers 5 outputs N-bit transfer count information and n / L-bit data.
It comprises L registers each storing n / L bits of data from the receiving conversion modules. The receiving data register 5 captures data when the output of the transfer count check circuit 7 is "1" and the strobe signal which is a data capture control signal is ON. In other cases, data acquisition is prohibited.

[0021]

As described above, the present invention has an effect that it is possible to economically achieve a method of transferring a large amount of data in parallel through a plurality of transmission paths at high speed. ing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a data transfer method according to the present invention.

FIG. 2A is an explanatory diagram of an operation of a transfer number counter and a sending-side conversion module, and FIG. 2B is a time chart.

FIG. 3 is a diagram illustrating a general configuration of a transfer number check circuit according to the present embodiment.

FIG. 4 is a diagram illustrating an operation of suppressing writing to a receiving-side data register according to the embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sender-side data register 2 Transfer number counter 3-1 to 3-L Sending-side conversion module 4-1 to 4-L Receiving-side conversion module 5 Receiving-side data register 6 AND circuit 7 Transfer number check circuit 8 Retry Required circuit

Claims (2)

(57) [Claims] In a method of transferring data between frames or between devices, a plurality of transmission paths are provided, and a sending side counts up a transfer request from a higher-level device, and transfers the transfer data requested to be transferred to the plurality of transfer devices. It is divided equally into transmission lines and transferred as serial data together with the count-up information, and the receiving side converts the serial data from the plurality of transmission lines into parallel data and includes the parallel data in each of the parallel data. A transfer data requested by the transfer from the divided transfer data included in each of the parallel data only when all the pieces of the count-up information coincide with each other. 2. In a data transfer method between frames or between devices, a sender data register for storing transfer data having a predetermined data width n (n is a positive integer) in response to a transfer request from a higher-level device. A transfer number counter that counts up the transfer request from the higher-level device to the sending-side data register and outputs it as transfer number information, and sets the data width n of the transfer data stored in the sending-side data register to L. (L is a positive integer, L ≦
the L transmission-side conversion modules for outputting each part of the n / L width when divided by n) together with the transfer count information of the transfer counter as serial data; the L transmission lines prepared in advance; , The L receiving-side conversion modules for inputting the serial data from the L transmission paths and outputting the data as parallel data, and the transfer of the parallel data output from each of the L receiving-side conversion modules. A transfer number check circuit that outputs a predetermined signal only when all pieces of frequency information match, and the n / L width included in the parallel data output from each of the L receiving-side conversion modules. The data width to store the transfer data only when the output of the transfer number check circuit is the predetermined signal is n. Data and the data transfer method which comprises a retry request circuit the transfer count information requests retransmission from the sender module in cases other than those match.