JP2953918B2 - Arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit used for digital signal processing, and more particularly, to a plurality of input data, each of which is multiplied by a coefficient using a plurality of multipliers and adders, and each multiplication result is obtained. The present invention relates to improvement of an arithmetic unit for adding.

[0002]

2. Description of the Related Art Conventionally, in image processing, a filter is often used for the purpose of extracting an appropriate frequency component. In digital signal processing, this filter is realized by multiplying a given plurality of input data by an appropriate coefficient, and adding the multiplication results.

FIG. 2 is a block diagram showing a conventional arithmetic unit for realizing a filter. In the figure, reference numeral 51 denotes a data holding circuit, which stores input data 53 in synchronization with a clock signal 52 and outputs it to the data holding circuit 51 of the next stage. Therefore, the output of the i-th data holding circuit from the input data side is the data that is i clocks before the input data. 54 is a multiplier, and 55 is a register for holding a coefficient. In this example, seven data holding circuits 51, seven multipliers 54, and seven coefficient registers 55 are provided. Each multiplier 54 multiplies the data of the corresponding data holding circuit 51 by the coefficient stored in the coefficient register 55 and outputs a result. Reference numeral 56 denotes an adder, and a plurality of adders 5
7 are formed in a tree shape, the results output from the seven multipliers 54 are sequentially added, and the sum of the output results of the seven multipliers 54 is output.

Now, the values of the coefficients stored in the seven coefficient registers 55 are determined in the order of a (1), a (2), a (3), a (4) in order from the one farthest from the input data 53. , A (5), a
(6) and a (7), and the input data at time T is d (T)
And The input data 53 is sequentially transferred to the seven data holding circuits 51 in synchronization with the clock signal 52, and when d (T) reaches the seventh data holding circuit from the input data 53, that is, the farthest data holding circuit. , The sixth data holding circuit 51 holds data one clock after the time T, that is, d (T + 1). Similarly, the fifth data holding circuit 51 holds d (T + 2). Therefore, the output result out of the adder 56 is represented by (Equation 1).

[0005]

[Formula 1] out = a (1) * d (T) + a (2) * d (T + 1) + a (3) * d (T + 2) + a (4) * d (T + 3) + a ( 5) * d (T + 4) + a (6) * d (T + 5) + a (7) * d (T + 6) In this way, a filter is realized. Further, the characteristics of the filter can be designated by the value of the coefficient.

[0006] Such an arithmetic unit is applied not only to filters but also to various applications requiring a product-sum operation, such as matrix calculation.

Next, another conventional example disclosed in US Pat. No. 5,195,049 is shown in FIG. In the figure, reference numerals 1 ... denote a plurality of sum-of-products arithmetic units, each of which has a data holding circuit 2;
It has an adder 3, a multiplier 4, and a coefficient register 5.
In this example, seven product-sum operation devices 1 are connected in series. Data holding circuit 2 of each product-sum operation device 1
Is supplied with the output of the adder 3 of the immediately preceding product-sum operation unit, and is stored in synchronization with the clock signal 6. A value of 0 is given to the data holding circuit 2 of the first product-sum operation device 1. The inputs of the multipliers 4 of the respective product-sum operation devices 1 are as follows:
Input data 7 is commonly provided. The multiplier 4 of each multiply-accumulation device 1 stores the value of the input data 7 and the coefficient register 5
Is multiplied by the value held in the table, and the result of the multiplication is output. The adder 3 adds the data held in the data holding circuit 2 and the output of the multiplier 4 and outputs the addition result to the data holding circuit 2 of the product-sum operation device 1 at the next stage.

The operation of the arithmetic unit configured as described above will be described below with reference to FIG. The coefficients stored in the coefficient registers 5 of the seven sum-of-products arithmetic units 1 are referred to as a (1), a (2),. Now, let the value of the input data 7 at the time T be d (T). The first product-sum operation unit 1 from the foremost stage multiplies d (T) by a (1),
The multiplication result is added to 0 and output. One clock later, in synchronization with the clock signal 6, the second product-sum operation device 1 outputs the output of the preceding stage, that is, a (1) * d (T), to the data holding circuit 2
To be stored. At this time, the input data 7 is data one clock after the time T, that is, d (T + 1), and the second multiply-accumulate device 1 adds a coefficient a (2) to d (T + 1). The data is multiplied, added to the data a (1) * d (T) of the data holding circuit 2, and output to the data holding circuit 2 of the third product-sum operation device 1. Similarly, the value of the output out of the final stage, here the seventh product-sum operation device 1, is as shown in the above (Equation 1), and the same operation result as the conventional example is obtained.

[0009]

However, in the former former configuration described above, the configuration of the adder 57 for adding the results of the plurality of multipliers 54 becomes a tree-like configuration, and the result is passed through a plurality of stages of adders. Therefore, there is a disadvantage that the addition time limits the operating frequency. Further, there is a disadvantage that the number of stages of the adder increases according to the number of multipliers. Further, if the above addition process is to be processed in a pipeline manner,
Since a latch is required for the output of each adder, the circuit scale becomes large. In addition, since the adder has a tree-like configuration, it is difficult to arrange the adder as a semiconductor integrated circuit, resulting in an increase in area. Also, when trying to increase the number of multipliers,
Since the tree-like configuration of the adder is greatly changed, there is a problem that expandability is poor.

On the other hand, in the latter conventional configuration,
The disadvantage of the former conventional configuration can be eliminated. That is, since a plurality of product-sum calculation devices 1 having the same configuration are connected in series, they can be easily arranged as a semiconductor integrated circuit, and the area and the development period can be reduced.
It is easy to add and reduce the product-sum operation device. Furthermore, 1
Since one multiplication and one addition need only be processed within a clock, the operating frequency can be increased to increase the processing capability.

However, in the latter configuration, the number of adders 3 and multipliers 4 equal to the number of input data to be operated
And there is a problem that the arithmetic unit is correspondingly increased in size.

In view of the above problems, the present invention has
Since the multiplier is much larger than the adder, it is an object of the present invention to provide an arithmetic unit capable of performing the same operation as the conventional one while reducing the number of the multipliers to reduce the size.

[0013]

In order to solve the above problems, the present invention has focused on the following points. That is, in a filter used in image processing or the like, at the time of multiplication of each of a plurality of input data, attention is paid to the fact that there is a symmetric filter in which coefficients used for the multiplication are symmetric between predetermined two input data. This symmetrical filter has a configuration in which input data using the same coefficient are added first, and then the result of addition is multiplied by a coefficient, thereby halving the number of multipliers.

[0014] That is, in the first aspect of the present invention, a common first
1 input data and n connected in series with each other
Comprising a product-sum operation means number (n ≧ 2), wherein each of the product-sum operation unit, said first data holding means, and second data holding means, and the content of the second data holding means the First adding means for adding the first input data, multiplying means for multiplying the addition result of the first adding means by a coefficient, and storing the multiplication result of the multiplying means and the first data holding means. and a second adding means for adding the data, the first stage
In the product-sum operation means, the second data is input to the first data holding means.
Data is given et al is, a third input to the second data holding means
Given data, i-th (2 ≦ i ≦ n) stage product-sum operation
In the means, the product sum of the (i-1) th stage is stored in the first data holding means.
The output of the second adding means of the arithmetic means is given and the second data
Data holding means in the data storage means
Is provided .

[0015]

According to the above-mentioned structure, according to the first aspect of the present invention,
In each of the product-sum operation means, for the input data, input data using the same coefficient as the input data is stored in the second data holding means, and the stored data and the input data are compared with the first data. After the addition by the adder, the addition result is multiplied by a coefficient.

Therefore, each product-sum operation means only needs to have one multiplier. Furthermore, the product of plural (n)
The sum operation means can have the same internal configuration.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment for realizing a symmetric filter of an arithmetic unit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an arithmetic unit showing an embodiment of the present invention. In the figure, reference numerals 20... Denote a product-sum operation device, each of which is an adder 22 as a first addition means, an adder 21 as a second addition means, a multiplier 23 as a multiplication means, and a first data. It has a data holding circuit 24 as holding means, a data holding circuit 25 as second data holding means, and a coefficient register 26. In the present embodiment, n ( three in FIG. 1 ) product-sum operation devices 20 are connected in series, and the input data 32 is used as the first input data. Are given to each adder 22.

In each of the product-sum operation units 20,...
2 adds the input data 32 and the output 31 of the data holding circuit 25 and outputs the addition result to the multiplier 23. The multiplier 23 multiplies the addition result of the adder 22 by the coefficient held in the coefficient register 26, and outputs the multiplication result.
Output to The adder 21 adds the multiplication result of the multiplier 23 and the content of the data holding circuit 24 and outputs the result. The data holding circuit 25 is configured by connecting two latches 27 and 28 in series. Latches 27 and 28 store data in synchronization with clock signal 29. Therefore, the data holding circuit 25 holds two data of the current value and the previous value of the input data, and outputs the input data two clocks later.

Reference numeral 33 denotes a multiplier, and reference numeral 34 denotes a coefficient register. After the multiplier 33, the three product-sum operation units 20
... are connected in series. Input data (first input data
( 32 ) is also given to the multiplier 33 together with the adders 22 of the three sum-of-products arithmetic units 20.

[0021] In the product-sum calculation unit 20 at the first stage (first stage)
Is the input of the internal data holding circuit 24 thereof, the output of the multiplier 33 is supplied as the second data, therein
The input data (first input of the data holding circuit 25 of
Input data) 32 is given as the third input data .

Further, assuming that the integer i is a value of 2 ≦ i ≦ n,
In the product-sum operation device 20 at the i-th stage (i = 2),
The input of the data holding circuit 24 is connected to the ith
The output of the adder 21 of the product-sum operation unit 20 at the -1 (= 1) stage
And the input of the internal data holding circuit 25
Of the first-stage product-sum operation device 20 located at the preceding stage
An output 31 of the data holding circuit 25 is provided. Similarly,
In the i-th (i = 3 = n) stage product-sum operation unit 20,
The input of the internal data holding circuit 24 is
Adder 2 of the i-1 (= 2) -th stage product-sum operation unit 20
1 of the data holding circuit 25
A second-stage product-sum operation device 2 located at the preceding stage as an input
The output 31 of the 0 data holding circuit 25 is provided.

The operation of the arithmetic unit configured as described above will be described below. As a symmetric filter, the coefficients a (1) = a (7) and a (2) =
Consider the case where a (6) and a (3) = a (5).

[0024] First, the value held in the coefficient register 34 a (4), first stage, second stage, held in the coefficient register 26 of the third stage of the product-sum calculation unit 20 has a value Is a
(3), a (2) and a (1).

After time T, data d (T)
, D (T + 1), d (T + 2),... Now, three clocks after the time T, the input data 32 is given data of d (T + 3), and the data holding circuit 25 of the first- stage multiply-accumulate operation device 20 outputs the input data d two clocks before. (T + 1) is output. The multiplier 33 multiplies the input data d (T + 3) by the content a (4) of the coefficient register 34.

At the next clock, the data holding circuit 24 of the first- stage product-sum operation unit 20 outputs the result of the multiplier 31, that is, a
(4) * d (T + 3) is stored, and the data holding circuit 25 stores d (T + 3).
2) is output. At this time, the input data 32 includes data d
(T + 4) is given, and the adder 22 of the product-sum calculator 20 in the first stage adds d (T + 4) and d (T + 2), and the multiplier 2
3 is the addition result of the adder 22 and the coefficient a of the coefficient register 26.
The adder 21 adds the result of the multiplication by the multiplier 23 and the content of the data holding circuit 24 and outputs the result to the data holding circuit 24 of the product-sum operation device 20 in the second stage .

At the next clock, d (T + 5) is given to the input data 32, and the output of the data holding circuit 25 of the second- stage product-sum operation unit 20 is d (T + 1). , Adder 2
2 adds d (T + 1) and d (T + 5), the multiplier 23 multiplies the result of addition by the coefficient a (2) of the coefficient register 24, and outputs the result of the multiplication in the first stage . The result is added to the addition result of the product-sum operation unit 20 and output to the product-sum operation unit 20 at the third stage .

In the same manner as described above, the output out of the adder 21 of the third- stage product-sum operation unit 20 outputs data represented by (Equation 3).

[0029]

(Equation 3) As described above, the arithmetic device of this embodiment can realize a symmetric filter.

Therefore, in this embodiment, three product-sum operation devices are used.
Since the devices 20 have the same configuration and the product-sum operation devices 20 having the same configuration are connected in series, the arrangement is easy as a semiconductor integrated circuit, and the area and the development period can be reduced. As well as the sum-of-products arithmetic unit 20 ...
Is easy to add and reduce. Further, since one multiplication and one addition need only be processed in one clock, the operating frequency can be increased and the processing capability can be increased.

Moreover, even if the arithmetic unit multiplies each of the seven input data by a coefficient and adds the result of each multiplication, it is sufficient to provide four multipliers 23... The number of multipliers can be reduced by three as compared with the case where seven multipliers are provided.

In this embodiment, three product-sum operation devices 2
.. And one multiplier 33, the operation on the seven input data is realized.
If the number is increased to 5, 5,..., It is needless to say that the operation can be performed on 9, 11,.

When the number of input data to be operated is even, the multiplier 33 and the coefficient register 34 are not provided.
To the data holding circuit 24 of the first- stage product-sum operation device 20, 0 is given instead of the result of the multiplier 33, and the latch in the data holding circuit 25 of the first- stage product-sum operation device 20 is reset. By using only one, the same operation as in the above embodiment can be realized.

Further, the adder 21 of each of the product-sum operation units 20...
Is replaced by a carry save adder, the partial sum, the partial carry and the result of the multiplication by the multiplier 23 are added, and the two outputs of the final stage carry save adder, that is, the partial sum and the partial carry May be separately provided. In this case, there is no carry propagation, so that the operation speed is high and the circuit scale can be extremely reduced.

In addition, when the coefficient is a power of 2, such as 2, 4, 8, etc., each of the multipliers 23 may be constituted by a shifter.

Further, each of the multipliers 23 may be configured to have a storage device for holding the result of the multiplication.

Further, in the present embodiment, the coefficients of each multiplication are held in each coefficient register 26..., But are provided to the multiplier via a signal line from outside the arithmetic unit without the coefficient register, or May be configured by a multiplier for multiplying by a specific coefficient.

In addition, in this embodiment, both addition and multiplication processing in each of the product-sum operation units 20 are performed in one clock, but a latch is provided at an appropriate position in each of the product-sum operation units 20. By providing and performing pipeline processing, the processing amount of one clock can be reduced and the clock frequency can be increased.

Also, an appropriate limiter function is provided for each of the adders 21... When the value of the result is out of the set range.
A configuration may be adopted in which the output is replaced with an appropriate value.

[0040]

As described above, according to the arithmetic unit of the present invention, the common first input data is provided, and n (n.gtoreq.2) product-sum operation means connected in series to each other are provided. wherein the respective product-sum operation means includes first data holding means,
Multiplies the second data holding means, a first adding means for adding the contents of the first input data of said second data holding means, the addition result and the coefficient of the first addition means a multiplying means, and a second adding means for adding the data stored in the multiplication result to the first data holding means of said multiplying means, in the first stage of the product-sum operation unit, the first data
The second input data is provided to the holding means, and the second data
The third input data is given to the holding means, and the ith (2 ≦ i)
.Ltoreq.n) the first data holding means
The output of the second adding means of the (i-1) th product-sum calculating means.
Is given to the second data holding means, and
Given the output of the second data holding means of the multiply-accumulate means of
Since the input data using the same coefficient are added to each other and then multiplied by the coefficient, the product-sum operation means of the same configuration is used while using less multipliers than the number of input data.
Are connected in series, are easy to arrange as a semiconductor integrated circuit, and have different numbers of input data.
The sum-of-products operator of the same configuration
It is possible to provide an arithmetic unit that can easily cope with the adjustment of the number of stages, has high expandability, and can perform high-speed processing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an arithmetic unit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a conventional arithmetic device.

FIG. 3 is a block diagram showing another conventional arithmetic unit.

[Explanation of symbols]

Reference Signs List 20 product-sum operation means 24 data holding circuit (first data holding circuit) 25 data holding circuit (second data holding circuit) 21 adder (second adding means) 22 adder (first adding means) 23 Multipliers (multiplication means) 26, 34 Coefficient register 29 Clock signal 32 Input data

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-59-127171 (JP, A) JP-A-60-119116 (JP, A) JP-A-1-126819 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) G06F 17/10 JICST file (JOIS)

Claims (5)

(57) [Claims] 1. A given common first input data, provided with a product-sum operation means n (n ≧ 2) which are connected in series with each other, the respective product-sum operation unit, a first data holding means, and second data holding means, a first adding means for adding the contents of the first input data of said second data holding means, and the addition result and the coefficient of the first addition means multiplication means for multiplying, and a second adding means for adding the data stored in the multiplication result to the first data holding means of said multiplying means, in the first stage of the product-sum operation unit, first Data retention means
The second input data is provided, and the second data
The third input data is provided, and the product-sum operation means of the i-th (2 ≦ i ≦ n) stage outputs the first data.
The second addition of the product-sum operation means of the (i-1) th stage to the data holding means.
The output of the arithmetic means is given and the second data holding means
Of the second data holding means of the product-sum operation means of the (i-1) th stage
An arithmetic unit characterized by receiving an output . 2. The arithmetic unit according to claim 1, wherein the coefficient used in the multiplying means is stored in a register. 3. The method according to claim 2, wherein the first input data is the third input data.
Together provided to the first stage of the product-sum operation manual stage as over data, multiplies the second register for storing the coefficients, and a coefficient of said first input data and the second register, the multiplication result arithmetic unit according to claim 1 or claim 2, wherein further comprising a second multiplying means for outputting to the first stage of the product-sum operation manual stage as the second input data. A second data holding means for inputting data;
3. The arithmetic unit according to claim 1, wherein two data of a current value and a previous value of the data are held. 5. The arithmetic unit according to claim 1, wherein at least one of the adding means of the product-sum calculating means comprises a carry save adder.