JP2954006B2 - Emulation device and emulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an in-circuit emulator and an emulation method thereof, and more particularly to an interrupt processing method using an ALT.

[0002]

2. Description of the Related Art A description will be given of a process performed by temporarily suspending the processing of a main program or a user program as a premise for explaining the conventional technology. For example, JP
As shown in Japanese Patent Application Laid-Open No. 0-238946, there are cases where the processing is shifted from the main program in order to obtain information for debugging. This will be described with reference to FIGS.

FIG. 5 is a block diagram showing a conventional memory dump process using an interrupt. Processing units A to C (508
In A to C), a process to be debugged is identified by a process ID (51).
0A-C). In this case, a method of displaying information for debugging is called a snapshot dump (hereinafter, referred to as snap).

When the process is shifted to the snap by the trace instructions 509A to 509C from the processing units A to C (508A to 508C), first, the state of the debug switch A 506A is read to determine whether the snap can be actually performed (60).
1). If the switch A is ON, the status of the debug switch B (506B) is read next, and the snap type process ID (510A to C) is set in advance.
It is determined whether the snap processing needs to be distinguished (602). Here, if the switch B is ON, it is determined whether the process IDs match (603), and if they match, a dump (screen display) (604) is performed. Next, the state of the debugging switch C (506C) is read, and it is determined whether to shift the processing to debugging after completion of the dump or to return to the main program (605). In this case, the switch state is determined four times only by the snap processing alone.

As described in Japanese Patent Application Laid-Open No. 4-262429, there is a case where processing is performed by an ALT program.
This case will be described with reference to FIGS. FIG. 7 is a block diagram showing a conventional interrupt process using a monitor. In this case, it is called an emulation monitor (hereinafter referred to as a monitor) instead of the ALT. To shift the processing to the monitor, it is necessary to interrupt the emulation CPU to temporarily suspend the user program, and to perform the monitor processing in the interrupt processing. As a result, a monitor introduction 801 for transferring control to the monitor stored in the emulation monitor storage memory 717 is performed. In the process after the introduction of the monitor, a command packet from the supervisor CPU 701 is read (802). By performing command analysis (803) from the read command packet, it is determined which processing is to be performed. Next, it is assigned to register bank switching (804), register writing / reading (805), and memory writing / reading (806) corresponding to the analyzed command.

Although the interrupt processing is omitted in this conventional technique, performing the interrupt processing uses the common resources of the emulation CPU, so that the register group must be saved. Further, in a process having versatility such as performing a command analysis and distributing a process, much information must be saved.

FIG. 9 shows a conventional interrupt processing using an ALT similar to the above-mentioned Japanese Patent Application Laid-Open No. 4-262429.
This will be described with reference to FIG. Here, the host program executed on the supervisor CPU and the emulation CPU
The processing of the user program and the ALT program executed above is described. ALT from user program by interrupt (902) from host program
Processing shifts to the program. Next, in the ALT program, the register data is saved (904), and the command data (91) received in the command transmission (903) from the host program is sent.
0) is analyzed (905). Next, a memory write process (906) or a memory read process (907) is performed by a command. After the processing is completed, the register is restored (90
8) and return to interrupt (909), and shift to the user program. Even in this case, the processing takes time because of the evacuation and the command analysis as in the related art.

[0008]

However, as described in the above-mentioned prior art, the number of steps is increased because a large number of switch state determinations are made. In addition, when the command analysis is performed and the process of allocating the process is performed, there is a problem that the information that must be saved increases and the number of steps further increases.

The reason why these problems are caused occurs when the conventional technology is used in a system in which a problem occurs if the operation is stopped for a certain period of time or longer. Since these processes account for a large proportion of the ALT process, the process in which the ALT is performed does not end in a short time. That is, although the interruption time must end at a time corresponding to the above-described system, the time of the ALT processing for determination and evacuation becomes long. If the processing is not completed within this time, the above-mentioned system will be in a state where complete control cannot be performed, which may lead to destruction of the system. This is a phenomenon that occurs because control cannot be performed normally in a system in which a problem occurs if emulation is stopped for a certain period of time or more, and particularly occurs in a motor control system.

An object of the present invention is to provide an emulation apparatus and an emulation method which solve such a problem, shorten the ALT processing time, and reduce the emulation interruption time.

[0011]

According to the present invention, there is provided an emulation CPU for executing an alternate (ALT) program for controlling an interface between a user program to be inspected and a host program.
And a supervisor CPU for executing the host program
When the interrupt vector setting means for setting the interrupt vector by the said prior from the host program to an interrupt process to the user program host program, the split
Memory specified by the host program prior to
Alternate (ALT) memory for storing instructions in the area
Wherein the interrupt vector setting means performs interrupt processing.
Prior to this, the ALT memory is stored in the ALT memory by the host program.
A memory write instruction is stored .

In the present invention, interrupt vector setting means
However, before the interrupt processing, the host program
In the ALT memory, a memory is used instead of the memory write instruction.
A read command can be stored .

[0013]

According to another aspect of the present invention, there is provided a first step of making an interrupt request by a host program, a second step of stopping the user program in response to the interrupt request, and executing an ALT command from the host program.
In a third have line interrupt processing by the steps, the emulation process and a fourth step of setting the interrupt vector prior to the interrupt processing executed by the program, the performing reception memory write command 5
And a specific memory by the host program.
No. of storing the memory write instruction in the ALT memory of the area
Step 6 and change and hold of the interrupt vector
Performing an ALT process including a seventh step to be performed .

[0015] In the emulation method of the present invention,
In the sixth step, instead of the memory write instruction,
A memory read instruction can also be stored .

According to the emulation method of the present invention,
Since the determination in the ALT program and the command analysis of the prior art are omitted, a process for preparing a specific function instruction group is provided in the ALT memory in advance, and this process is performed for a specific area in the ALT memory. Can be reduced in time required.

Preparing the instruction group for the specific function eliminates the need to perform judgment and command analysis as ALT processing, which leads to reduction of register save and omission of processing such as command analysis. Shortening becomes possible. However, it is not absolutely necessary to save the registers. For example, in the case of a memory write, the number of registers necessary for the memory write process is saved.
Also, in order to shorten the ALT processing, only the minimum necessary combination of instructions is used for a 1-byte write instruction to the memory, so that the ALT processing time is shortened and the emulation interruption time can be reduced. it can.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In this configuration, two processes are mainly performed in this configuration. One is that the host program 104 in the supervisor CPU 101 executes the instruction writing process 109 to execute the ALT in the ALT memory 102.
This is a process of writing necessary instructions to the program 105 memory write. Another is the host program 104
The interrupt control unit 107 receives the interrupt instruction 114 from the CPU and outputs an interrupt to the emulation CPU 103.
5. As a result, the control shifts from the user program 106 to the ALT program 105 (11
1).

The memory write instruction written in the above process is executed to write data to the emulation memory 108 (110), and control is returned to the user program (11).
2). Here, the host program 104 checks the user program execution state 113 output from the emulation CPU 103. In this process, the host program 104 recognizes that control has been transferred from the ALT program 105 to the user program 106.

Next, the operation of this embodiment will be described with reference to the flowchart of FIG. Host program 201
First, the number of bytes to be written and the data to be written are received by the memory write command 202. Then AL
A memory write instruction is written 203 to the T processing unit. Here, ALT is stored in a specific memory area of the ALT processing unit in advance.
Register write 211, memory write 212, register restore 2 related to memory write that must be processed
13. Write each instruction of the interrupt return 214. Next, the interrupt vector is changed so that the location to which the processing shifts when an interrupt occurs is the specific memory area written in the above-described procedure (204). Also, the vector before the change is held.

Since the interrupt vector to be changed is an address indicating a specific memory area, it is described in advance in the host program as data. Next, an interrupt is generated (205). Here, A from the user program
The processing is shifted to LT, and the emulation is temporarily suspended. In the ALT process 210, the instruction of the register save 211 written in advance and the memory write 21
2, the instruction of register return 213, and the instruction of interrupt return 214 are executed. Here, judgment and command analysis as in the prior art are not performed,
The T processing has been shortened. Further, the processing returns from the ALT processing 210 to the user program by the interrupt return 214. At this time, the host program accepts the ALT processing end 215 and restarts the host program processing.

Thereafter, an interval is provided until the next interrupt is generated (206). This is a process of inserting a wait for a specific time in order to adjust the time until the emulation is interrupted due to the interruption and the interruption is again entered. Next, a memory byte number check 207 is performed to determine whether to continue the memory write by the ALT process 210.
Here, the received number of bytes to be written is decremented. If there is a remaining number of bytes to be written, the ALT process 210 is again performed by the interrupt, and if there is no remaining, the next process is performed. When the memory write process is completed, the interrupt vector is returned (208). The memory write ends (209) through the above flow.

Next, another embodiment of the present invention will be described in detail with reference to the block diagram of FIG. 3 and the flowchart of FIG. FIG. 3 shows a configuration obtained by modifying FIG. 1. In this configuration, three processes are mainly performed in the modified example. One is that the host program 104 in the supervisor CPU 101 executes the instruction writing processing 109 to execute the ALT memory 10.
This is a process for writing an instruction necessary for memory read into the ALT program 105 in the second program.

The other is that the interrupt controller 10 receives an interrupt instruction 113 output from the host program 104.
7 is an interrupt output to the emulation CPU 103
14 As a result, the process is shifted from the control user program 106 to the ALT program 105 (110). The memory read written in the above process is executed to read data from the emulation memory 108 into the buffer 121 of the ALT memory, and control is returned to the user program 106 (112). Here, the host program 104 checks the user program execution state 113 output from the emulation CPU 103. In this process, the host program 104 recognizes that control has been transferred from the ALT program 105 to the user program 106. The other is a process 122 for reading the contents of the buffer of the ALT into the host program 104.

Next, the operation of this embodiment will be described with reference to FIG. The host program processing unit 201 receives the number of bytes to be read by the memory read command 202. Next, a memory read instruction is written to the ALT processing unit.
Perform 3A. Here, a register save 211 and a memory read 2 related to a memory read that must be processed by the ALT in advance in a specific memory area of the ALT processing unit.
Instructions of 12A, register return 213, and interrupt return 214 are written in advance. Next, the interrupt vector is changed so that the location to which the processing shifts when an interrupt occurs is the specific memory area written in the above procedure (204). Also, the vector before the change is retained. Since the interrupt vector to be changed is an address indicating a specific memory area, it is described in advance as data in the host program.

Next, an interrupt is generated (205). Here, the processing is shifted from the user program to the ALT, and the emulation is temporarily suspended. In the ALT process 210, a pre-written instruction for register save 211, an instruction for memory read 212A, an instruction for register return 213, and an instruction for interrupt return 214 are executed.
Here, the ALT processing is shortened because the judgment and the command analysis as in the related art are not performed. The process returns from the ALT process 210 to the user program due to the return from the interrupt. At this time, the host program receives the ALT processing end 215 and restarts the host program processing. In this memory read process, the read contents are written in the buffer of the ALT.

Thereafter, an interval is provided until the next interrupt is generated (206). This is a process of inserting a wait for a specific time in order to adjust the time until the emulation is interrupted due to the interruption and the interruption is again entered. Then A
A memory byte number check 207 is performed to determine whether to continue the memory read by the LT process 210. Here, the number of bytes to be read received is decremented.
Is performed, and if there is no remaining, the next processing is performed. When the memory read processing is completed, the interrupt vector is returned (208). Next, the read contents are read (208A). At this time AL
The data written to the buffer in the area where T is located is read. Through the above flow, the memory read ends 209.

[0028]

As described above, according to the present invention, A
An emulation interruption time can be reduced by shortening the steps that must be performed in the LT processing. This is applicable to a user via an application that cannot be controlled if the interruption time due to the ALT processing for the user program is long when the ALT processing is performed using the interrupt during the execution of the user program.

In particular, in the development of servo-related applications, the system controls the system at a severe timing by a program. Therefore, a long interruption by a user program interrupt will hinder system control. For example, in the case of a motor control system, there is a possibility that the motor is burned. However, if the present invention is applied here, the interrupt processing can be performed without being aware of the emulation interruption time.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment explaining an emulation method of the present invention.

FIG. 2 is a flowchart illustrating the operation of FIG.

FIG. 3 is a block diagram of another embodiment of the present invention.

FIG. 4 is a flowchart illustrating the operation of FIG. 3;

FIG. 5 is a block diagram showing a conventional memory dump process using an interrupt.

FIG. 6 is a flowchart illustrating a memory dump process of FIG. 5;

FIG. 7 is a block diagram showing an interrupt process using a conventional monitor.

FIG. 8 is a flowchart illustrating the operation of FIG. 7;

FIG. 9 is a flowchart showing a conventional interrupt process using ALT.

[Explanation of symbols]

101, 701 Supervisor CPU 102, 702 ALT memory 103 Emulation CPU 104 Host program 105 ALT program 106 User program 107 Interrupt control unit 108, 710 Emulation memory 109 Instruction writing processing 110 Data writing 111 Processing transition (ALT processing from user program) 112 Processing Transition (from ALT processing to user program) 113 User program executing state 114 Interrupt instruction 115 Interrupt output 121 Buffer 122 Data reading 201 Host program processing unit 202 Emory write command 203 Write memory write instruction to ALT processing unit 204 Change and hold write vector 205 Interrupt generation 206 Interrupt interval 207 Memory byte number check 208 Interrupt Vector return 208A Read contents read 209 Memory write end 210 ALT processing 211 Register save 212 Memory write 212A Memory read 213 Register return 214 Interrupt return 215 ALT processing end 501 Main processor 502 Control unit 503 Display 504 KB (keyboard) 505 Printer 506A ＣC Debugging SW-AＣC 507 Debug target section 508AＡC Processing section A〜C 509A〜C Trace instruction (processing section A〜C) 510A〜C Processing ID (processing section A〜C) 511 Switch state check Unit 512 Dump processing unit 513 Debugger processing unit 514 Debugger 601, SW-A, B 603 Process ID 604 Dump (screen display) 605 SW-C 703 Supervisor emulation CPU shared memory 7 4 DMA transfer buffer memory 705 DMA transfer control circuit 706 DMA status information line 707 DMA transfer control program storage memory 708 Emulation CPU data bus 709 Emulation CPU address bus 711 Target bus interface 712 Target probe 713 Target memory 714 Supervisor data bus 715 Supervisor address bus 716 DMA transfer information line 717 Emulation monitor storage memory 801 Monitor introduction 802 Interrupt processing 803 Command analysis 804 Register bank switching 805 Register writing / reading 806 Memory writing / reading 807 Processing 808 Monitor exit 901 Memory write command acceptance 902 Interrupt generation 903 Command sending 904 Register saving 905 Command analysis 906 Memory write processing 907 Memory read processing 908 Register return 909 Interrupt return 910 Command data

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 11/22-11/34

Claims (4)

(57) [Claims] And emulation CPU for executing the alternate (hereinafter referred ALT) program for controlling the interface of the user program and the host program as claimed in claim 1 is an object to be inspected, and Supabaiza CPU for executing the host program, the from the host program and interrupt vector setting means for setting the interrupt vector by the host program before the interrupt processing to the user program, the host program before the interrupt processing
Alternate to store instructions in a specific memory area by a program
(ALT) memory, the interrupt vector setting means
Stage is preceded by the host program prior to interrupt processing.
The memory write instruction is stored in the ALT memory.
Emulation and wherein the a. Wherein said interrupt vector setting means, the ALT memory by the host program before the interrupt processing, the memory write instruction emulation device according to claim 1 which is adapted to store memory read instruction instead of. 3. A first step of making an interrupt request by a host program, a second step of stopping the user program in response to the interrupt request, and a third step of executing a command from the host program by an ALT program. There line interrupt processing by the steps, in the emulation process and a fourth step of setting the interrupt vector prior to the interrupt <br/> untreated, scaled
A fifth step of accepting a write command,
ALT memory in a specific memory area
A sixth step of storing a memory write instruction;
And the seventh step of changing and holding the
An emulation method comprising performing ALT processing . 4. The method according to claim 1, wherein the sixth step is a step of
Instead of bets instruction, claim 3 for storing memory read command
The emulation method described.