JP2964989B2 - Printed circuit board design system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a printed circuit board design system.

[0002]

2. Description of the Related Art Devices such as information processing equipment have built-in electronic circuits for achieving desired performance. An electronic circuit formed on a flat substrate is a printed circuit board. In the design of a printed circuit board, component placement based on circuit design information and pattern wiring design for connecting the placed components are performed.

FIG. 9 is a flowchart showing a design flow of a pattern wiring. Referring to FIG. 9, a pattern wiring design 901 is performed between parts where connection is desired and an arbitrary wiring length. If it cannot be connected in a straight line due to the arrangement of parts, bend it at an appropriate place. In the case of a multilayer substrate, when connecting between different layers, wiring is performed using connection vias.

When a printed circuit board is installed in an apparatus and is in an operating state, a signal current flows through a wiring pattern of the printed circuit board, and this signal current generates electromagnetic noise. The radiation level limit of the electromagnetic noise is specified as the operating condition of the device, and the electromagnetic noise must be suppressed to a specified value or less.

[0005] The electromagnetic noise generated from the wiring pattern is
It depends on the pattern wiring length.

The signal wiring pattern includes a component mounting pattern, a bent portion, a discontinuous portion such as a via, and the like. The wiring length between the discontinuous points is １ ／
Electromagnetic noise tends to increase at frequencies that are wavelengths.

As an automatic wiring method for automatically performing wiring at a CAD level so as to reduce radiation noise radiated from wiring on a wiring board, reference is made to, for example, the description of Japanese Patent Application Laid-Open No. 5-67176.

[0008]

When the operating signal frequency of the device and its harmonic frequency coincide with the half-wavelength frequency of the wiring length, the electromagnetic noise increases and becomes a value equal to or higher than the specified electromagnetic noise. And the operating conditions of the apparatus are not satisfied.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a printed circuit that suppresses radiation of electromagnetic noise depending on a pattern wiring length in a printed circuit board incorporated in an apparatus. An object of the present invention is to provide a printed circuit board design system capable of providing a board.

[0010]

In order to achieve the above object, the present invention relates to a wiring design system for a printed circuit board, wherein the wiring length of a wired pattern is set to 1 / (the operating signal frequency of the device and its harmonic frequency). It is characterized by having a means for checking that it does not match the two wavelength length.

Further, according to the present invention, the wiring length of the wiring pattern, the operating signal frequency of the device and 1 / (harmonic frequency thereof) are used.
A means for calculating an optimum wiring length that does not match the two wavelength lengths is provided.

[0012]

Embodiments of the present invention will be described below. In a preferred embodiment of the present invention, after designing a pattern wiring on a printed circuit board, a step of obtaining a wavelength shortening rate from the dielectric constant and the wiring impedance of the printed circuit board (201 to 20 in FIG. 2).
3) inputting clock frequency information, obtaining a harmonic frequency in a specified frequency range of electromagnetic noise, and calculating a half wavelength from the wavelength shortening ratio (204 to 2 in FIG. 2).
07), the wiring length is checked so that the wiring length of the wiring pattern does not match the half-wave length of the operation signal frequency of the device and its harmonic frequency. is there.

In the embodiment of the present invention, a step of detecting a clock pattern portion from the pattern wiring design result (208 in FIG. 2) and a step of detecting a discontinuous portion in the detected pattern (FIG. 2). 2 209),
Step of detecting a wiring length between discontinuous portions (21 in FIG. 2)
0), the 波長 wavelength calculation result information is compared with the wiring length detection information between discontinuous portions (211 in FIG. 2), and the clock frequency and 波長 wavelength of its harmonics and the clock of the printed circuit board are compared. If the pattern lengths match, alarm information is output (212 in FIG. 2).

In the embodiment of the present invention, each of the above steps is realized by a program executed on a computer.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to describe the above-mentioned embodiment of the present invention in more detail, an embodiment of the present invention will be described below.

FIG. 1 is a flowchart showing an outline of a processing flow of an embodiment of the present invention. In FIG. 1 showing the flow of designing a printed circuit board, after performing pattern wiring design (step 1), a wiring length check for judging the quality of the wired wiring length is performed (step 2).

FIG. 2 is a flowchart showing a processing flow of a wiring length check step in one embodiment of the present invention.

Referring to FIG. 2, information on the dielectric constant and wiring impedance of a printed circuit board to be used is input (step 201). A pattern width-dielectric thickness ratio calculation is performed from the dielectric constant and the wiring impedance (step 202).

FIG. 3 is a diagram showing a cross section of the printed circuit board. In FIG. 3, the printed circuit board 301 is H
Having a dielectric thickness of 302 and a dielectric constant of εr. The wiring pattern 304 must have a certain impedance in order to electrically match with the components to be connected.
From the desired impedance, the printed circuit board 301
From the dielectric thickness H302 and the substrate dielectric constant εr303, the ratio W / H of the pattern width 305 and the dielectric thickness H302 can be obtained.

From the obtained pattern width-dielectric thickness ratio W / H, the wavelength shortening rate is calculated again with reference to FIG. 2 to obtain the wavelength shortening rate (step 203).

On the other hand, clock frequency information is input as an operation signal of the apparatus (step 204).

A harmonic frequency calculation for obtaining a clock frequency harmonic in a specified frequency band of electromagnetic noise is performed (step 205).

Further, the wavelengths of all the obtained frequencies are calculated (step 206).

Using the wavelength shortening rate calculation result obtained in step 203, a half wavelength calculation on the printed circuit board is performed (step 207).

Based on the input of the design information and the result of the calculation, all the half wavelength lengths that can be considered as factors causing an increase in the electromagnetic noise are calculated from the operating frequency of the device.

Further, based on the result of the pattern wiring design 1 shown in FIG. 1, a clock pattern portion is detected in the processing flow shown in FIG. 2 (step 208).

FIG. 4 is a plan view showing an example of mounting a printed circuit board. In FIG. 4, the printed circuit board 4
There are a component A 402 and a component B 403 mounted on the device 01. The component A 402 and the component B 403 have connection terminals 404 and 405, respectively, and the terminals are wired and connected by a clock pattern 406. This clock pattern is detected.

Referring again to FIG. 2, a discontinuous portion is detected in the detected pattern (step 209). As a discontinuous portion, a via for signal layer connection on a multilayer substrate, a bent portion of a clock pattern, and a component mounting pattern portion are detected.

FIG. 5 is a diagram showing an example of mounting a printed circuit board. FIG. 6 is a diagram showing a side cross section of the printed circuit board shown in FIG. Referring to FIGS. 5 and 6, component A 502, component B 503, and component C 504 are mounted on printed circuit board 501. The component A has a terminal 505 and the component B has a terminal 506, and the wiring between them must be connected and connected by a clock pattern.

However, since the component C504 is mounted between the component A502 and the component B503, the shortest wiring on the component mounting surface cannot be performed.

Therefore, vias 507 and 508 for interlayer connection are used as clock pattern wiring bypassing component C 504.
Is conceivable. The clock pattern 509 from the terminal 505 is connected to the via 507. Via 507
Clock pattern 5 different from the component mounting surface
10 is connected. The via 508 and the terminal 506 are connected again by the clock pattern 511 on the component mounting surface. By these wirings, the component A502 and the component B5
03 clock pattern wiring can be realized.

Referring again to FIG. 2, the discontinuous portion via in the discontinuous portion detection processing (step 209) corresponds to connection vias 507 and 508 in FIGS.

FIG. 7 is a plan view showing an example of mounting a printed circuit board. 7, the printed circuit board 7
01, component A 702, component B 703, component C 704
And a component D705 are mounted.

The terminal 706 of the component A 702 and the component B 703
Must be wired and connected in a clock pattern. Due to the component C704 and the component D705, the clock pattern cannot be routed in the shortest, and the component C7
04 and the component D705 must be bypassed.

Clock pattern 708 from terminal 706
Changes the wiring route at the bend 709. The changed clock pattern 710 changes the wiring route again at the bend 711. Clock pattern 71 changed again
2 is connected to terminal 707. With these wiring methods, clock pattern wiring and connection between the component A 702 and the component B 703 can be realized.

Referring again to FIG. 2, the bending of the discontinuous portion in the discontinuous portion detection processing (step 209) is shown in FIG.
, Correspond to the bends 709 and 711.

Next, the wiring length between the detected discontinuities is detected (step 210). A clock wiring length that maintains the same wiring impedance of the pattern wiring between discontinuous locations of vias and bends is determined.

The wiring length between discontinuities in FIGS. 5 and 6 is the length of the clock patterns 509, 510 and 511. The wiring length between discontinuities in FIG. 7 is the length of the clock patterns 708, 710, and 712.

The half-wavelength calculation result information in step 207 is compared with the wiring length detection information between discontinuous portions in step 210 (step 211). If the clock frequency and the half wavelength of its harmonics match the clock pattern length of the printed circuit board, alarm information is output (step 212).

Referring again to FIG. 1, wiring length check 2
If the alarm information is output in step, the wiring length is determined to be inappropriate and the pattern wiring design is performed again.

Next, a second embodiment of the present invention will be described.
FIG. 8 is a flowchart showing a processing flow of the printed circuit board design system according to the second embodiment of the present invention. Referring to FIG. 8, the pattern wiring of the printed circuit board is designed (step 801), and the wiring length of the designed pattern is checked (step 802). As a result of the check, alarm information is output. If the result is "NO", the optimum wiring length is calculated (step 803). This is to calculate the wiring length of the clock pattern that does not match the clock frequency of the design apparatus and a half wavelength of its harmonic frequency. Based on the result of the calculation of the optimum wiring length, it is possible to redesign the pattern wiring that can reduce the radiation noise.

[0042]

As described above, according to the present invention,
By using the printed circuit board wiring design system, the radiation of electromagnetic noise depending on the pattern wiring length is suppressed, and the electromagnetic noise is reduced from the printed circuit board designed by the prior art printed circuit board design system incorporated in the device. Thus, it is possible to provide a printed circuit board in which is suppressed.

Therefore, according to the present invention, even a printed circuit board designer who does not have knowledge of the mechanism of electromagnetic noise emission can design a printed circuit board with reduced electromagnetic noise emission. It enables the construction as a type printed circuit design system.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a design flow of a printed circuit board according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing flow of wiring length check in one embodiment of the present invention.

FIG. 3 is a sectional view of a printed circuit board for explaining one embodiment of the present invention.

FIG. 4 is a mounting diagram of a printed circuit board for explaining one embodiment of the present invention.

FIG. 5 is a mounting diagram of a printed circuit board for explaining one embodiment of the present invention.

FIG. 6 is a sectional view of a printed circuit board for explaining one embodiment of the present invention.

FIG. 7 is a mounting diagram of a printed circuit board for explaining one embodiment of the present invention.

FIG. 8 is a flowchart illustrating a design flow of a printed circuit board according to another embodiment of the present invention.

FIG. 9 is a flowchart showing a design flow of a conventional printed circuit board.

[Explanation of symbols]

 1 pattern wiring design 2 wiring length check 201 dielectric constant, wiring impedance information input 202 pattern width-dielectric thickness ratio calculation 203 wavelength shortening rate calculation 204 clock frequency information input 205 harmonic frequency calculation 206 wavelength calculation 207 1/2 wavelength calculation 208 Clock pattern location detection 209 Discontinuous part detection 210 Discontinuous wiring length detection 211 Matching 212 Alarm 301 Printed circuit board 302 Dielectric thickness H 303 Dielectric constant εr 304 Pattern 305 Pattern width W 401 Printed circuit board 402 Part A 403 Part B 404 Terminal 405 Terminal 406 Clock pattern 501 Printed circuit board 502 Component A 503 Component B 504 Component C 505 Terminal 506 Terminal 507, 508 Via 509 Clock pattern 510 Clock pattern 5 11 Clock Pattern 701 Printed Circuit Board 702 Part A 703 Part B 704 Part C 705 Part D 706 Terminal 707 Terminal 708 Clock Pattern 709 Bend 710 Clock Pattern 711 Bend 712 Clock Pattern 801 Pattern Design 802 Wiring Length Check 803 Optimal Wiring Length Calculation 90 Wiring design

Claims (8)

(57) [Claims] 1. A printed circuit board design system comprising means for checking the wiring length of a wiring pattern so as not to match the operating signal frequency of the device and a half wavelength length of its harmonic frequency. . 2. An apparatus according to claim 1, further comprising means for calculating an optimum wiring length that does not cause the wiring length of the wiring pattern to be equal to the operating signal frequency of the device and a half wavelength length of its harmonic frequency. The printed circuit board design system as described. 3. The printed circuit board design system according to claim 1, wherein the wavelength shortening rate is calculated from the permittivity of the printed circuit board and the wiring impedance. 4. The printed circuit board design system according to claim 1, wherein a harmonic frequency in a specified frequency range is obtained by a clock frequency input, and a half wavelength is calculated. 5. The printed circuit board design system according to claim 1, wherein a wiring length between discontinuous portions of the wiring pattern is detected. 6. A step of designing a pattern wiring on a printed circuit board, a step of obtaining a wavelength shortening rate from a dielectric constant and a wiring impedance of the printed circuit board, and c) inputting clock frequency information. Calculating a harmonic frequency in a specified frequency range of electromagnetic noise, and calculating a half wavelength from the wavelength shortening rate, checking the wiring length, and determining the wiring length of the wiring pattern and the operation signal of the device. Frequency and its harmonic frequency 1
A method of designing a printed circuit board, wherein the length of the printed circuit board is not matched with the wavelength length. 7. (d) detecting a clock pattern portion from the pattern wiring design result; (e) detecting a discontinuous portion in the detected pattern; and (f) wiring between the discontinuous portions. (G) comparing the 波長 wavelength calculation result information with the wiring length detection information between discontinuous parts, and determining the clock frequency and 高調 wavelength of its harmonics and the clock of the printed circuit board. 7. The method for designing a printed circuit board according to claim 6, wherein alarm information is output when the pattern lengths match. 8. A process for obtaining a wavelength shortening rate from a dielectric constant and a wiring impedance of a printed circuit board with respect to pattern wiring design data on a printed circuit board. A process of calculating a harmonic frequency in a specified frequency range of noise and calculating a half wavelength from the wavelength shortening ratio; (c) a process of detecting a clock pattern portion from the pattern wiring design result; (E) processing for detecting a wiring length between discontinuous parts, and (f) processing for detecting the half-wavelength calculation result information and wiring length detection information between the discontinuous parts. If the clock frequency and the half wavelength of its harmonics match the clock pattern length of the printed circuit board, the above processing of outputting alarm information is performed. A recording medium recording a program to be executed by Yuta.