JP2900699B2 - Display control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access management method for a display control device.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional display control device, FIG. 6 is a flowchart showing the operation of the conventional display control device, FIG. 7 is a timing chart showing the operation of the conventional display control device, and FIG. 9 is a memory map showing the state of memory allocation as viewed from the CPU when two conventional display control devices are used to simultaneously obtain two screen images.

In FIG. 5, reference numeral 61 denotes an external access means,
62 is a display reading means, 63 is a memory management means, 64
Is a memory.

A conventional display control device will be described with reference to a flowchart. Here, the external access means 61
It is assumed that a 68000 is connected as a CPU to the.

First, an operation for reading the memory 64 managed by the display control device from the external access means 61 will be described.

When the word data is read in the 68000, the 68000 first outputs the address of the display control device to the address bus in the read state, and asserts the address strobe and the data strobe corresponding to the word access (step 70). The external access means 61 decodes the address on the address bus and confirms that the address is its own, and makes a memory access request to the memory management means 63 (step 71), and when the reading of the memory 64 is completed (step 72). The read data is output to the corresponding data bus, and a data acknowledge is asserted (step 73). When the 68000 detects the data acknowledge from the external access means 61, it transfers the data on the data bus to the designated place, stops outputting the address, and negates the address strobe and the data strobe (step 74). External access means 6
1 confirms negation of the address strobe and data strobe, stops outputting data, negates the data acknowledge, and ends the bus cycle (step 7).
5).

The above is the basic operation. The timing of a memory access request to the memory management means 63 and the time required for memory access will be described with reference to FIG.

FIG. 7 shows a state in which a display section for the display reading means 62 and a CPU section for the external access means 61 are alternately arranged, and reading of pixel data for display is performed without delay. I have.

The external access means 61 decodes the address on the address bus and, when confirming that it is the address of the memory 64 managed by the memory management means 63, makes a memory access request. The memory management means 63
At the beginning (T0) of the U section, it is determined whether there is a memory access request. At this time, if there is a memory access request, the memory access is performed, but if there is no memory access request, the memory access is suspended in the CPU section.

The memory access in the CPU section 1 is performed when a memory access request is issued immediately before T0.
Can acquire data without waiting.

In the CPU section 2, a memory access request has already been issued during the display section 1, during which the CPU is suspended from accessing the memory.

In the CPU section 3, a memory access request is issued immediately after T0, and the memory access is suspended continuously from the CPU section 3 and the display section 3, and the memory access is performed in the CPU section 4.

[0013]

However, in the above-mentioned conventional configuration, even when a memory access request is issued from the CPU, the time during which the memory access is suspended changes at the timing of the memory access request, and the average time required for the memory access is changed. Had the problem of becoming longer.

In order to simultaneously obtain image information of two screens, the memory is mapped as shown in FIG. 8 using two conventional display control devices. In this case, the image on the memory managed by each display control device can be displayed only by that display control device, and if the display is to be performed mutually, transfer for copying the image data is required. At the same time, it wastes memory.

An object of the present invention is to solve the above-mentioned conventional problems, and to provide a display control device that reduces the average required time of memory access and improves the memory use efficiency by centrally managing the memory. And

[0016]

In order to achieve this object, a display control device according to the present invention reads out information stored in a memory means and outputs it as image information, and display contents of the memory means. And an external access means for updating and referring to the first and second banks, each of which comprises a first bank and a second bank in which addresses are alternately allocated at equal intervals. While the bank is reading image information by the display reading means, the second bank is assigned to reading and writing by the external access means, and while the first bank is reading and writing by the external access means, the second bank is The memo from the display reading means and the external access means is assigned so as to be assigned to image information reading by the display reading means. It is obtained by a memory management unit to repeat the access arbitration to means.

[0017]

According to the present invention, with the above-described configuration, the average required time for memory access can be reduced, and the memory use efficiency can be improved by centrally managing the memories.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment and a second embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a display control apparatus according to one embodiment of the present invention. FIG. 2 is a flowchart showing the operation of the display control device according to the first embodiment of the present invention. FIG. 3 is a timing chart showing the operation of the display control device according to the first embodiment of the present invention. FIG. 4 is a memory map showing a memory allocation state as viewed from the CPU.

In FIG. 1, reference numeral 11 denotes external access means,
12 is a display reading means, 13 is a memory management means, 14
Is a first memory, and 15 is a second memory. In this embodiment, the external access means 11 has 68000 as a CPU.
Is connected, and the memory managed by the memory management means 13 is D
-It is assumed that a RAM is used.

The operation of the display control device according to the first embodiment of the present invention configured as described above will be described below with reference to FIGS.

First, an operation for reading a memory managed by the display control device from the external access means 11 will be described.

When the word data is read in the 68000, the 68000 first outputs the address of the display control device to the address bus in the read state, and asserts the address strobe and the data strobe corresponding to the word access (step 20). The external access means 11 decodes the address on the address bus and confirms that the address is its own, and issues a memory access request to the memory management means 13 (step 21). The output data is output to the corresponding data bus, and a data acknowledge is asserted (step 23). When the 68000 detects the data acknowledge from the external access means 11, it transfers the data on the data bus to the designated place, stops outputting the address, and negates the address strobe and the data strobe (step 24). The external access means 11 confirms negation of the address strobe and data strobe, stops outputting data, negates the data acknowledge, and ends the bus cycle (step 25).

The above is the basic operation. The timing of a memory access request to the memory management means 13 and the time required for memory access will be described with reference to FIG.

In FIG. 3, the memory access for the display reading means 12 and the memory access for the external access means 11 are alternately arranged between the first and second memories 14 and 15, and a pixel for display is displayed. The figure shows that data reading is performed without delay.

The external access means 11 decodes the address on the address bus and, when confirming that the address is a memory managed by the memory management means 13, makes a memory access request. The memory management means determines the presence or absence of a memory access request at the beginning (T0) and (T8) of each equally spaced time slot. At this time, if there is a memory access request, the first memory 1 of the even-numbered word is determined by the address information.
It is determined whether the access to the second memory 15 or the access to the second memory 15 of the odd word is performed. If there is no access, the memory access is suspended in the CPU section.

The memory access in slot 1 is a case where a memory access request has been issued at an even word address immediately before T0. In slot 1, access to only an odd word address is permitted, so the CPU is suspended from accessing. .

In slot 2, a memory access request accesses an even-numbered word address already issued during slot 1.

In slot 3, if the CPU makes a memory access request at an odd word address that is continuous from the address requested to be accessed in slots 1 and 2, the CPU can acquire data without waiting.

Even in the subsequent slot 4, the CPU obtains data without waiting for an access request of a continuous odd word address.

Next, the operation of the second embodiment of the present invention will be described. The first screen data is arranged in slots 1 and 2, the second screen data is arranged in slots 3 and 4, and reading for each screen is arranged for every two slots, and four pixel data are read and output for every two slots. This means that four pixel data of two screens are simultaneously read out every four time slots on average.

Next, the operation of the third embodiment of the present invention will be described. Changing the local address of each of the first and second memories 14 and 15 to 0 and 1 is equivalent to changing the address as viewed from the CPU to 0 and 4. Therefore, the memory management unit 13 rearranges the pixels in the order of the addresses as viewed from the CPU when the reading of the four pixels is completed so that no inconsistency occurs in the order of the read pixels, and outputs the pixels to the display reading unit 12. You.

Next, the operation of the fourth embodiment of the present invention will be described. The memory management means 13 monitors the memory access request from the display reading means 12 at the beginning (T0) and (T8) for each time slot, and when reading for display is suspended, the first in the time slot. The access right of both the first memory bank and the second memory bank is released to the external access means 11. At the same time, the memory management means 1
No. 3 determines the presence or absence of a memory access request from the external access means 11 at the beginning (T0) and (T8) of each time slot. The corresponding memory bank is accessed regardless of whether the word is an even word or an odd word.

[0033]

As described above, the display control device of the present invention
For each time slot at a predetermined interval, while the first bank is reading image information by the display reading unit, the second bank is assigned to reading and writing by the external access unit, and while the first bank is reading and writing by the external access unit, By arbitrating access to the memory means from the display reading means and the external access means repeatedly so that the second bank is assigned to image information reading by the display reading means, one of the banks is always assigned to the external access means. In addition, it is possible to reduce the average time required for memory access in random access. Furthermore, once the memory access is successful, access at consecutive addresses can be performed without suspension, and the average suspension time can be made closer to 0 as the number of consecutive accesses increases.

In the memory management means, the image information of the first screen is read in the first time slot and the subsequent second time slot, and the image information is read in the third and fourth time slots following the second time slot. The image information of the second screen is repeatedly read, and the image information of the first and second two screens is passed to the display reading means every four time slots, so that the memory access by the continuous address from the external access means can be performed. Images on two screens can be taken out without interference.

On the other hand, the first pixel and the third pixel are read out continuously during the first time slot, and the second pixel is read out continuously during the second time slot following the first time slot. After the reading of the fourth pixel, the first pixel, the second pixel, the third pixel, and the fourth pixel are rearranged in the order of the address, and are passed to the display reading unit as the read result of the image information. Thus, a pixel rate can be secured without inconsistency in the order of pixels.

In the memory management means, a memory access request from the display reading means is monitored for each time slot, and when reading for display is suspended, the first bank and the second bank in the time slot are monitored. By assigning access rights of both banks to external access means,
The average required time for memory access of the external access means can be further reduced while access for display is suspended in a blanking interval of image display or the like.

Further, since the two memory banks are treated as one continuous memory space, the images used in the first display reading means and the second reading means can be used mutually, and the arrangement of the images can be changed. Any address can be mixed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a display control device according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the display control device according to the embodiment;

FIG. 3 is a time chart for explaining the operation of the display control device in the embodiment.

FIG. 4 is a memory map for explaining the operation of the display control device in the embodiment.

FIG. 5 is a block diagram showing a configuration of a conventional display control device.

FIG. 6 is a flowchart for explaining the operation of a conventional display control device.

FIG. 7 is a time chart for explaining the operation of a conventional display control device.

FIG. 8 is a memory map for explaining the operation of a conventional display control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 External access means 12 Display reading means 13 Memory management means 14 1st memory 15 2nd memory

Claims (3)

(57) [Claims] (1) consecutive addresses are alternately divided at equal intervals;
And a first bank and a second bank.
Memory means to said read out memory means information recorded in a display reading means for outputting as image information, and external access means for referencing updates the stored contents of said memory means, for each time slot of a predetermined distance While the first bank is reading image information by the display reading means, the second bank is assigned to reading and writing by the external access means, and the first bank is reading and writing by the external access means. the second bank is to be allocated to image information read by the display reading means, and a said memory management means for performing repeated access arbitration to the memory means from the said display reading means external access means, said memory management means Is the first picture for each time slot.
The image information for the screen and the image information for the second screen are alternately read.
Managing access to the memory means so that
Display means for reading the first screen image.
A display control device for outputting image information and the second image information independently . 2. The method according to claim 1, wherein successive addresses are alternately divided at equal intervals.
And a first bank and a second bank.
Memory means for reading, and information recorded in the memory means, and image information
A display reading means for outputting as an output, and an external address for updating and referencing the contents stored in the memory means.
Access means and the first bank at each predetermined time slot.
During reading of image information by the display reading means,
The second bank is used for reading and writing by the external access means.
Assigned and the first bank is the external access
During reading and writing by columns, the second bank is
Assigned to image information readout by protruding means
From the display reading means and the external access means.
For repeatedly arbitrating access to the memory means
Memory management means , wherein the memory management means comprises a plurality of odd
The image information of the number-th pixel and a plurality of even-numbered image information
Manage the access to the memory means to read alternately
The read image information is rearranged in the display order,
Display system characterized by sequentially outputting to the display reading means
Control device. 3. The memory management means monitors a memory access request from a display reading means for each time slot, and when reading for display is suspended , both the first and second banks in the time slot are monitored. Wherein the right of access is assigned to external access means
Item 3. The display control device according to item 1 or 2 .