JP2912402B2 - Signal detection circuit in magnetic recording / reproducing device - Google Patents

Description

The present invention relates to a signal detection circuit in a magnetic recording / reproducing apparatus, and more particularly to a signal of a magnetic recording / reproducing apparatus suitable for detecting a signal recorded at high density without error. It relates to a detection circuit.

[Conventional technology]

A signal detection circuit in a conventional magnetic recording / reproducing apparatus performs data reproduction by detecting a peak of an output waveform of a magnetic head. However, noise or undershoot included in the output waveform causes the occurrence or disappearance of data, thereby limiting the reliability of information.

To improve such problems, Japanese Patent Publication No. 60-28460
As described in Japanese Patent Application Laid-Open Publication No. H10-260, the following four conditions have been proposed as conditions for determining a valid peak. (1) The detected signal pulse must have an appropriate polarity, and the polarity of successive pulses must be inverted. (2) The signal amplitude must exceed a predetermined threshold level.
(3) A point at which the sign of the signal slope changes, that is, a peak detection is required. (4) The voltage change from the highest amplitude point, that is, the peak, must decrease by the predetermined voltage ΔV before the predetermined delay time elapses. When these four criteria were satisfied, it was determined to be a valid peak.

[Problems to be solved by the invention]

FIG. 4 shows that the reproduced waveform includes noise caused by the reading circuit and the head and noise caused by a medium defect.
This shows a reproduced waveform in which a waveform peak occurs at a place other than the recording data “1”, or a part that should originally be the data “1” has disappeared. Numerical values written over the time (n-2) to (n + 13) are sampling values by a clock. If a signal determination in bit units is performed on the reproduced waveform by the conventional method, a signal can be accurately detected for a noise waveform that slightly exceeds a threshold level due to noise or undershoot. However, at a high recording density F, a reproduced waveform that dynamically fluctuates due to the data bit length, a waveform in which a transition portion between a medium defect, noise, and data bits sufficiently exceeds a threshold level (the slope of the waveform has a predetermined monitoring voltage ΔV In the case of a lost waveform in which valid data does not exceed a threshold level due to dropout or the like, accurate signal detection cannot be performed.

For example, when the reproduced waveform shown in FIG. 4 is identified by the conventional method, the peak value at the time n, (n + 2) is smaller than the threshold level, and it is erroneously assumed that “1” is originally “1”. After detection, the peak amplitude values at times (n + 5) and (n + 10) sufficiently exceed the threshold level, and erroneous detection of "0" as "1" originally occurs. Therefore, under high-density recording, there has been a problem that correct signal detection becomes impossible.

The present invention has been made in view of the above-described prior art,
At a high recording density F, a source waveform in which a pseudo peak sufficiently exceeds the threshold level due to noise, undershoot, medium defect, or the like, or a loss in which an effective peak does not exceed the threshold level. An object of the present invention is to provide a signal detection circuit in a magnetic recording / reproducing device capable of maintaining good signal detection performance for a waveform.

[Means for solving the problem]

The signal detection circuit in the magnetic recording / reproducing device generates a clock signal synchronized with the peak value of the reproduced signal read from the magnetic recording medium, and calculates the clock signal from the absolute value of the peak value of the reproduced waveform at the timing synchronized with the clock signal. Quantization means for applying a signal detection circuit in a magnetic recording / reproducing apparatus for determining “1” or “0”, for quantizing a reproduction signal in synchronization with the clock signal and outputting a quantized signal; A multi-stage shift register that delays the quantized signal in synchronization with the clock signal, and compares the value of the quantized signal output from the last stage of the shift register with the quantized signal indicating the current reference value. If the quantized signal output from the last stage of the shift register is larger than the quantized signal indicating the current reference value, the quantized signal output from the last stage of the shift register A reference value generating unit that outputs a new reference value and holds the current reference value when the value of the quantized signal output from the last stage of the shift register is smaller than the quantized signal indicating the current reference value; Arithmetic means for adding the reference value and the quantized signal output from the last stage of the shift register, and subtracting and outputting the quantized signal output from the last stage of the shift register from the reference value; The plurality of quantized signals output from each stage of the register and the two quantized signals output from the arithmetic unit are respectively converted according to the detection logic of the data pattern “1” based on the (d, k) run-length code. And a detecting means for detecting "1" from the plurality of comparison results according to the detection logic of the data pattern "1" based on the (d, k) run-length code. And

[Action]

According to the present invention, the reference value is sequentially changed by the reference value generation means, and based on the output of the arithmetic means and the shift register, the detection means detects the "1" detection logic of the (d, k) run-length code. Perform detection according to for that reason,
Even when a pseudo peak exists in the reproduced waveform or when the effective peak does not exceed the threshold, signal detection can be performed accurately.

That is, the signal detection circuit of the present invention searches for a peak value exceeding the positive reference value and a peak value exceeding the negative reference value in order to distinguish between a valid signal peak and a pseudo peak. Two signal detection algorithms are used. As this signal detection algorithm, an effective peak is determined by using the following characteristics of a series signal in magnetic recording.

(1) A portion where the positive / negative amplitude of the read signal is larger than the reference A is determined as data “1”.

(2) In a portion where the amplitude is smaller than the reference value, there may be a case where noise of a portion “0” gushes out or a case where a signal of “1” originally disappears. In this case, the determination is made based on the relationship between the front and rear bits.

(3) The occurrence of "1" is restricted by the (d, k) run-length code. For example, there are four types of data patterns in the (0,3) run-length code, "11", "101", "1001", and "10001". Therefore, the inspection target is narrowed down to four types of patterns. Also, "1" always exists in four bits. In the present invention, an effective peak and noise are distinguished by using such characteristics of magnetic recording.

Further, the generation of the reference value for judging the signal is performed using the peak level of the reproduction signal to be judged at present, and the reference value is automatically adjusted in proportion to the fluctuation within the entire amplitude of the reproduction signal.

Further, the operation of the signal detection circuit of the present invention will be described with reference to the reproduced waveform of the (0,3) run-length code illustrated in FIG. In FIG. 4, the reproduced waveform has an effective peak and includes noise, undershoot, and noise due to a medium defect. In FIG. 4, the dotted line portions of the waveforms (a), (b) and (c) represent appropriate reproduction waveforms. The solid lines in the waveforms (a), (b), and (c) show the effective peaks (n,
n + 2) and invalid peaks (n + 5, n + 10) due to noise and undershoot. The signal detection circuit according to the present invention is designed to detect a signal having high reliability with respect to such a waveform generated by the disappearance of the effective peak waveform or the pseudo peak due to noise.

In the signal detection algorithm according to the present invention, as described above, in the reproduced waveform, effective peaks appear alternately in correspondence with the recording data, and further, the generation pattern of the bit sequence is restricted by the (d, k) run-length code. By using such characteristics of magnetic recording, valid peaks and noise are distinguished from the context of bits to be determined. When the reproduced waveform shown in FIG. 4 is specifically identified, it is as follows. (1) Since the first bit (time n-2) has a large amplitude on the positive side, the signal "1"
Is determined. (2) Since the next bit (time n-1) has a large amplitude on the negative side, it can be determined that the signal is "1". (3) Since the next bit (time n, waveform a) has a small amplitude on the positive side and the next bit (time n + 1) has an amplitude larger than the reference value level on the negative side, the signal "1" Is determined. (4) Since the next bit (time n + 1) has a large amplitude on the negative side, it is determined that the signal is “1”. (5) The next bit (time n + 2) has a small amplitude on the positive side, but the bit at time n + 4 has a larger amplitude on the negative side than the reference value level. (6) Time n +
Since the bit of 4 has a larger amplitude on the negative side than the reference value level, it can be determined that the signal is "1". (7) Next bit (time n
+5, waveform b) has a large amplitude on the positive side and has the opposite polarity to the previous bit, but since the bit at time n + 8 has the same polarity and has an amplitude greater than waveform b, it can be determined as noise. Since the next bit (time n + 8) has a large amplitude on the positive side and the next bit (time n + 9) has a large amplitude on the negative side, it can be determined that the signal is "1". (9) Since the next bit (time n + 9) has a large amplitude on the positive side, the signal "1"
Can be determined. (10) The next bit (time n + 10, waveform c) has a large amplitude on the positive side and has the opposite polarity to the previous bit, but since the bit at time n + 12 has the same polarity and has a larger amplitude than waveform c. This is noise and can be determined to be “0”. In FIG. 4, time n + 3, n + 5 to n + 7
Are not compatible with the “1” detection logic, and are therefore determined to be signal “0”.

As described above, in the signal detection circuit of the present invention, peaks of the opposite polarity appear alternately in correspondence with the recording data “1”. The generation pattern of the bit sequence is restricted by the (d, k) run-length code. For example, in the (0,3) code, the sequence of "0" is 3 bits. That is, since "1" always exists in 4 bits, the signal and noise are distinguished by using the characteristic of magnetic recording such that the inspection target is narrowed down to 4 bits. Therefore, correct read data can be obtained with respect to a lost waveform whose effective peak waveform is smaller than the threshold level and a well-formed waveform that sufficiently exceeds the threshold level in the conventional signal detection method based on bit-by-bit signal determination.

〔Example〕

Hereinafter, the present invention will be described in more detail with reference to examples shown in the accompanying drawings.

FIG. 3 is an explanatory diagram showing a positive-side signal detection algorithm in which the present invention is applied to a (0,3) run-length code.
As is well known, the (0,3) run length code is “11”, “1”.
It is possible to take only four patterns of 01 "," 1001 ", and" 10001 ". When the state transitions of these four patterns are represented by a lattice diagram, FIGS. 2 (a), (b), and (c) respectively. ),
(D). In the figure, state 0 indicates a state where signal detection on the positive side is expected, and state 0 indicates a state where signal detection on the negative side is expected. The symbol A, 0 written along each path is an output when a transition occurs in that path.

As shown in FIG. 2 (a), if the output state at time (n-1) is state 0, the reproduction time (n
It can be seen that there are two partial paths P1 and P2 that merge at +1). The first partial path P1 is at time n or (n +
The path where "1" does not exist in 1). The second partial path P2 is a path having a positive “1” at time n and a negative “1” at time (n + 1). In the detection of "1" on the positive side at time n, the most desirable case is a path with a small least square error. Therefore, if the second partial path P2 is likely to occur, the following relational expression is established from the grid diagram shown in FIG.

(V (n) + A) ² + (V (n + 1) + A) ≦ (V (n) -0) ² + (V (n +
1) -0) ² , V (n) −A ≧ V (n + 1) (1) holds. Equation (1) shows that at time n, a positive “1” exists,
If there is a negative "1" at time (n + 1), the first partial path P1 is rejected without possibility of being established. Since it is determined that the surviving second path P2 is a correct path, "1" is determined at time n.

In FIG. 2 (b), as in the case of FIG. 2 (a), the state is 0 at the time (n-1) and again at the time (n +
Three partial paths P3 and P that join state 0 in 2)
4, P5 exists. The first partial path P3 is at time n, (n +
1), (n + 2) path without positive “1”, second path
Is a path where "0" is present at time n and "1" is present at time (n + 1), and a third partial path P5 is a path where "1" is present at time n. In this grid diagram, the following relational expression is obtained from the first and third partial paths P3 and P5.

V (n) −A ≧ V (n + 2). Further, the second partial path P4 has a relationship of V (n)> V (n + 1). If the relationship of the following expression (2) that simultaneously holds the above two expressions is obtained, at time n, " 1 "is determined.

V (n)> V (n + 1) and V (n) −A ≧ V (n +
2) (2) Similarly, in FIG. 2 (c), there are four partial paths P6, P7, P8, P9 that merge at time (n + 3). As shown in the partial path P9, if the negative “1” exists at the time (n + 3) and “0” exists at the times (n + 1) and (n + 2), the following relationship is established.

V (n) −A ≧ V (n + 3) In the partial paths P7 and P8, the relationship of V (n)> V (n + 1) and V (n)> V (n + 2) is established. Therefore, if the relationship of the following expression (3) in which the above two expressions are simultaneously satisfied is obtained, “1” at time n is determined.

V (n)> V (n + 1) and V (n)> V (n + 2) a
nd V (n) -A> V (n + 3) (3) In FIG. 2 (d), the negative “1” is the time (n +
Since it does not exist in 3), the relationship of V (n)> V (n + 3) holds. This is because, in the (0,3) run-length code, the positive "1" always exists at times n, n + 1, n + 2, n + 3, and n + 4. Therefore, it is considered appropriate to select the four bits having the largest peak amplitude on the positive side, and the following relationship is established.

V (n)> V (n + 1) and V (n)> V (n + 2)
and V (n)> V (n + 3) and V (n) −A ≧ V (n +
4)... (4) By the same reasoning, the algorithm for detecting “1” on the negative side can be derived as in the following equation.

V (n) + A ≦ V (n + 1) (5) V (n) <V (n + 1) and V (n) + A ≦ V (n +
2)... (6) V (n) <V (n + 1) and V (n) <V (n + 2) a
nd V (n) + A ≦ V (n + 3) (7) V (n) <V (n + 1) and V (n) <V (n + 2)
andV (n) <V (n + 3) and V (n) −A ≦ V
(N + 4) (8) In the signal detection circuit of the present invention, the expressions (1) to (3) are used as the positive-side detection logical expression, and the expression (4) is used as the negative-side detection logical expression.
Equations (6) to (6) are used. The determination of the signal is performed as follows. That is, with respect to the sampled value of the read signal, the logical expressions (1) to (3) are satisfied during the positive peak search, and the logical expressions (4) to (6) are satisfied during the negative peak search, and After examining the subsequent bit sequence of two or more bits, it is determined as data "1". If the logical expressions (1) to (3) are not satisfied at the time of the positive peak search and the logical expressions (4) to (6) are not satisfied at the time of the negative peak search, after examining the subsequent bit sequence of two or more bits, Data "0" is determined. The logic configuration is adapted to apply the polarity alternation requirement to the read signal.

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG.
The figure is a time chart showing the operation. In FIG. 1 and FIG. 3, a read signal 201 is converted into an analog signal, for example, via an automatic gain control circuit (not shown), a peak detection circuit 101 and an A / D (analog / digital) converter 10.
Given to 3. The peak detection circuit 101 receives the read signal 201 and generates and outputs peak data 202 of the read signal 201. The peak data 202 is input to the reference clock generator 102. The reference clock generator 102 generates a clock signal 203 whose phase is synchronized with the peak data 202. A / D converter 10
3 generates a quantized digital signal 204 by sampling the read signal 201 based on the clock signal 203. The quantized digital signal 204 is transmitted to a four-stage shift register 1
The signal is sent to the reference A generation circuit 105, the arithmetic circuit 106, and the comparison units 310, 311 and 312 in the comparator 107 via the line 04.

The reference A generation circuit 105 receives the quantized digital signal 204a output from the shift register 104 as an input, and the full-wave converter 305 converts the quantized digital signal 204a into a full-wave waveform based on the center level of the quantized digital signal 204a. The signal is converted to 206 and output to one input terminal of the comparator 306 and the D-type flip-flop 308. Flip-flop 308
Is sent to the comparator 306 via the voltage divider 309. The voltage divider 309 is composed of, for example, a division circuit. The voltage divider 309 reduces the voltage value of the output A to 1 / n to form an output 207, and outputs the output 207 to the other input terminal of the comparator 306. One input terminal of the comparator 306 has a full-wave waveform 206 output from the full-wave converter 305 as described above.
Is entered. Accordingly, the comparator 306 sets the output 208 to “H” when the full-wave waveform 206 exceeds the value of the output 207 of the voltage divider 309. The output 208 is input to the AND gate 307 together with the clock signal 203. When the output 208 of the comparator 306 is “H”, the flip-flop 308 takes in the full-wave waveform 206 output from the full-wave converter 305 and outputs it as the reference A. The purpose of the circuit is to hold the quantized digital signal 204 as reference A only when the quantized digital signal 204 is "1" instead of "0". The reason for this is that the generation of the reference A is made to follow the peak level fluctuation of the partial response signal in a state where the data “1” is detected. Therefore, criterion A
Is the digital data "1" in the partial response signal
Voltage level that simultaneously follows the magnitude of the level change.

The arithmetic circuit 106 receives the reference A and the quantized digital signal V (n) at time n as inputs, generates (V (n) -A) and (V (n) + A), and generates (V (n) -A). ) Is the comparison section
317,318,319,320 is input to one input terminal,
(N) + A) is input to one input terminal of the comparison units 313, 314, 315, 316. The other input terminal of the comparison unit 320 is connected to the quantized digital signal V (n +
1) is input, and the output α _P of the comparison unit 320 becomes “H” when the expression (1) is satisfied, and is output to the OR circuit 317 of the positive side detection logic circuit 109. by being detected with alpha _P is "H", it is detected first "1" of the data in the primary side of the "11" pattern (0,3) run-length code.

At the other input terminal of the comparator 319, the time V (n +
The quantized digital signal V (n + 2) in 2) is input, and the output of the comparison unit 319 is V (n) −A ≧ V (n
When “+2) is satisfied, the signal goes to the“ H ”level, and is sent to the AND gate 321. The other input terminal of the AND gate 321 has a comparator 31 which is set to “H” when V (n)> V (n + 1).
The output of 2 is input. Therefore, AND gate 3
When the output β _P of 21 is expressed by a logical expression, the above expression (2) is obtained. When the expression (2) is satisfied, the first data “1” of the positive “101” pattern is detected.

The other input terminal of the comparison unit 312 has a time (n +
The quantized digital signal V (n + 1) in 1) is input, and the other input terminal of the comparison unit 311 is connected to the time (n + 1)
The quantized digital signal V (n + 2) at time (n + 3) is input to the other input terminal of the comparison unit 310. Therefore, the output terminal P of the comparison unit 312 is V (n)
"H" is output to the first input terminal of the AND circuit 319 when> V (n + 1) is satisfied, and the output terminal P of the comparison unit 311 is "H" when V (n)> V (n + 2) is satisfied. Is output to the second input terminal of the AND circuit 319, and the output terminal P of the comparison unit 310 outputs “H” to the third input terminal of the AND circuit 319 when V (n)> V (n + 3) holds. I do. Therefore, if the output γ _P of the AND circuit 322 is represented by a logical expression, the above expression (3) is obtained. When the equation (3) is satisfied, the positive side “100
The first data "1" of the 1 "pattern is detected.

Similarly, when the output δ _P of the AND circuit 323 is expressed by a logical expression, the above expression (4) is obtained. When the expression (4) is satisfied, the first data “1” of the positive “10001” pattern is detected.

In the positive side detection logic circuit 108 described above, α _P , β _P ,
Similarly to γ _P and δ _P , the OR circuit 329 and the AND circuits 325, 326, 3
Α _N and β in the negative side detection logic circuit 109 composed of 27
_N , γ _N , δ _N are “H” when α _N satisfies the equation (5).
Next, beta to "H" when _{the N} is the (6) is established, gamma when _N is the (7) is established to "H", [delta] _N
Is set to “H” when the equation (8) is satisfied.

In FIG. 1, the flip-flop 423 is set when the output 210 of the positive signal detection logic circuit 108 is “H”, reset when the output 211 of the negative signal detection logic circuit 109 is “H”, and outputs 212. Generate Therefore, when the set or reset signal is continuously generated for the flip-flop 423, the second and subsequent signals are effectively ignored. The output 212 is extended by one clock at the clock 203 by the flip-flops 424 and 425 to generate the output 213. Then, by taking exclusive logic of the output 212 and the output 213, the read data 216 corresponding to the recording data is obtained.
Get.

As is clear from the above description, in this embodiment, (0,
3) If the relation of any of the equations (1) to (3) or (4) to (6) obtained from the grid diagram of the pattern of the run length code is satisfied, it is determined to be "1". If not satisfied, it is determined to be “0”. For example, in the reproduced waveform of the “11” pattern at time n in FIG. 4, the ideal amplitudes at times (n−1), n, (n + 1), and (n + 2) are −1, 1, −1, 1 However, the actual waveform sample values are -0.9, 0.2, -1.0, 0.3. Where A =
Substituting 0.85 into equation (1) gives 0.2−0.85 ≧ −1.0. Therefore, the relationship of the inequality expression (1) is satisfied, the bit at time n is determined to be positive “1”, and correct read data is obtained. In this manner, in the present embodiment, if the negative peak at time (n + 1) is equal to “1”, correct read data can be obtained unless the amplitude at positive time n to be identified becomes −0.15 or less. can get. Similarly, the fourth
In the "101" pattern waveform at the time (n + 2) in the figure, the sample values are -1.0, 0.3, -0.3, -1.1, and the ideal amplitudes are -1,1,0, -1. In this reproduced waveform, since the inequality expression (2) is satisfied, the bit at time (n + 2) is determined to be “1” on the positive side, and correct read data is obtained. Finally, in the “10001” and “1001” pattern waveforms at time (n + 5), the sample value is
−1.1, 0.6, 0.1, −0.1, 1.0 and −1.1, 0.9, 0.4, 1.0.
In this case, since the expressions (1) to (6) are not satisfied, the times (n + 5) and (n + 10) are determined to be “0”. As described above, the signal detection circuit of this embodiment can correctly identify a signal that cannot be discriminated by the conventional method due to a local defect or noise of the medium.

Note that the signal detection algorithm used in the present invention can be extended to other (d, k) codes. For example,
In the 1 ± 07 modulation method and the 2 ± 07 modulation method, the number of stages n of the shift register is calculated from (d, k) run-length code code as n =
It is easily understood that k may be set to satisfy k and the grid diagram used in the (0,3) code may be developed according to the pattern of each modulation method.

In the embodiment described above, when generating the reference A, the full-wave waveform 206 of the full-wave converter 305 and the output 207 obtained by converting the current reference A into 1 / n by the voltage divider 309 are used. However, the present invention is not limited to this.
Instead of using 309, the current reference A may be used as it is.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, a pseudo peak occurs due to noise, undershoot, medium defect, and the like in the reproduction waveform of a signal recorded at high density, and this causes a sufficient threshold level. If the effective peak does not exceed the threshold level,
It is possible to maintain good signal detection performance without errors.

Also, since the component is a logic circuit, it has features such as high integration, variation of elements, and low temperature characteristics.
As a result, good signal detection performance can be maintained even if the signal quality is reduced due to the narrow track or the high density.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 (a), (b), (c) and (d) show signal detection algorithms employed in the embodiment shown in FIG. FIG. 3 is a time chart showing an example of the operation of the embodiment shown in FIG. 1, and FIG. 4 is a graph showing a pseudo peak caused by a medium defect or noise or an effective peak not reaching a threshold level. FIG. 9 is a waveform diagram showing an example of a reproduced waveform including the waveform. 101: peak detection circuit, 102: reference clock generator, 103
... Analog / digital (A / D) converter, 104 ... Shift register, 105 ... Reference A generation circuit, 106 ... Operation circuit, 107 ...
Operation comparison circuit, 108: positive signal detection logic circuit, 109: negative signal detection logic circuit.

Claims (3)

(57) [Claims] A peak detection circuit for detecting a peak of a reproduction signal read from a recording medium; a reference clock generator connected to the peak detection circuit for generating a clock signal synchronized with the peak of the reproduction signal; An A / D converter connected to a clock generator and digitizing a reproduction signal in synchronization with the clock signal to generate a digital signal; and an A / D converter connected to the A / D converter and converting the digital signal to the clock signal. A plurality of shift registers for delaying in synchronization with each other, a last stage shift register of the plurality of shift registers and a reference clock generator, and a value determined based on a current reference value and the last stage. The value of the full-wave waveform output from the shift register is compared with the value of the full-wave waveform output from the shift register. A reference value generating means for outputting the value of the output full-wave waveform as a new reference value, and maintaining the current output when the value of the output of the final-stage shift register is small; A calculating means connected to a shift register and the reference value generating means for calculating a sum of an output value of the last-stage shift register and a difference between an output value of the last-stage shift register and the reference value; Connected to a shift register and the arithmetic means,
The output of each of the plurality of shift registers and the output of the arithmetic means are set to the peak "1" of the reproduced signal based on the data pattern based on the (d, k) run-length code,
A detection logic unit for determining "0" and outputting the read data as read data. 2. The reference value generating means includes: a voltage divider that outputs a value of 1 / n of a current reference value; a full-wave converter that converts an output of the last-stage shift register into a full-wave waveform; A comparing unit connected to the voltage divider and the full-wave converter, for comparing an output value of the voltage divider with an output value of the full-wave converter, and connected to the comparing unit and the reference clock generator, When the output value of the full-wave converter is large, the output of the full-wave converter is output as a new reference value in synchronization with the reference clock, and when the output value of the full-wave converter is small, the current reference 2. The signal detection circuit according to claim 1, further comprising: a voltage divider that maintains a value and outputs the reference value to the voltage divider and the arithmetic unit. 3. The shift register includes a first shift register connected to an A / D converter, a second shift register connected to the first shift register, and a second shift register. A third shift register connected thereto, and a fourth shift register connected to the third shift register.
Wherein the comparing means determines the sign of the difference between the output value of the fourth shift register and the output value of each of the first to third shift registers. , A third comparing unit, a fourth comparing unit that determines the sign of the difference between the sum of the output value of the fourth shift register and the reference value and the output of the A / D converter, A fifth, sixth, and seventh comparing unit that determines the sign of the difference between the sum of the output value and the reference value of the shift register and the output value of each of the first to third shift registers; An eighth comparison unit that determines the sign of the difference between the output value of the shift register and the reference value and the output of the A / D converter; and the output value of the fourth shift register and the reference value. And the first
And a ninth, tenth, and eleventh comparison unit that determines the sign of the difference from each output value of the third shift register, and the detection logic unit determines a result of the determination by the tenth comparison unit. And the first AND circuit which is at the “H” level when the value of the comparison unit is 0 or positive and the determination result of the third comparison unit is positive, and the determination result of the ninth comparison unit is 0 or positive and the second and third And the second AND circuit, which is at the “H” level when the judgment result of the comparison unit is positive, the judgment result of the eighth comparison unit is 0 or positive and the judgment results of the first to third comparison units are A fourth AND circuit that goes to "H" level when positive, and when the determination result of the eleventh comparing section is 0 or positive, or when any of the first to third AND circuits is at "H" level A positive-side detection logic unit having a first OR circuit that goes to an “H” level; and a “H” level when the determination result of the sixth comparison unit is 0 or negative. A fourth AND circuit, a fifth AND circuit that goes to “H” level when the determination result of the fifth comparing unit is 0 or negative and the determination results of the second and third comparing units are negative, When the determination result of the fourth comparison unit is 0 or negative and the determination results of the first to third comparison units are negative, the sixth level becomes “H” level.
And the second OR which becomes "H" level when the determination result of the seventh comparison unit is 0 or negative or when any of the fourth to sixth AND circuits is at "H" level 2. The magnetic recording apparatus according to claim 1, further comprising: a negative side detection unit having a circuit; and a circuit that outputs an exclusive OR of the first OR circuit and the second OR circuit as read data. Signal detection circuit in the playback device.