JP2938831B2 - Delayed branch control method and circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to control of the branch operation in a processor, in particular, Ru <br/> the related control to the delayed branch operation in a processor of the delayed branch method.

[0002]

2. Description of the Related Art In a so-called pipeline processing system for executing instructions in a pipeline, a system called a delayed branch has been conventionally used. For example, consider a case where instruction processing is performed by pipeline processing including three stages of instruction fetch (F), instruction decode (D), and instruction execution (E) as shown in FIG. As can be seen from FIG. 10, in the pipeline processing, since the instruction at the branch destination is fetched after the decoding of the branch instruction is completed, an empty slot (delay slot) for at least one stage is generated. The number of delay slots is
It is given by the number of stages other than the fetch and execution stages in the pipeline processing.

[0003] Delayed branching is a method of removing useless empty slots by inserting an instruction at the next address of a branch instruction into a delay slot. By using this method, the performance of an information processing apparatus is improved. (JP-A-4-127237, JP-A-3-122718)
Reference).

A conditional branch instruction determines whether or not to branch in accordance with a condition flag on which an execution result of an operation instruction, a transfer instruction, or the like is reflected. Conventionally, however, rewriting of the condition flag is controlled. There has been a method for improving the degree of freedom in determining the order of execution of instructions. For example, in the RISC processor SPARC, one control bit for determining whether or not to rewrite the condition flag is provided in the code of the operation instruction, and when the value of this control bit is "1", the operation result is set to the condition flag. On the other hand, if the value is "0", do not rewrite the condition flag ("SPARC Architectur
e Manual ", SunMicrosystems Inc., 1991). With such a method, whether or not the condition flags are rewritten can be controlled for each instruction. improves.

[0005]

However, there have been the following problems in the prior art.

First, in the above-described delayed branch method, there is a problem in that when the delayed branch instructions are consecutive, the execution order of the instructions becomes complicated.

FIG. 11 is a diagram showing an example of a program at an assembler language level in the case where successive delayed branch instructions are provided. An address 100 includes a first delayed branch instruction br20.
0 (branch to address 200 when the condition is satisfied) is described in address 101, and second delayed branch instruction br400 (branch to address 400 when the condition is satisfied) is described in address 101. FIG. 12 is a diagram showing the relationship between the presence or absence of a branch in each delayed branch instruction and the execution order of the instructions when the program shown in FIG. 11 is executed. The operation of the program shown in FIG. 11 is divided into two cases, a case where the first delayed branch instruction br200 branches and a case where the branch is not performed.
In this case, there are two cases: a case in which the branch is performed by the delayed branch instruction br400, and a case in which the branch is not performed. Therefore, a total of four cases are considered as shown in FIG.

Here, the first and second delayed branch instructions br
In the case where the condition is satisfied in both 200 and br400 and the branch is taken, as shown in FIG.
After the instruction at address 200 is fetched due to the satisfaction of the branch condition of r200 (the instruction at address 200 is described as (200) in FIG. 13), the address of address 400 is satisfied by the satisfaction of the branch condition of the second delayed branch instruction br400. The instruction is fetched (in FIG. 13, the instruction at address 400 is described as (400)). Therefore, in this case, as shown in FIG. 12, after jumping to the branch destination (address 200) of the first delayed branch instruction br200 and executing only one instruction, the branch destination of the second delayed branch instruction br400 is further reduced. A complicated operation of jumping to (address 400) and executing the instruction is performed.

This significantly impairs the readability of the program at the assembler language level.
This can cause bugs to be created in the program.

[0010] In particular, a programmer who does not fully understand the delayed branch creates a program without expecting such an operation, and thus certainly creates a bug.
In addition, since this bug can be known only when successive delayed branch instructions are both taken and the condition is satisfied, it is extremely difficult to debug in advance and often cannot be found until the device is actually operated.

In order to avoid this problem, a veteran programmer who is familiar with delayed branching takes measures such as inserting a no-operation instruction (NOP) between successive delayed branch instructions in a program. Such a response is troublesome and often forgotten. Furthermore, if the number of delay slots of the processor increases, it is necessary to insert the no-operation instructions as many as the number of delay slots, so that the program becomes redundant and the memory capacity for storing the program increases.

This problem can occur even when the delayed branch instructions are not consecutive, even when the instructions are relatively close in the order of the program. In FIGS. 12 and 13, the number of delay slots of the processor is assumed to be 1. However, if the number of delay slots of the processor is larger, even if the delay branch instructions are not consecutive, the interval is equal to the number of delay slots of the processor. If it is smaller than the above, a similar problem occurs, and when the branches are taken together, the execution order of the instructions becomes complicated.

On the other hand, a control bit for determining whether or not to perform a delayed branch is provided in the code of the delayed branch instruction. When this control bit is 0, the control bit is placed in the delay slot when the conditional branch is established. There is a type of processor that does not execute an instruction (see Japanese Patent Application Laid-Open No. 4-127237). FIG.
FIG. 12 is a diagram showing the relationship between the presence or absence of a branch in each delayed branch instruction and the execution order of instructions when the program shown in FIG. 11 is executed by this type of processor. In FIG. 14, "***" indicates that the instruction placed in the delay slot is not executed. In this case, if the control bit of the first delayed branch instruction br200 is set to 0, as shown in FIG. 14, the first delayed branch instruction br2
00, it is determined whether or not to branch to the address 200, and the second delayed branch instruction br4
Since 00 is executed, the readability of the program at the assembler language level is not impaired.

However, providing a control bit for determining whether or not to perform a delayed branch in the instruction code increases the bit width of the instruction code by one bit, and thus increases the memory capacity for storing the program. The problem arises. Especially in portable information devices, the increase in memory capacity
This is a fatal drawback in terms of the size of the device, power consumption, manufacturing cost, and the like. In this case, a circuit for performing delayed branch control based on the control bits of the delayed branch instruction code is required in the instruction decoder.

If the bit width of the instruction code is already determined by the standard, the provision of the control bit, even if it is one bit, is a great constraint in the design of the device. For example, when the instruction code is 24 bits, the number of bits that can be freely used in design is at most a few bits except for the necessary bits indicating the type of the instruction, the designated address, and the like. Therefore, the control bit is only one bit. However, the degree of freedom in design is greatly impaired.

A similar problem also occurs in the conventional condition flag rewriting control. In other words, providing a control bit for rewriting the condition flag in the instruction code means that the memory capacity for storing the program increases, and a circuit for performing the condition flag rewriting control based on the control bit of the instruction code is required. There arises a problem that it becomes necessary in the instruction decoder and a problem that the degree of freedom in device design is impaired.

In view of the above-mentioned problems, the present invention provides a delayed branch which makes it easy to read a program at an assembler language level without complicating the execution order of instructions even when the delayed branch instructions are continuous or relatively close. An object of the present invention is to realize a control method without providing a control bit in an instruction code, and to provide a circuit for realizing the method .

[0018]

Means for Solving the Problems In order to solve the above-mentioned problem, a solution taken by the invention of claim 1 is a delay branch control method for controlling a branch operation of a delay branch instruction in a processor of a delay branch system. When executing a delayed branch instruction, if a branch is taken in a predetermined cycle of a cycle from one cycle before the execution cycle of the delayed branch instruction to the number of delay slots before the processor, the delayed branch instruction is executed. Is prohibited.

According to the first aspect of the present invention, even if the branch condition of the delayed branch instruction is satisfied, the branch is prohibited if the branch is performed in the predetermined cycle that is traced back from the execution cycle of the delayed branch instruction. No branch is taken. For this reason, even in the case where both of the branch conditions are satisfied in the delayed branch instruction relatively close to the number of delay slots of the processor, the execution order of the instructions is not complicated, and the program at the assembler language level becomes easy to read. .

According to a second aspect of the present invention, in the delayed branch control method of the first aspect, all the cycles from one cycle before the execution cycle of the delayed branch instruction to the number of delay slots before the processor are set to the predetermined number. Cycle.

According to the second aspect of the present invention, even if the branch condition in the delayed branch instruction is satisfied, the branch is prohibited if the branch is taken in the past by the number of delay slots of the processor. Is not done. For this reason, when the delayed branch instructions are continuous, if the branch is not performed by the first delayed branch instruction, it is determined whether or not the second delayed branch instruction branches depending on whether or not the branch condition is satisfied. On the other hand, when the branch is performed by the first delayed branch instruction, the branch of the second delayed branch instruction is prohibited, so that the branch is not performed regardless of whether the branch condition is satisfied or not. That is, when the delayed branch instructions are consecutive, the first delayed branch instruction apparently performs the same operation as the non-delayed branch instruction, so that the flow of the program at the assembler language level becomes easier to read. Similarly, even for delayed branch instructions that are not consecutive but are not separated by the number of delay slots of the processor, the order of execution of the instructions is not complicated, so that the program at the assembler language level is easy to read .

[0022] Also, solutions of the invention is taken of claim 3 is provided to a processor of a delayed branch method, a delayed branch control circuit for controlling a branch operation of the delayed branch instruction, before one of the current execution cycle In a predetermined cycle among cycles up to the number of delay slots before the processor,
A branch information storage circuit for storing whether or not a branch has been taken;
When the delayed branch instruction is executed, the processor is executed only when the branch condition of the delayed branch instruction is satisfied and the branch information storage circuit stores that the branch was not performed in the predetermined cycle. And a branch determination circuit for instructing a branch.

According to the third aspect of the present invention, when the delayed branch instruction is executed, the branch condition of the delayed branch instruction is satisfied,
Only when the branch information storage circuit stores that the branch was not taken in a predetermined cycle that is traced back from the execution cycle of the delayed branch instruction, the branch is instructed to the processor by the branch determination circuit. . Therefore, even if the branch condition in the delayed branch instruction is satisfied, the branch is not performed if the branch information storage circuit stores that the branch has been performed in the predetermined cycle. Therefore, even in the case where the branch condition is satisfied for both delayed branch instructions that are not separated by the number of delay slots of the processor, the execution order of the instructions is not complicated, and the program at the assembler language level is easy to read.

[0024] In the invention of claim 4, wherein the claim
In the delay information storage circuit in the delay branch control circuit of No. 3, all the cycles from one before the current execution cycle to before the delay slot number of the processor are set as the predetermined cycle.

[0025] According to the invention of claim 5 , in claim 4,
The branch information storage circuit in the delay branch control circuit includes a number of flip-flops connected in series corresponding to the number of delay slots of the processor. Each time an instruction is executed in the processor, the branch information storage circuit of the branch determination circuit is It is assumed that a shift register that inputs an output signal and shifts a held signal is provided.

According to the fifth aspect of the present invention, the signal held in each flip-flop of the shift register indicates whether or not a branch has been taken in each cycle from one immediately before the current execution cycle to the number of delay slots before the processor. Will be represented. Therefore, the branch information storage circuit can be configured with a simple configuration.

[0027] In the invention of claim 6, claim 4
The branch information storage circuit in the delay branch control circuit starts counting the number of executed instructions in the processor when the branch determination circuit instructs the processor to branch, and the count value reaches the number of delay slots in the processor. And a latch circuit that sets the output signal when the counting of the counter is completed while the output signal is cleared when the branch determination circuit instructs the processor to perform the branch. Shall be.

According to the sixth aspect of the present invention, the output signal of the latch is cleared between the time when the branch determination circuit instructs the processor to execute the branch and the time when the instruction of the number of delay slots of the processor is executed. I have. That is,
The output signal of the latch is cleared when a branch is taken in any one of the cycles from one before the current execution cycle to the number of delay slots before the processor, and is set otherwise. It will be. Therefore, the branch information storage circuit can be configured with a simple configuration .

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle of delay branch control according to the present invention will be described.

As described in the section of the problem, in the processor of the delayed branch method, when the delayed branch instructions are consecutive, a complicated operation that significantly impairs the readability of the program at the assembler language level is a continuous operation. This is only when the branch condition is satisfied in both of the delayed branch instructions. On the other hand, the operation of the delayed branch instruction when the branch condition is not satisfied is the same as that of the NOP instruction (no operation instruction), which is equivalent to not executing anything.

Therefore, if the branch condition of the delayed branch instruction is satisfied, the readability of the program at the assembler language level will be significantly impaired if the delayed branch instruction placed in the delay slot is controlled so that the branch is not always taken. Such an operation can be avoided.

FIG. 1 is a diagram showing a configuration of a delay branch control circuit according to an embodiment of the present invention based on such a principle. In FIG. 1, reference numeral 11 denotes a shift register as a branch information storage circuit, 12 denotes an AND gate as a branch determination circuit that outputs a branch instruction signal SI, and 13 denotes an AND gate 1.
2 to the shift register 1
This is an inverter that inverts input to 1.

The shift register 11 is composed of a flip-flop of the number of delay slots of the processor, and inverts and holds the branch instruction signal SI via the inverter 13 every cycle, that is, every time an instruction is executed in the processor. Shift the signal. That is, the shift register 11 stores the presence or absence of a branch when the number of delay slots of the processor goes back in the past, and uses the stored information as a logical product gate 1 as a branch information storage signal SR.
Enter 2

The AND gate 12 determines that the branch condition in the branch instruction is satisfied, the branch taken execution signal SEa is input, and the branch information storage signal SR input from the shift register 11 indicates that no branch has occurred in the past. , The branch instruction signal SI is output.

That is, the delay branch control circuit shown in FIG.
The past branch occurrence information by the branch instruction is stored in the shift register 11 by the number of delay slots of the processor, and control is performed so that the branch is unconditionally unsatisfied while the shift register 11 stores the past occurrence of the branch. Things.

FIG. 2 is a diagram showing the operation of the delay branch control circuit shown in FIG. 1, and is a diagram showing the operation when the program shown in FIG. 11 is executed by pipeline processing. In FIG. 2, the number of delay slots of the processor is one. As shown in FIG. 2, when the delay branch control circuit shown in FIG. 1 is used, when the branch condition is satisfied, the branch is performed when the branch information stored in the shift register 11 is false, and when the branch information is true, Will not be taken. Therefore, when the delayed branch instructions are consecutive, the first branch instruction br
200, the second conditional branch instruction b
In r400, the branch is not always taken.

In the delay / branch control circuit shown in FIG. 1, a shift register 11 composed of flip-flops of several delay slots is provided in order to store branch information by the number of delay slots, but as shown in FIG. Counter 16 instead of 11 and RS latch 1 as a latch circuit
7 may be used. In the delay branch control circuit shown in FIG.
A branch information storage circuit is configured by the counter 16 and the RS latch 17, and the branch instruction signal SI
At the same time when the latch 17 is cleared, the counting operation of the counter 16 is started. The counter 16 performs a counting operation each time the processor executes an instruction, and sets the RS latch 17 when the counted value reaches the number of delay slots. That is, the output signal of the RS latch 17 is set only when a branch has not occurred when the number of delay slots goes back in the past. The output signal of the RS latch 17 is input to the AND gate 18 as a branch information storage signal SR, and the AND gate 18 controls the output of the branch instruction signal SI according to the branch information storage signal SR. As a result, the branch can be prohibited until the instruction of the number of delay slots is executed after the branch is performed.

In the delay branch control circuit shown in FIGS. 1 and 3, there is no need to take any special measures, even if the branch instruction is an unconditional branch instruction, assuming that the branch instruction is always a conditional branch instruction in which a branch is always taken.

It is not always necessary to store whether or not a branch has occurred for all cycles from one before the current execution cycle to before the number of delay slots of the processor.
Depending on the design of the processor, whether or not a branch has occurred in a part of the cycle from immediately before the current execution cycle to the number of delay slots before the processor may be used as the condition for prohibiting the branch. In this case, for example, the delay / branch control circuit shown in FIG. 1 stores only the output signal of the flip-flop constituting the shift register 11 corresponding to the cycle conditioned on the presence or absence of a branch in the branch information storage. What is necessary is just to input to the AND gate 12 as the signal SR.

Next, the principle of the condition flag rewriting control used in one embodiment of the present invention will be described.

The comparison instruction is an instruction for rewriting the condition flag, and is an instruction on the assumption that a conditional branch instruction is executed. Therefore, if control is performed such that rewriting of the condition flag is inhibited between the time when the condition flag is rewritten by the execution of the comparison instruction and the time when the condition flag is referred to by the execution of the conditional branch instruction, the comparison instruction and the branch condition instruction are controlled. Even if an operation instruction that normally involves an operation of rewriting the condition flag is executed during the period, whether the condition is satisfied or not can be determined based on the result of the comparison instruction.

[0042] Figure 4 is a diagram showing the condition flag rewriting control circuit based on such a principle, (a) shows the block diagram,
FIG. 2B is a diagram illustrating the operation of the circuit illustrated in FIG. FIG.
In (a), 21 receives a comparison execution signal SEc and a conditional branch execution signal SEb as inputs, and is set when a comparison instruction is executed, and is cleared when a conditional branch instruction is executed. Condition flag lock register, 22 is an inverting gate, 23 is an operation execution signal SE
A logical product gate as a rewrite determination circuit that receives d as an input, and outputs a condition flag rewrite signal SF instructing rewriting of a condition flag in accordance with an output signal of the condition flag lock register 21 when an operation instruction is executed.

The output signal of the condition flag lock register 21 becomes true by the execution of the comparison instruction, and becomes false by the execution of the conditional branch instruction. The output signal of the condition flag register 21 is inverted by the inversion gate 22 and input to the AND gate 23. Therefore, when the operation instruction is executed, the condition flag rewriting signal SF is output from the AND gate 23 only when the output signal of the condition flag lock register 21 is false.

Therefore, as shown in FIG. 4B, after the comparison instruction (CMP) is executed, the conditional branch instruction (B
Until R) is executed, the condition flag rewriting signal SF is not output because the condition flag register 21 is set even if the operation instruction (ADD) is executed, and the condition flag is not rewritten.

Further, in the pipeline type processor, the next instruction is decoded when executing the instruction, so that it is possible to know the type of the next instruction when executing the instruction. Taking advantage of this, the following two condition flag rewriting control methods can be considered.

Even if the condition flag is rewritten by the operation instruction, if the condition flag is not referenced by the conditional branch instruction, the rewriting of the condition flag is useless. Therefore, as a first method, when the next instruction is also an instruction for rewriting the condition flag in the execution cycle of the operation instruction, it is obvious that rewriting of the condition flag is useless. Control.

[0047] Figure 5 is a diagram showing a condition <br/> matter flag rewriting control circuit you realize such a first method, (a) shows the block diagram, (b) the circuit shown in (a) It is a figure which shows operation | movement. In FIG. 5A, a NOR gate 24 receives a comparison signal SDc indicating that the comparison instruction is in the decode stage and an operation signal SDd indicating that the operation instruction is in the decode stage, and receives the comparison signal SDc or the operation signal SDc.
When d is true, that is, when the comparison or operation instruction is in the decode stage, a signal is output to inhibit the condition flag from being rewritten by the operation instruction. The AND gate 25 outputs an operation execution signal SEd indicating that the operation instruction is in the execution stage.
When the operation execution signal SEd is true, that is, when the operation instruction is in the execution stage, the output signal is made true only when the output signal of the NOR gate 24 does not prohibit the condition flag from being rewritten. OR gate 26
Outputs the condition flag rewriting signal SF when the output signal of the AND gate 25 is true. That is, in the execution cycle of the operation instruction, the condition flag rewriting signal SF is output only when the next instruction to be executed is an instruction that does not rewrite the condition flag. OR gate 2
6 is a condition flag rewriting signal S whenever the comparison execution signal SEc indicating that the comparison instruction is in the execution stage is true.
Output F.

Therefore, as shown in FIG. 5B, even when there is an operation instruction (AD1) in the execution stage, the condition flag is not rewritten when there is an operation instruction (AD2) in the decode stage.

Also, as a second method, when the next instruction is a conditional branch instruction in the execution cycle of an operation instruction, it is clear that rewriting of the condition flag becomes effective. Control to rewrite.

[0050] Figure 6 is a diagram showing a condition <br/> matter flag rewriting control circuit you realize such a second method, (a) shows the block diagram, (b) the circuit shown in (a) It is a figure which shows operation | movement.
In FIG. 6A, the AND gate 27 outputs a conditional branch signal SD indicating that the conditional branch instruction is in the decode stage.
b and an operation execution signal SEd indicating that the operation instruction is in the execution stage, and when the conditional branch signal SDb and the operation execution signal SEd are both true, that is, the operation instruction is in the execution stage and the conditional branch instruction is in the decode stage. Sometimes, the output signal is made true. The OR gate 28 outputs the condition flag rewriting signal SF when the output signal of the AND gate 27 is true. That is, in the execution cycle of the operation instruction, the condition flag rewriting signal SF is output only when the next instruction to be executed is a conditional branch instruction. The OR gate 28 always outputs the condition flag rewriting signal SF when the comparison execution signal SEc indicating that the comparison instruction is in the execution stage is true.

Accordingly, as shown in FIG. 6B, when the execution instruction includes the operation instruction (AD1) in the execution stage and the decode stage includes the conditional branch instruction (BR), the condition flag is rewritten, but the execution stage includes the operation instruction. Instruction (AD
If 2) and there is no conditional branch instruction in the decode stage, the condition flag is not rewritten.

When the number of pipeline stages is deep, not only the instruction to be executed next but also the type of instruction to be executed thereafter can be known.
It goes without saying that rewriting of the condition flag can be controlled by the first or second method.

FIG. 7 is a block diagram showing a configuration of a pipeline type processor provided with a delay branch control circuit and a condition flag rewrite control circuit according to an embodiment of the present invention. In FIG. 7, portions other than those related to the delay branch control and the condition flag rewriting control are simplified.

In FIG. 7, an instruction memory 101 is a memory for storing an instruction code, and has a program counter (P
C) Output the instruction addressed from 102 to the instruction decoder 110. The instruction decoder 110 includes a branch instruction decoder 111, a comparison instruction decoder 112, and an operation instruction decoder 113. The branch instruction decoder 111 decodes a branch instruction among instructions input from the instruction memory 101, and outputs a branch signal SDb. At the same time, whether the branch is taken or not is determined by referring to the condition flag register 103. When the branch is taken, a branch taken signal SDa is output. The comparison instruction decoder 112 decodes the comparison instruction among the instructions input from the instruction memory 101 and outputs a comparison signal SD
Output c. The operation instruction decoder 113 is the instruction memory 1
It decodes an operation instruction among the instructions input from 01 and outputs an operation signal SDd. The branch establishment signal SDa, the branch signal SDb, the comparison signal SDc, and the operation signal SDd are timing signals of an execution stage by the delay circuit (FF) 104, respectively. The branch establishment execution signal SEa, the branch execution signal SEb, the comparison execution signal SEc, And the timing is adjusted to the operation execution signal SEd.

The delay / branch control circuit 120 employs the same configuration as the delay / branch control circuit shown in FIG. 1 and includes a branch information storage circuit 121 composed of one flip-flop, an inversion gate 122 and an AND gate 123. The branch taken execution signal SEa and the branch information storage circuit 121
The logical product signal of the inverted signal of the output signal of FIG.
I, and the selector 105 outputs the branch instruction signal SI
To select an input signal of the PC 102. The branch instruction signal SI is held by the branch information storage circuit 121.

The condition flag rewrite control circuit 130 is shown in FIG.
And the same configuration as the condition flag rewriting control circuit shown in FIG.
FIG. 4 shows an inversion gate 135 and an AND gate 133.
The same configuration as described above is realized, and the OR gate 136,
The same configuration as in FIG. 5 is realized by the inverting gate 132, the AND gate 133, and the OR gate 134.
The condition flag lock register 131 stores the comparison execution signal SE
c as a set signal and a branch execution signal SE
b is input as a clear signal and a condition flag lock signal is output. The AND gate of the inverted signal of the logical sum of the operation signal SDd and the comparison signal SDc, the inverted signal of the condition flag lock signal, and the operation execution signal SEd generated by the OR gate 136 and the inversion gate 132 1
33, the logical product signal and the comparison execution signal SE
The logical sum signal with c is output as the condition flag rewriting signal SF. The arithmetic unit 1 is operated by the condition flag rewriting signal SF output from the condition flag rewriting control circuit 130.
The operation of the condition flag generation circuit 141 in 40 and the update of the condition flag register 103 are controlled.

The operation of the delay branch control according to the embodiment of the present invention in the processor shown in FIG. 7 will be described with reference to the flowchart shown in FIG.

First, in step ST11, it is determined whether or not the instruction to be executed is a delayed branch instruction. If the instruction to be executed is not a delayed branch instruction, the procedure proceeds to step ST15. Naturally, the branch is not taken. If the instruction to be executed is a delayed branch instruction, the procedure proceeds to step ST12. In step ST12, it is determined whether the instruction executed one cycle before is a delayed branch instruction and whether or not the instruction has been branched. If the instruction is a delayed branch instruction and the branch is taken, the procedure proceeds to step ST15 and the branch is not taken. If not, the procedure proceeds to step ST13. In step ST13, it is determined whether a branch condition is satisfied. If the branch condition is satisfied, the process proceeds to step ST14. If the condition is not satisfied, the process proceeds to step ST15.

The specific operation of the processor shown in FIG. 7 is as follows. For example, when the delayed branch instructions are consecutive, and when the first delayed branch instruction does not branch, the branch instruction signal SI becomes false. Therefore, for the next delayed branch instruction, the output signal of the inverting circuit 122 connected to the branch information storage circuit 121 in the delayed branch control circuit 120 becomes true, so that it is determined whether or not to branch according to the branch establishment signal SEa. It is determined. On the other hand, when branching occurs in the first delayed branch instruction, the branch instruction signal SI becomes true, so that the next delayed branch instruction is inverted by the inversion connected to the branch information storage circuit 121 in the delayed branch control circuit 120. Since the output signal of the circuit 122 becomes false, the branch instruction signal SI becomes false irrespective of the branch establishment signal SEa and does not always branch. That is, when the delayed branch instructions are consecutive, the first delayed branch instruction apparently performs the same operation as the non-delayed branch instruction.

In the processor shown in FIG. 7, the number of delay slots is assumed to be one, and the branch information storage circuit 121 is constituted by one flip-flop. As shown in FIG. 3, a shift register 11 composed of flip-flops of several delay slots is provided, and an AND signal of the output signals of each flip-flop is used as a prohibition signal of the branch establishment execution signal SEa, or as shown in FIG. And RS latch 17
It is needless to say that this can be realized by providing.

[0061] Next, the operation of the condition flag rewriting control that put the processor shown in FIG. 7, with reference to the flowchart shown in FIG.

First, in step ST21, the type of instruction to be executed is checked. Step S for conditional branch instruction
Proceeding to T22, the condition flag lock register 131 is cleared. In the case of a comparison instruction, the progress condition flag lock register 131 is set in step ST23, and the progress condition flag is rewritten in step ST26. If the instruction is an operation instruction, the process proceeds to step ST24, and the authenticity of the output signal of the condition flag lock register 131 is determined. When the output signal of the condition flag lock register 131 is true, the process proceeds to step ST27, and the condition flag is not rewritten. On the other hand, when the output signal of the condition flag lock register 131 is false, the process proceeds to step ST25, and it is determined whether or not the next instruction to be executed is an instruction for rewriting the condition flag, that is, an operation or comparison instruction. If the instruction is for rewriting the condition flag, the procedure proceeds to step ST27, and the condition flag is not rewritten. Otherwise, the procedure proceeds to step ST26, and the condition flag is rewritten.

As a specific operation of the processor shown in FIG. 7, for example, when the condition flag is rewritten by the comparison instruction, the condition flag lock register 131 is set by the comparison execution signal SEc, and then the condition branch instruction or the like is set. The condition flag rewrite control signal SF becomes false until the condition flag lock register 131 is cleared by an instruction referring to the condition flag of (1), and the operation of the condition flag generation circuit 141 and the update of the condition flag register 103 are stopped.

When the operation commands are continuous, the logical product gate 133 takes the logical product of the inverted signal of the operation signal SDd and the operation execution signal SEd, so that the condition flag rewrite control signal SF becomes false. Then, the operation of the condition flag generation circuit 141 and the update of the condition flag register 103 are stopped.

As described above, according to the delayed branch control according to the present embodiment, the readability of the program at the assembler language level can be maintained even when the delayed branch instructions are consecutive. Further, a circuit for realizing the delay branch control method according to the present embodiment can be realized by a simple configuration.
In the case of (1), it can be realized by a small-scale circuit of one flip-flop with inverted output and one AND gate.

According to the condition flag rewriting control according to the present embodiment, the condition flag rewriting can be efficiently controlled without providing a condition flag rewriting control bit in the instruction code. Level programming and compiler creation,
Further, the power consumed by the operation of the condition flag generation circuit and the update of the condition flag register in the operation unit can be suppressed. Normally, operation instructions occupy about 80% of the total operation cycle in a program, and branch instructions account for 20%.
Since the number of cycles is about 80%, the number of cycles for operating the condition flag generation circuit and updating the condition flag register can be reduced from 80% to 20%.

[0067]

As described above, according to the delayed branch control according to the present invention, the case where the branch condition is satisfied for both the delayed branch instructions that are continuous or relatively close to the number of delay slots of the processor. However, the order of execution of the instructions is not complicated, so that the program at the assembler language level becomes easier to read. Moreover, there is no need to provide a control bit in the instruction code .

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a delay branch control circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operation of the delay branch control circuit according to the embodiment of the present invention shown in FIG. 1;

FIG. 3 is a diagram illustrating another example of the delay branch control circuit according to the embodiment of the present invention;

[Figure 4] is a diagram showing a condition flag rewriting control circuit used Oite to an embodiment of the present invention, (a) is a block diagram,
(B) is a diagram showing the operation.

[Figure 5] is a diagram showing another example of a condition flag rewriting control circuit used Oite to an embodiment of the present invention, showing (a) is a structural view, the (b) operation.

[Figure 6] is a diagram showing another example of a condition flag rewriting control circuit used Oite to an embodiment of the present invention, showing (a) is a structural view, the (b) operation.

FIG. 7 is a block diagram showing a configuration of a pipeline type processor including a delay branch control circuit and a condition flag rewrite control circuit according to an embodiment of the present invention.

8 is a flowchart illustrating a delay branch control method according to an embodiment of the present invention in the processor illustrated in FIG. 7;

9 is a flowchart showing the condition flag rewriting control how put the processor shown in FIG.

FIG. 10 is a diagram showing the operation of pipeline processing when executing a branch instruction.

FIG. 11 is a diagram illustrating an example of an assembler language level program in a case where delayed branch instructions are consecutive;

FIG. 12 is a diagram showing a state in which the program shown in FIG. 11 is executed.
FIG. 7 is a diagram illustrating a relationship between the presence or absence of a branch and the execution order of instructions in each delayed branch instruction.

FIG. 13 shows a case where the program shown in FIG. 11 is executed.
FIG. 11 is a diagram illustrating the operation of pipeline processing when a branch condition is satisfied for both successive delayed branch instructions.

FIG. 14 shows the relationship between the presence or absence of a branch in each delayed branch instruction and the instruction execution order when the program shown in FIG. 11 is executed by a processor that executes an instruction code provided with a delayed branch control bit. FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Shift register (branch information storage circuit) 12 AND gate (branch determination circuit) 16 Counter 17 RS latch (latch circuit) 18 AND gate (branch determination circuit) 21 Condition flag lock register (condition flag lock circuit) 23 Logical product Gate (Rewrite determination circuit) 120 Delay branch control circuit 130 Condition flag rewrite control circuit

Claims (6)

(57) [Claims] 1. A delayed branch control method for controlling a branch operation of a delayed branch instruction in a processor of a delayed branch method, wherein when a delayed branch instruction is executed, the delay branch instruction is executed immediately before an execution cycle of the delayed branch instruction. A delayed branch control method, wherein when a branch is taken in a predetermined cycle among cycles up to the number of delay slots before the processor, the branch by the delayed branch instruction is prohibited. 2. The delay branch control method according to claim 1, wherein all the cycles from one cycle before the execution cycle of the delayed branch instruction to the number of delay slots before the processor are set as the predetermined cycle. A delayed branch control method. 3. A delay branch type processor, wherein:
A delay branch control circuit for controlling a branch operation of a delay branch instruction, wherein a branch is performed in a predetermined cycle among cycles from one immediately before a current execution cycle to before a delay slot number of the processor. A branch information storage circuit that stores a condition that when a delayed branch instruction is executed, a branch condition of the delayed branch instruction is satisfied, and that the branch information storage circuit does not branch in the predetermined cycle. And a branch determination circuit for instructing the processor to branch only when the branch is being performed. 4. The delay branch control circuit according to claim 3 , wherein said branch information storage circuit regards all cycles from one immediately before a current execution cycle to before a delay slot number of said processor as said predetermined cycle. And a delay branch control circuit. 5. The delay branch control circuit according to claim 4 , wherein said branch information storage circuit comprises a number of flip-flops connected in series and corresponding to the number of delay slots of said processor. A delay branch control circuit, comprising: a shift register that inputs an output signal of the branch determination circuit and shifts a held signal every time the branch determination circuit is executed. 6. The delay branch control circuit according to claim 4 , wherein the branch information storage circuit starts counting the number of executed instructions in the processor when the branch determination circuit instructs the processor to branch. A counter that terminates counting when the count value reaches the number of delay slots of the processor; an output signal that clears an output signal when the branch determination circuit instructs the processor to perform branching, and an output when the counting of the counter ends. And a latch circuit for setting a signal.