JP2939043B2 - Active matrix substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a display panel of a liquid crystal television receiver, a word processor, a computer terminal display device, or the like. The present invention relates to an active matrix substrate for applying a voltage to a substance whose optical properties change, for example, a liquid crystal.

[0002]

2. Description of the Related Art FIG. 4 is a plan view showing a schematic structure of an active matrix substrate 50 on which the present invention is based, and FIG.
It is a schematic perspective view which shows arrangement | positioning of 8. FIG.

In an active matrix substrate 50, a plurality of pixel electrodes 52 and switching elements 53 for controlling a voltage applied to the pixel electrodes 52 are formed in a matrix on a surface of an insulating substrate 51.

The switching element 53 for selectively driving the picture element electrode 52 includes a TFT (thin film transistor) element and a MOS element.
A three-terminal element such as an FET (metal oxide semiconductor field effect transistor) element, or a two-terminal element such as an MIM (metal-insulating layer-metal) element, a diode, and a varistor are used.

When the switching element 53 is a three-terminal element, a plurality of data lines 54 and scanning lines 55 are formed on the substrate on which the picture element electrodes 52 are formed in a grid pattern orthogonal to each other. The source is connected to the data line 54, the gate is connected to the scanning line 55, and the drain is connected to the pixel electrode 52. As shown in FIG. , A uniform counter electrode 56 is formed over the entire surface. When color display is performed, the color filters 57B, 57G, and 57R are formed in a staggered lattice.

When the switching element 53 is a two-terminal element, a plurality of scanning lines 55 are formed in parallel on the substrate on which the picture element electrodes 52 are formed, and one terminal of the two-terminal element is connected to the scanning line 55. The other terminal is connected to each of the picture element electrodes 52, and a counter substrate facing the picture element electrodes 52 via a liquid crystal or the like is provided with a counter picture element electrode corresponding to each picture element and a plurality of parallel connecting picture elements. Data lines are formed orthogonal to the scanning lines.

In the active matrix system, when the number of scanning lines is m and the number of data lines is n, m × n picture element electrodes can be driven in a matrix by time-divisionally scanning them. In general, a dot-sequential driving method for sequentially transferring display data for each picture element or a line-sequential driving method for sequentially transferring display data for each scanning line is used.

Hereinafter, an example in which the switching element 53 is a three-terminal element as shown in FIG. 4 will be described.

On a part of the active matrix substrate 50, a first clock signal line 61 and a second clock signal line 6 through which first and second clock signals having phases opposite to each other are transmitted.
2 and a logic circuit 60 for generating a scanning line control signal for transmitting the driving timing of each scanning line 55 using each clock signal.
Are formed. The logic circuit 60 includes a scanning line driving circuit 70 for controlling an applied voltage for each scanning line and the like. In addition, a power supply line 65 and a ground line 64 for supplying a constant voltage to each scanning line driving circuit 70, A control line 63 for transmitting a scanning line control signal is formed between the line driving circuits 70, and the first clock signal line 61 and the second clock signal line 6
2. The control line 63, the power supply line 65, and the ground line 64 are connected to electrodes 61a formed on the end of the active matrix substrate.
62a, 63a, 65a, and 64a, respectively.

FIG. 6 shows an example of a conventional scanning line driving circuit 70. As shown in FIGS. 3A and 3B, two-phase clock signals φ1 and φ2 having phases opposite to each other are transmitted to the first clock signal line 61 and the second clock signal line 62, respectively. A scanning line control signal STP for transmitting the scanning line driving timing is transmitted to the control line 63 from the preceding scanning line driving circuit.

The operation of the scanning line driving circuit 70 will be described. A shift register circuit is constituted by analog switches 71, 74, 75, 78 and inverters 72, 73, 76, 77, and the scanning line control signal STP is controlled from the preceding stage. When one pulse is input through the line 63, the clock signal φ1
Becomes H (high level), the analog switch 71 conducts, is input to the inverter 72, and outputs L (low level). At this time, the inverter 73 outputs H, but since the clock signal φ2 is L, the analog switches 74 and 75 are off.

Next, when the clock signal φ1 is inverted to L and the clock signal φ2 is inverted to H, the analog switch 71
Is turned off, and the analog switches 74 and 75 are turned on, so that the input of the inverter 72 is maintained at H, L is input to the inverter 76, the output thereof is H, and the inverter 77 outputs L. Therefore, the scanning line control signal STP transmitted by the control line 63 connected to the scanning line driving circuit of the next stage becomes H, and outputs H to the scanning line 55 via the buffers 79 and 80 to output the scanning line control signal STP. The switching element 53 connected to 55 is made conductive.

Next, when the clock signal φ1 is inverted to H and the clock signal φ2 is inverted to L, the analog switch 7
When the analog switches 74 and 75 are turned off and the analog switches 74 and 75 are turned off, the input of the inverter 76 is held at L, the scan line control signal STP to the next stage is held at H, and scanning from the previous stage is performed. When the line control signal STP becomes L, L is inputted to the inverter 72 and the output thereof becomes H.

Next, when the clock signal φ1 is inverted to L and the clock signal φ2 is inverted to H, the analog switch 7
When the analog switches 74 and 75 are turned on and the analog switches 74 and 75 are turned on, H is input to the inverter 76, the scanning line drive signal STP to the next stage becomes L, and the switching element connected to the scanning line 55. 53 is shut off.

As described above, the scanning line control signal ST from the preceding stage is
When a pulse that is H at the rising of the clock signal φ1 and L at the next rising is input as P, a pulse having a time width of one cycle of the clock is output to the scanning line 55, and the next scanning is performed. In the line drive circuit, a similar pulse is output to the scan line after being delayed by one cycle of the clock, so that the logic circuit 60 can sequentially scan each scan line for each cycle of the clock. The conduction time of each switching element is set in a range from 15 μsec to 100 μsec.

FIG. 7 shows the scanning line driving circuit 70 shown in FIG.
FIG. 3 is a front view showing a part of a conductor near an input unit of the shift register circuit of FIG. Portion 90 surrounded by a two-dot chain line in FIG.
Corresponds to a portion 90 surrounded by a two-dot chain line in FIG. 6, in which the conductors of the first clock signal line 61 and the second clock signal line 62 are formed in parallel, and the first clock signal line 61
Of the second clock signal line 62 intersect with the conductor of the second clock signal line 62 via the insulating film, and further the scanning line control signal ST
It intersects with the conductor of the control line 63 through which P is transmitted via an insulating film. The wiring structure of the conductor is a metal film composed of a lower metal film made of Ta, Al, etc., an insulating film made of SiN _x , SiO ₂ , etc., and an upper metal film made of Ti, Mo, etc. FIG. 7 shows a three-layer structure of the film.
In, for example, the first clock signal line 61 and the second
The clock signal line 62 is wired with a lower metal film. When the branch of the first clock signal line 61 intersects with the second clock signal line 62, the clock signal line 62 is wired with an upper metal film via a contact hole 82. The hole 63 connects to the lower metal film. Similarly, the control line 63 is wired with an upper metal film, and is capacitively coupled to the first clock signal 61 via an insulating film to generate a coupling capacitance 81 at an intersection area of a perspective portion, and is connected to the analog switch 71. .

[0017]

However, in the conventional scanning line driving circuit, the generation of the intersection region between the clock signal line and the scanning line cannot be avoided in the active matrix system in which the scanning lines are sequentially driven.

An analog switch, an inverter and the like constituting the scanning line driving circuit 70 are generally formed in the same circuit form as a switching element for controlling a picture element electrode.
In particular, when a TFT or MOSFET is used as a switching element, the control line 63 has a high impedance because the on-resistance of the analog switch 71 is relatively high. Therefore, the control line 63 is in a state where signals from other conductors are apt to be mixed. When the control line 63 is capacitively coupled to the first clock signal line 61, as shown in FIG. There is a problem that an abnormal pulse is generated due to the superposition of the above pulse waveform, and the logic circuit 60 malfunctions.

It is an object of the present invention to solve the above-mentioned problems by providing a clock to a scanning line control signal for controlling a scanning line when a switching element for controlling a voltage applied to a plurality of picture element electrodes is driven in a matrix. An object of the present invention is to provide an active matrix substrate that can eliminate superposition of signals and prevent a malfunction of a logic circuit.

[0020]

According to the present invention, a plurality of picture element electrodes and switching elements for controlling a voltage applied to the picture element electrodes are formed in a matrix on an insulating substrate. A plurality of scanning lines for driving the first and second clock signals, and a first clock signal line and a second clock signal line through which first and second clock signals having phases opposite to each other are transmitted, and using the first and second clock signals. In an active matrix substrate on which a logic circuit for generating a scanning line control signal for transmitting a driving timing of a scanning line is formed, a conductor transmitting the scanning line control signal crosses a conductor of the first clock signal line via an insulating film. An active matrix, wherein the first coupling capacitance is formed by the first coupling capacitance, and the second coupling capacitance is formed by overlapping with the conductor of the second clock signal line via the insulating film. Box board.

[0021]

According to the present invention, the conductor transmitting the scanning line control signal crosses the conductor of the first clock signal line via the insulating film to form a first coupling capacitor, and the second clock signal via the insulating film. By forming the second coupling capacitance by overlapping with the conductor of the signal line, even if one clock signal is superimposed on the scanning line control signal via one coupling capacitance, another clock signal having the opposite phase is generated. Since the clock signal is superimposed on the scanning line control signal via the other coupling capacitor, the superimposed clock signal can be canceled out, and occurrence of an abnormal pulse can be prevented.

[0022]

FIG. 1 is a circuit diagram of a scanning line driving circuit 10 constituting an active matrix substrate according to an embodiment of the present invention. The configuration of the scanning line driving circuit 10 is the same as that shown in FIG.
And a shift register circuit including inverters 12, 13, 16, and 17, and buffers 19 and 20, and a first clock signal line 1 and a second clock signal line 2
, Clock signals φ1 and φ2 having opposite phases are transmitted to each other, and a scanning line control signal STP for transmitting the driving timing of the scanning line is transmitted to the control line 3 from the preceding scanning line driving circuit. Note that the point that a coupling capacitor 22 is formed between the control line 3 and the second clock signal line is different from the conventional one.

Each of the analog switches 11, 14, 15, 1
8. The active elements constituting the inverters 12, 13, 16, 17 and the buffers 19, 20 may have the same element configuration as the switching elements for controlling the pixel electrodes in order to simplify the manufacturing process of the active matrix substrate. preferable.

The operation of the scanning line driving circuit 10 is the same as that described above. As the scanning line control signal STP from the preceding stage, a pulse which becomes H at the rising of the clock signal φ1 and becomes L at the next rising is input. When done, clock 1
A pulse having a time width corresponding to one cycle is output to the scanning line 5, and a similar pulse is output to the scanning line after being delayed by one cycle in the next scanning line driving circuit.
The logic circuit 60 can sequentially scan each scanning line every clock cycle.

By transmitting a video signal corresponding to each picture element via a plurality of data lines 54 in synchronization with such scanning of each scanning line, a two-dimensional display of a video can be performed.

FIG. 2A is a front view showing a part of the conductor near the input part of the shift register circuit of the scanning line driving circuit shown in FIG. 1, and FIG. 2B is a front view. A) AA ′
It is sectional drawing. Part 3 surrounded by a two-dot chain line in FIG.
0 corresponds to a portion 30 surrounded by a two-dot chain line in FIG. 1, and the wiring structure of the conductor is formed on an insulating substrate 31 such as glass or quartz in the same manner as shown in FIG. A lower metal film 32 made of Ta, Al or the like is formed by sputtering or the like, an insulating film 33 made of SiN _x , SiO ₂ or the like is formed by plasma CVD or the like, and an upper metal film 34 made of Ti, Mo or the like is formed by sputtering or the like. It has a three-layer structure of a metal film-insulating film-metal film as a whole, and the pattern of each layer is formed by plasma etching or the like. The analog switch 11 has the same configuration as a switching element for controlling a voltage applied to a pixel electrode, and has a gate electrode 11a made of Ta, Al, or the like.
And an insulating film 11b made of SiN _x , SiO _2, etc.
Functional film 11 made of amorphous Si, polycrystalline Si, etc.
and a source electrode 11d and a drain electrode 11e made of Ti, Mo, or the like.

The first clock signal line 1 and the second clock signal line 2 are wired with a lower metal film, and
When the branching crosses with the second clock signal line 2, it is wired to the upper metal film via the contact hole 23 and further connected to the lower metal film via the contact hole 24.
Similarly, the control line 3 is wired with an upper metal film, is capacitively coupled to the first clock signal line via an insulating film, and generates a coupling capacitance 21 in the crossing area of the perspective portion, and is connected to the analog switch 11. At the same time, it branches off in the middle, and is capacitively coupled to the second clock signal line 2 via the insulating film, so that a coupling capacitance 22 is formed at the intersection region of the perspective portion.

FIG. 3 is a timing chart showing the waveform of each signal of the scanning line driving circuit. Since the control line 3 and the first clock signal line 1 are capacitively coupled by the coupling capacitance 21, the pulse waveform of the clock signal φ1 is superimposed on the scanning line control signal STP transmitted to the control line 3, but on the other hand, the control line 3 and the second clock signal line 2 are also capacitively coupled by the coupling capacitance 22, so that the clock signal φ2 having the opposite phase is superimposed on the scanning line control signal STP transmitted to the control line 3, and as a result, the clock signal φ1 3 and the superimposed pulse of the clock signal φ2 cancel each other, and the scanning line control signal STP can maintain a normal pulse waveform (see FIG. 3 (4)). Therefore, malfunction of the logic circuit 60 due to abnormal pulse generation can be prevented.

In the above embodiment, the control line 3 to which the scanning line control signal STP is transmitted is connected to the first clock signal line 1
And the second clock signal line 2 is capacitively coupled at one location each. However, capacitive coupling may be performed at two or more locations, and abnormalities may be obtained by adjusting the sum of the coupling capacitances. Pulse generation can be similarly prevented.

The present invention can be similarly applied to a display panel or the like in which a switching element for controlling a voltage applied to a picture element electrode is a two-terminal element and a data line is formed on a counter substrate.

[0031]

As described in detail above, according to the present invention,
The conductor transmitting the scanning line control signal intersects the conductor of the first clock signal line via the insulating film to form a first coupling capacitance, and overlaps the conductor of the second clock signal line via the insulating film to form the second coupling capacitor. By forming the coupling capacitance, the superposition of the two clock signals is cancelled, and abnormal pulse generation can be prevented, and malfunction of the logic circuit can be reliably prevented with a simple configuration. Further, since the present invention can be realized only by modifying the shape of the conductor of the control line, it is possible to suppress an increase in the manufacturing cost of the active matrix substrate.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a scanning line driving circuit constituting an active matrix substrate according to an embodiment of the present invention.

FIG. 2 is a front view showing a part of a conductor near an input part of a shift register circuit of the scanning line driving circuit shown in FIG. 1;

FIG. 3 is a timing chart showing waveforms of signals of a scanning line driving circuit.

FIG. 4 is a front view showing a schematic configuration of an active matrix substrate on which the present invention is based.

FIG. 5 is a schematic perspective view showing an arrangement of an active matrix substrate and a counter substrate.

FIG. 6 is an example of a conventional scanning line driving circuit.

FIG. 7 is a front view showing a part of a conductor near an input part of a shift register circuit of the scanning line driving circuit shown in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st clock signal line 2 2nd clock signal line 3 control line 5 scanning line 10 scanning line drive circuit 11,14,15,18 analog switch 12,13,16,17 inverter 19,20 buffer 21,22 coupling capacity 23 , 24 contact holes

──────────────────────────────────────────────────続 き Continued on front page (72) Inventor Hiroshi Fujiki 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Yoshiharu Kataoka 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Sharp Corporation No. (72) Inventor Makoto Miyago 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Sharp Corporation (56) References JP-A-2-3008 (JP, A) JP-A-49-114333 (JP, A) (58) Field surveyed (Int.Cl. ⁶ , DB name) G09G 3/36 G02F 1/133 G02F 1/1333 G02F 1/1345

Claims (1)

(57) [Claims] A plurality of pixel electrodes and switching elements for controlling a voltage applied to the pixel electrodes are formed in a matrix on an insulating substrate, and a plurality of scans for driving the switching elements are provided. A first clock signal line and a second clock signal line through which first and second clock signals having phases opposite to each other are transmitted; and a scan transmitting drive timing of the scanning line using the first and second clock signals. An active matrix substrate on which a logic circuit for generating a line control signal is formed;
An active matrix substrate, wherein a first coupling capacitance is formed by intersecting with a conductor of a clock signal line, and a second coupling capacitance is formed by overlapping with a conductor of a second clock signal line via an insulating film. .