JP3056833B2 - Automatic gain control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

 [Object of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit for keeping an output constant with respect to a fluctuating input, for example.
In particular, in electronic devices that handle media such as banknotes and printed materials, they are used for the purpose of compensating for variations in the elements of an optical sensor used for determining the presence or absence of a medium and reading the surface, and changes in characteristics due to environment such as temperature and humidity. Automatic
The present invention relates to a gain control circuit.

[0002]

2. Description of the Related Art As is well known, in an electronic apparatus for handling a medium such as a bill and a printed matter, an optical sensor is often used for discriminating the presence or absence of the medium and reading the surface.
In this case, automatic gain control is performed to compensate for variations in the characteristics of the optical sensor and changes in characteristics due to the environment such as temperature and humidity.
A circuit (hereinafter, referred to as an AGC circuit) is used.

Conventionally, AGC circuits generally change the gain of an analog amplifier in accordance with the output. That is, in a general AGC circuit, the gain of an analog amplifier is changed at a speed according to a time constant determined by a capacitor and a resistor in accordance with an output.

However, in the case of this type of AGC circuit, it is very difficult to control the response speed and the reference value by software, and when the input fluctuates greatly, oscillation is likely to occur. Met.

[0005]

As described above, conventionally, it is very difficult to control the response speed and the reference value by software, and when the input fluctuates greatly, oscillation is likely to occur. There is a disadvantage that the operation is extremely unstable. Accordingly, it is an object of the present invention to provide an automatic gain control circuit which can be easily controlled by software and has a stable operation.

[0006]

To achieve the above object, according to the Invention The, in the automatic gain control circuit of the present invention, analog
Analog signal input terminal and control input terminal
Analog signal from input terminal and reference potential of control input terminal
Output as a digital output signal by comparing
Converter and the digital output signal from this AD converter
Signal so that the output signal of the AD converter has a desired value.
From a storage medium in which reference values for controlling
The ratio by comparison means and, the comparing means for the reference value of the comparison
As a result of the comparison, the digital output signal of the AD converter is
If it is larger than the reference value, add and count
If the digital output signal is smaller than the reference value
The digital output signal of the AD converter is subtracted and counted.
When the count value is equal to the reference value, the counting means holds the count value as it is, and the count value of the counting means is converted into an analog signal.
And the output signal is controlled by the AD converter.
DA converter for feedback input to input terminal as reference potential
And a clock signal to each of the means,
By stopping the clock supply, the automatic gain control
Is constituted whether <br/> et clock supply means for holding the state of the control circuit constant.

Further, in the automatic gain control circuit according to the present invention, a first circuit for selecting one from a plurality of analog signals is provided.
Selection means, an analog signal input terminal and a control input terminal
And an analog signal selected by the first selecting means.
Analog signal from input terminal and reference potential of control input terminal
Output as a digital output signal by comparing
An inverter, a setting means for setting a reference value for controlling an output signal from the AD converter to a desired value, respectively corresponding to the plurality of analog signals, and the first selection means by the setting means. Means for selecting a reference value corresponding to the analog signal selected by the means, and the reference value selected by the second selection means and the AD converter.
Comparing means for comparing the output signal from the analog-to-digital converter with the digital output signal of the AD converter.
If the signal is larger than the reference value, the addition
The digital output signal of the converter is smaller than the reference value
If not, count down and digital output of AD converter
If the signal is equal to the reference value, the count value is kept as it is.
Counting means for lifting, the count value of the counting means, memory means for correspondingly storing each of the plurality of analog signals, from the storage means, corresponding to the analog signal selected by the first selection means a third selecting means for selecting a count value, the count value selected by the third selection means Ana
The signal is converted to a log signal, and the output signal is
The feedback input is applied to the control input terminal of the converter as the reference potential.
And a clock signal to each of the means.
Power supply and stop the clock supply.
To keep the state of the automatic gain control circuit constant.
And a lock supply means .

[0008]

According to the present invention, an analog signal can be converted into a numerical value and handled by the means described above, so that the operation can be controlled using the numerical value.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows an AGC circuit according to the present invention.

That is, the AGC circuit includes, for example, an input terminal 1 for inputting an analog signal as an optical sensor output, an AD converter 2 as a converting means, a DA converter 4 as a feedback means, and a counter 5 as a counting means. , Comparator 6 as comparison means, storage medium 7, clock generator 8, and clock generator 8
Is constituted by a control terminal 9 for varying the cycle of the clock signal generated. 3 is the AG
The desired controlled output value of the C circuit. The AD converter 2 converts an analog signal from the input terminal 1 into a numerical value based on a control input. Comparator 6
Is for comparing the output of the AD converter 2 with a reference value preset in the storage medium 7. The storage medium 7 stores, for example, data for controlling the output of the AD converter 2 to a desired value as a reference value.

The counter 5 increases or decreases the count value in accordance with the result of the comparator 6.
When the digitized output from the converter 2 is smaller than the reference value, 1 is subtracted from the count value. Conversely, when the digitized output from the AD converter 2 is larger than the reference value, the count value is subtracted. Is incremented by one. When the digitized output from the AD converter 2 is equal to the reference value, the count value is held as it is. The counter 5 is designed not to reset (0) when counting a value exceeding the maximum countable value. The DA converter 4 converts the count value of the counter 5 into a voltage, and feeds it back as a reference potential as a control input of the AD converter 2.

The clock generator 8 generates a clock signal for AGC operation, which is supplied to the above-described units. The clock generator 8 can continuously generate a plurality of clock signals at an arbitrary clock cycle. Next, the operation in the above configuration will be described.

An analog signal from the input terminal 1 is digitized by an AD converter 2. This digitized output is supplied to a comparator 6 where it is compared with a reference value stored in a storage medium 7.

When the digitized output from the AD converter 2 is smaller than the reference value of the storage medium 7 as a result of the comparison by the comparator 6, 1 is subtracted from the count value of the counter 5.
When the digitized output is larger than the reference value, 1 is added to the count value of the counter 5. Further, when the digitized output is equal to the reference value, the count value of the counter 5 is not changed and is kept as it is.

The count value of the counter 5 is converted by the DA converter 4 into a voltage proportional to the value. Thereafter, it is fed back as the control input (reference potential) of the AD converter 2 described above.

Accordingly, when the digitized output from the AD converter 2 is larger than the reference value of the storage medium 7, A
The reference potential of the D converter 2 increases, and the output of the AD converter 2 decreases. If the digitized output from the AD converter 2 is smaller than the reference value of the storage medium 7, the reference potential of the AD converter 2 is lowered, and the output of the AD converter 2 is increased.

This series of operations is performed once for each cycle of the clock signal from the clock generator 8. Therefore, by continuously supplying the clock signal from the clock generator 8, the above-described operation is repeated at a cycle corresponding to the clock cycle. As a result, AD
The output value 3 of the converter 2 is changed at a following speed according to the cycle of the clock signal until the output value 3 becomes equal to the reference value set in the storage medium 7. After the output value 3 of the AD converter 2 is made equal to the reference value, the output value 3 is kept constant.

In this embodiment, the clock cycle of the clock generator 8 can be changed using the control terminal 9. For this reason, it is possible to easily change the follow-up characteristic with respect to the input fluctuation, and when the input fluctuates greatly, it is possible to perform control such as reducing the follow-up speed to prevent oscillation. By stopping the generation of the clock signal from the clock generator 8, the state of the AGC circuit can be kept constant. As described above, an analog signal can be handled by being digitized.

That is, a desired controlled output value is obtained after digitizing the input. This allows
It is easy to set the time constant and the like, and it is possible to control the operation using numerical values, which is resistant to errors and the like. Therefore, it is possible to easily perform software control of the reference of the output and the follow-up characteristic with respect to the fluctuation of the analog signal, and to make the operation of the AGC circuit more stable. Next, another embodiment of the present invention will be described.

FIG. 2 shows an example in which one AGC circuit can be shared by a plurality of inputs and outputs using an analog switch and a data selector.
In the example of this figure, a case where there are four inputs will be described.

That is, this AGC circuit has, for example, input terminals 1a to 1d for inputting an analog signal as an optical sensor output, an AD converter 2 as a conversion means,
DA converter 4 as feedback means, counter 5 as counting means, comparator 6 as comparing means, storage medium 7 as setting means, clock generator 8, for example, memory 10 as storage means, as first selecting means It comprises an analog switch S1, a data selector S2 for selecting one of the output values 3a to 3d, a data selector S3 as second selecting means, and data selectors S4 and S5 as third selecting means. The AD converter 2 digitizes analog signals from the input terminals 1a to 1d based on control inputs. The comparator 6 compares the output of the AD converter 2 with one of the reference values preset in each of the storage units 7a to 7d of the storage medium 7.

The storage medium 7 has a plurality (four in this case) of storage units 7a to 7d.
It stores data for controlling the output of the D converter 2 to have a desired value.

The counter 5 increases or decreases the count value in accordance with the result of the comparator 6.
When the digitized output from the converter 2 is smaller than the reference value, 1 is subtracted from the count value. Conversely, when the digitized output from the AD converter 2 is larger than the reference value, the count value is subtracted. Is incremented by one. When the digitized output from the AD converter 2 is equal to the reference value, the count value is held as it is. The counter 5 is designed not to reset (0) when counting a value exceeding the maximum countable value. The DA converter 4 converts the count value of the counter 5 into a voltage, and feeds it back as a reference potential as a control input of the AD converter 2.

The clock generator 8 generates a clock signal for AGC operation, which is supplied to the above-described units. The clock generator 8 can continuously generate a plurality of clock signals at an arbitrary clock cycle.

The memory 10 has a plurality of (here, four) storage units 10a to 10d, and stores, for example, data (reference potential) for controlling the control input of the AD converter 2 as a count value. Things. This count value is rewritten according to the output from the counter 5. The analog switch S1 selects one of the input terminals 1a to 1d. The data selector S2 selects one of the output values 3a to 3d. The data selector S3 is provided in each storage unit 7a of the storage medium 7.
To select one of the reference values stored in .about.7d. The data selectors S4 and S5 select one of the count values stored in each of the storage units 10a to 10d of the memory 10.

Here, the combination when the input terminal 1a, the output value 3a, the storage unit 7a of the storage medium 7, and the storage unit 10a of the memory 10 are selected by the analog switch S1 and the data selectors S2 to S5 is described as a channel. a, similarly, the combination when the input terminal 1b, the output value 3b, the storage unit 7b of the storage medium 7 and the storage unit 10b of the memory 10 are respectively selected is channel b, input terminal 1
c, output value 3c, storage unit 7c of storage medium 7, memory 10
The combination when each of the storage units 10c is selected is the channel c, the input terminal 1d, the output value 3d, the storage medium 7
A combination when the storage unit 7d of the memory 10 and the storage unit 10d of the memory 10 are selected will be described below as a channel d. FIG. 3 shows an operation example of the analog switch S1 and the data selectors S2 to S5.

In the figure, S is a clock signal supplied from the clock generator 8, and A to D are selection signals of four channels a to d by the analog switch S1 and the data selectors S2 to S5.

In this case, for example, when the selection signal A is turned on, the analog switch S1 has the input terminal 1a, the data selector S2 has the output value 3a, the data selector S3 has the storage section 7a of the storage medium 7, and the data selector S4. S5 indicates that the operation is performed to select each of the storage units 10a of the memory 10. That is, the analog switch S
1 and the data selectors S2 to S5 are connected to the channel a from the channel b or from the channel b to the channel c every one cycle of the clock signal from the clock generator 8.
, Or from channel c to channel d, or from channel d to channel a. The switching operation is repeated every four cycles of the clock signal from the clock generator 8.

For example, the analog switch S1 has the input terminal 1a, the data selector S2 has the output value 3a, the data selector S3 has the storage section 7a of the storage medium 7, and the data selectors S4 and S5 have the storage section 10a of the memory 10. In each selected state, the clock generator 8
Assume that a clock signal for one cycle is supplied. Then, the analog signal from the input terminal 1a is converted by the AD converter 2 into the DA converter 4 in the storage unit 1 of the memory 10.
The value is converted into a numerical value based on a control input using a value obtained by converting the count value stored in 0a into a voltage as a reference potential.

The digitized output of the AD converter 2 is compared by the comparator 6 with a reference value stored in the storage section 7a of the storage medium 7. At this time, if the output obtained by digitizing the analog signal is larger than the reference value, the counter 5 adds 1 to the count value stored in the storage unit 10a of the memory 10. If it is smaller than the reference value, 1 is subtracted from the count value stored in the storage unit 10a of the memory 10. Further, when the digitized output is equal to the reference value, the count value is not changed and is kept as it is.

From the counter 5, as described above, according to the result of the comparison between the digitized output of the analog signal and the reference value stored in the storage unit 7 a of the storage medium 7, the data is stored in the storage unit 10 a of the memory 10. A value obtained as a result of increasing or decreasing the stored count value or not increasing or decreasing is output to be stored in the storage unit 10a of the memory 10. Therefore, memory 1
The output from the counter 5 is stored as a new count value in the 0 storage unit 10a.

In one cycle of the clock signal from the clock generator 8, since the analog signal is digitized by the AD converter 2, the storage unit 1 of the memory 10
The operation up to the storage of the output (new count value) from the counter 5 by 0a and the switching of channels by the analog switch S1 and the data selectors S2 to S5 are performed.

Then, in the next one clock cycle,
The analog switch S1 sets the input terminal 1b, the data selector S2 sets the output value 3b, the data selector S3 sets the storage unit 7b of the storage medium 7, and the data selector S4.
At S5, the storage units 10b of the memory 10 are selected, and the same operation as the above-described clock cycle is performed.

The analog switch S1 and the data selectors S2 to S5 make one cycle with a clock signal for four cycles, and are connected again to the same contact. Therefore, in the AGC circuit, the same operation is performed again in a state where the reference potential of the DA converter 4 becomes a potential obtained by converting the count value stored in the storage units 10a to 10d of the memory 10 four cycles before. Is performed.

As described above, since the storage medium 7 and the memory 10 can all operate independently of each other, in the case of the present AGC circuit, the analog switch S1 and the data selector S2
By the switching operations of S5 to S5, independent AGC operations can be performed for a plurality of inputs.

By setting the reference values stored in the storage units 7a to 7d of the storage medium 7 to different values,
It is also possible to make the output values 3a to 3d constant at different values.

As described above, according to this embodiment, the output reference value is stored as a numerical value in the storage medium, so that the output reference value can be easily controlled by software.

Further, since the operation of the circuit is performed once for each cycle of the clock signal, by changing the generation cycle of the clock signal in the clock generator, the following speed of the AGC circuit with respect to the fluctuation of the input is softened. It can be easily and freely changed.

Further, since the value at which the count value of the counter changes in one operation can be limited, it is possible to realize an extremely stable operation that does not oscillate due to severe input fluctuations.

Further, by performing switching by the analog switch and the data selector, AGC operation for a plurality of inputs can be performed by one AGC circuit.
It is economical and can be downsized. Of course, various modifications can be made without departing from the spirit of the invention.

[0041]

As described above, according to the present invention, it is possible to provide an automatic gain control circuit which can be easily controlled by software and has a stable operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an AGC circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an AGC circuit according to another embodiment of the present invention.

FIG. 3 is a timing chart for explaining a switching operation.

[Explanation of symbols]

1, 1a-1d: input terminal, 2: AD converter, 3,
3a to 3d: output value, 4: DA converter, 5: counter, 6: comparator, 7: storage medium, 8: clock generator, 9: control terminal, 10: memory, S1: analog switch, S2 to S5: data selector.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-20407 (JP, A) JP-A-3-270308 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03G 3/20-3/34 H04B 3/04

Claims (2)

(57) [Claims] An analog signal input terminal and a control input terminal
Control the analog signal from the analog signal input terminal.
Digital output signal by comparing with reference potential of control input terminal
An A / D converter that outputs as an A / D converter and a digital output signal from the A / D converter
Control the output signal of the inverter to a desired value.
Comparison means for the reference value of the order is compared with a reference value from the pre-stored storage medium, the result of the comparison by the comparing means, the AD converter digital
If the total output signal is greater than the reference value,
And the digital output signal of the AD converter is the reference value
If it is smaller than the value, the count is subtracted and the
If the digital output signal is equal to the reference value,
Counting means for holding the count value as it is, and converting the count value of the counting means into an analog signal.
And outputs the output signal to a control input terminal of the AD converter.
A D / A converter that feeds back a reference potential as a reference potential and a clock signal to
The automatic gain control circuit
Clock supply means for keeping the state of
Automatic gain control circuit, characterized in that that. 2. The apparatus according to claim 1, further comprising: a first selection unit for selecting one of a plurality of analog signals; an analog signal input terminal and a control input terminal;
1 from the analog signal input terminal selected by the selecting means.
The analog signal is compared with the reference potential of the control input terminal and
An AD converter that outputs the digital signal as an output signal , and setting means in which a reference value for controlling the output signal from the AD converter to a desired value is set corresponding to each of the plurality of analog signals. Means for selecting a reference value corresponding to the analog signal selected by the first selection means; and a reference value selected by the second selection means and the AD converter.
Comparing means for comparing the output signal from the converter with the digital signal of the AD converter.
If the total output signal is greater than the reference value,
And the digital output signal of the AD converter is the reference value
If it is smaller than the value, the count is subtracted and the
If the digital output signal is equal to the reference value,
Counting means for holding the count value as it is; storage means for storing the count value of the count means in correspondence with each of the plurality of analog signals; and storage means for storing the count value corresponding to the analog signal selected by the first selection means. A third selecting means for selecting a count value to be set, and an analog signal for selecting the count value selected by the third selecting means.
And convert the output signal to the AD converter
For feedback input to the control input terminal of the
A clock signal is supplied to the converter and the respective means, and the clock signal is supplied to the converter.
The automatic gain control circuit
Clock supply means for keeping the state of
Automatic gain control circuit, characterized in that that.