JP3092641B2 - Semiconductor memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit composed of MOSFETs.

[0002]

2. Description of the Related Art A conventional semiconductor memory circuit is shown in FIG. This semiconductor memory circuit has a P-type MOSFET having a source connected to a power supply voltage V _DD , a gate connected to a reference voltage V _R2, and a drain connected to a digit line D _0.
Q _2, digit lines D ₀ and a plurality of memory cells connected respectively in parallel between the ground potential GND (semiconductor memory cell) M ₀ ~M of _four memory cell arrays (semiconductor memory cell array) 20, a memory cell M ₀ ~ X decoder 10 connected to the gate of M _4, and inputs an inverter circuit I _V output to the digit line D ₀ is connected to the output terminal V _0.

The operation of this semiconductor memory circuit will be described with reference to FIG. If no current flows in the memory cell selected by the X decoder 10, the voltage of the digit lines D ₀ power supply voltage V _DD becomes pulled up by P-type MOSFET Q _2, thus the output of the inverter I _V and the ground potential (low level) Become. When a current flows through the selected memory cell M ₀ , for example, the potential of the digit line D ₀ becomes the operating point _VL determined by the load characteristics of the P-type MOSFET Q ₂ and the memory cell M ₀ . The threshold value of the inverter _IV is usually determined by the power supply voltage _VDD and the operating point _VL.
Therefore, at the operating point _VL , the output of the inverter _IV becomes the power supply voltage V _DD (high level).

[0004]

Usually to the invention Problems to be Solved by the way the digit lines D ₀ is connected to a number of memory cells M ₀ ~M _4, thus the digit lines D ₀ memory cells M ₀ ~
Large capacity for such diffusion layer capacitance and wiring capacitance of M ₄ are attached. Further, the gate width of the cell transistor constituting the memory cell M ₀ ~M ₄ in order to increase the integration degree of the memory cell array 20 is small.

For this reason, digit line D ₀ is connected to power supply voltage V
_{When DD} is selected, the selected memory cell turns ON,
It takes time when discharging using a memory cell charge of the parasitic capacitance of the digit lines D ₀ for decreasing the digit lines D ₀ to the operating point V _L from the power supply voltage V _DD. As a result, there is a disadvantage that the reading speed of the memory in the semiconductor memory circuit is reduced.

An object of the present invention is to provide a semiconductor memory circuit capable of increasing the reading speed of a memory.

[0007]

According to the present invention SUMMARY OF], a clamp circuit connected between the first potential and the first connection point, Shin
Switch that can bypass the clamp circuit by a signal
Circuit, a source to the first connection point, and a gate to the second connection point.
The potential, the drain to the output terminal of the memory array cells,
Connect one-conductivity-type MOSFET and input
The drain of the serial M OSFET, and a gate circuit which connects the output to the output terminal, the semiconductor memory circuit is obtained and comprise characterized by being configured.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a semiconductor memory circuit according to a first embodiment of the present invention. The semiconductor memory circuit of this embodiment includes a memory cell array (semiconductor memory cell array) 20 including a P-type MOSFET Q ₁ , a P-type MOSFET Q ₂ , an inverter circuit I _V , and memory cells (semiconductor memory cells) M _{0 to} M _3, and an X decoder 10. Consists of P-type MOSFET Q ₁ is intended to function as a clamping circuit, its source connected to the power supply voltage V
The _DD, and the gate and drain are respectively connected to the first connection point P _1. The example shown is one P-type MOSF
Although an example in which a clamp circuit composed of ETQ _1, may constitute a clamp circuit comprising a plurality of P-type MOSFET Q ₁ connected in series.

The P-type MOSFET Q ₂ has a source at the first connection point P ₁ , a gate at the reference voltage V _R1 ,
The drain is the digit line D of the memory cell array 20.
Each is connected to ₀ . Input side of the inverter circuit I _V is the digit line D _0, and the output of the output-side terminal V ₀
Connected to each other. Memory cells M ₀ ~M ₄ is connected in parallel between the ground potential GND and the digit line D _0. X decoder 10 is connected to the gates of the memory cells M ₀ ~M _3.

[0011] In the semiconductor memory circuit of the first embodiment which is above configuration, when a current does not flow through the memory cell selected by the X decoder 10, the potential of the digit line D _0, the first
When the threshold voltage of the MOS FETs Q ₁ and V _TP,
V _DD − | V _TP |. On the other hand, when a current flows through the selected memory cell M ₀ , for example, the potential of the digit line D ₀ becomes the operating point V _L determined by the load characteristics of the second P-type MOSFET Q ₂ and the memory cell M ₀ . Here, the threshold value of the inverter _IV is set to V _DD − | V _TP | and the operating point _VL.
If it is set to be between, the _IV output of the inverter,
That output of the semiconductor memory circuit becomes a low level when no current flows in the memory cell M _0, also becomes a high level when a current flows through the memory cell M _0. FIG.
(A) is a high-level digit lines D ₀ from the low level, and FIG. 2 (b) shows the change in the voltage of the digit lines D ₀ and a semiconductor memory circuit in the case where the digit line D ₀ is changed from the high level to the low level, respectively It is a thing. In these figures, _Tf is the fall time of the digit line, and _Tr is the rise time of the digit line.

[0012] In the semiconductor memory circuit of the first embodiment, FIG. 2 (a), the voltage amplitude when the digit lines D ₀ is changed from the low level to the high level or vice versa as in (b) is less than conventional. As a result, the AC current is reduced even if the DC current is the same, and as a result, the speed of the read circuit of the memory can be increased. For example, the power supply voltage V _DD is 5 V, and the threshold value V _TP of the P-type MOSFET Q ₁ is −0.8.
V, the operating point V _L is to 1V, the voltage amplitude of the digit lines D ₀ becomes 1V～4.2V. Therefore, the inverter I
If the threshold value of V is set to 2.6 _V , the circuit of the first embodiment is about 20% faster than the conventional circuit.

FIG. 3 is a circuit diagram showing a semiconductor memory circuit according to a second embodiment of the present invention. The semiconductor memory circuit of the second embodiment is obtained by constituting the clamp circuit instead of P-type MOSFET Q ₁ by a diode D _i in the first embodiment shown in FIG. Incidentally, a similar diode D _i to each other in series connection may constitute a clamp circuit. Diode _Di has anode A connected to power supply voltage V
The _DD, also the cathode C are connected to the first connection point P _1. P-type MOSFET Q ₃ is connected in parallel with the diode D _i. P-type MOSFET Q ₃ has a source to the power supply voltage V _DD, the gate control signal V _P, the drain is connected to the first connection point P _1.

[0014] forward characteristics herein diode D _i is 4
Because as shown in, by using a diode D _i in place of the P-type MOSFET Q _1, the potential of the digit line D ₀ in the case where current is current in the selected memory cell and to the voltage starts to flow V _F does not flow V _DD -V _F. Therefore, it is clear that the same effects as those of the first embodiment can be obtained by adopting the configuration of the second embodiment.

In the semiconductor memory circuit according to the second embodiment, the clamp circuit can be switched between an active state and a non-operable state according to the power supply voltage V _DD and used. That is, normally the control signal V _P to the high level, by the gate voltage of the P-type MOSFET Q ₃ to a high level, the same operation as in Example 1 are carried out. On the other hand, when the low supply voltage V _DD is a control signal V _P to a low level, by the gate voltage of the P-type MOSFET Q ₃ to the low level, the P-type MOSFE
Performs control of turning on the TQ _3. Thus, a short circuit both ends of the clamp circuit consisting of diode D _i, it is possible to eliminate a reduction potential of the digit line D ₀ by diode D _i.

In this type of semiconductor memory circuit, when the power supply voltage V _DD is reduced, the voltage amplitude range of the digit line D ₀ is reduced, so that a noise margin is lost and a malfunction may occur. In addition, at the time of low power supply voltage operation, generally, the operation speed of the entire system is slower than at the time of normal power supply voltage. By bypassing the clamp circuit only at a low power supply voltage as in the semiconductor memory circuit of the second embodiment, it is possible to cope with a low power supply voltage.
The above malfunction can be prevented. Others
By varying the P-type MOSFET Q ₁ to the diode D _i, it is also possible to reduce the layout area.

[0017]

As described above, according to the semiconductor memory circuit of the present invention, the voltage amplitude of the digit line is reduced,
The memory reading speed can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor memory circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation of the semiconductor memory circuit according to the first embodiment;

FIG. 3 is a circuit diagram of a semiconductor memory circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating characteristics of a diode used in a circuit according to a second embodiment.

FIG. 5 is a circuit diagram of a conventional example of a semiconductor memory circuit.

FIG. 6 is a diagram illustrating an operation of a conventional semiconductor memory circuit.

[Explanation of symbols]

_{Q 1, Q 2, Q 3} P -type MOSFET I _V inverter D ₀ digit lines _{M 0, M 1, M 2} , M 3 memory cell V _R1, V _R2 reference voltage V _DD supply voltage V ₀ memory output D _i diode

Claims (3)

(57) [Claims] 1. A a first potential and a clamp circuit connected between the first connection point, the clamp circuit by the signal by
A switching circuit capable path, the source to the first connection point, the gate to the second potential, the drain to the output terminal of the memory array cells, the one conductivity type which is connected MO
And SFET, the drain of the prior Symbol M OSFET input, and a gate circuit which connects the output to the output terminal, constitute comprise
A semiconductor memory circuit. 2. The method according to claim 1, wherein the clamp circuit comprises a gate and a drain.
MOSFETs of the same conductivity type as the one conductivity type
It is characterized by comprising one or more circuits connected in series.
The semiconductor memory circuit according to claim 1. 3. The clamp circuit includes one diode.
A contract characterized by comprising circuits connected in series as described above.
The semiconductor memory circuit according to claim 1.