JP3001417B2 - Manufacturing method of semiconductor chip - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor chip, and more particularly, to a method of using a reticle having different magnifications together.
The present invention relates to a method of manufacturing a semiconductor chip for manufacturing a product chip and a test element group (hereinafter, referred to as TEG) chip for testing electrical characteristics and the like on a semiconductor wafer (hereinafter, referred to as a wafer).

[0002]

2. Description of the Related Art The steps of a method for manufacturing a semiconductor chip differ from product to product, but are performed using about 10 to 20 reticles. As the mask pattern in the reticle, a wafer having a size approximately five times the actual size of a semiconductor chip is used in order to finely process a wafer.

[0003] A semiconductor chip is formed on a wafer using this reticle. In many cases, a TEG chip is required in the wafer for evaluating electrical characteristics and the like.

[0004] The problems when inserting TEG chips are that the number of TEG chips is not increased more than necessary in order not to reduce the number of product chips, and that the time required for the stepper exposure step for the diffusion step or the like is not increased. In comparison, do not increase more than necessary.

Conventionally, in order to solve the above-mentioned problems, a reticle as shown in FIG. 9 in which a mask pattern of a product chip and a mask pattern of a TEG chip are drawn on the same reticle with a light-shielding band having a fixed width. Exposure processing of a semiconductor chip has been performed using all the steps of the product.

In FIG. 9 of a 5 × reticle, light-shielding bands 5BLD1 and 5BLD of dark portions provided inside a frame 5WAK of a portion that does not transmit light (hereinafter, referred to as a dark portion).
No. 2 is for separately exposing the mask pattern 5CR of the product chip and the mask patterns 5AR and 5BR of the TEG chip on the wafer.

[0007] PR process, such as for wafer diffusion manufacturing process,
That is, a mask is passed through the photoresist (PR) film.
The photoresist film is exposed to a latent image pattern.
In exposing the mask pattern 5CR of the product chip in the PR step of forming the mask, the mask pattern 5AR of the TEG chip is hidden by the shutter above the exposure device, and the mask pattern 5BR of the TEG chip is hidden by the shutter below.

When exposing the mask pattern 5AR of the TEG chip, both the mask pattern 5BR of the TEG chip and the mask pattern 5CR of the product chip are simultaneously hidden by a shutter below the exposure device.

When exposing the mask pattern 5BR of the TEG chip, both the mask pattern 5AR of the TEG chip and the mask pattern 5CR of the product chip are simultaneously hidden by a shutter above the exposure device.

The upper and lower shutters of the exposure apparatus cannot improve the accuracy like a reticle, and the distance to the wafer is different from that of the reticle. Light-shielding bands 5BLD1 and 5BLD2 to prevent light from leaking to the unexposed portions.
Is required.

By separately exposing the mask pattern of the product chip and the mask pattern of the TEG chip on the wafer, the TEG chip can be exposed at an arbitrary position. Moreover, since the mask pattern of the product chip and the mask pattern of the TEG chip are drawn on the same reticle, the reticle exchange that occurs when the reticle of the mask pattern of the product chip and the reticle of the mask pattern of the TEG chip are separately manufactured. And so on.

FIG. 8 shows an example of a wafer diffused by using the reticle of FIG.

In FIG. 8, since two product chip mask patterns 5CR are arranged side by side, when exposing the product chips C on the wafer W, the TEG chip mask patterns 5AR and 5BR are moved to the upper and lower shutters of the exposure apparatus. , And two product chips C are exposed. And TEG
The chips A and B are separately exposed once each, and two chips are exposed similarly to the product chip C.

The size of the TEG chip area obtained by adding the TEG chip A and the TEG chip B is equal to the product chip C on the wafer.
Of two.

Here, the mask pattern 5A of the TEG chip is used.
The reason for dividing the mask pattern 5BR of the R and TEG chips above and below the reticle is that the closer to the center of the reticle when exposing the wafer W, the more accurate the exposure is possible. Because it is.

More recently, the vertical structure of a semiconductor device has become more complicated and finer, and even if the total number of reticles used in a PR process for diffusing a semiconductor chip or the like does not change much, each reticle can be used. The processing time by the stepper is increasing due to an increase in the work in the process to be used.

As a countermeasure against the above-mentioned increase in processing time, there is a method in which reticles having different magnifications are used in combination. For example, the process that requires a highly accurate reticle is 5
A process that does not require high reticle accuracy and high accuracy uses a double reticle.

Since the upper limit of the size of the reticle is determined, the number of products drawn on one reticle can be increased by using a double reticle as compared with a reticle.

Then, when a double reticle is used,
Since the number of exposures per wafer decreases as the number of products increases, the time of the exposure processing step can be reduced.

When the total exposure step by a stepper for manufacturing a semiconductor chip is 20 steps, the double reticle step is 10 steps, and the 5 × reticle step is 10 steps, the exposure time is half of the step, ie, 10 steps. Be shortened.

FIG. 10 shows a double reticle. 5 in FIG.
Similarly to the double reticle, also in FIG. 10 of the double reticle, the light shielding bands 2BLD1 and 2BLD2 of the dark part provided inside the outer frame 2WAK of the dark part are the mask pattern 2CR of the product chip and the mask pattern 2AR of the TEG chip. ,
2BR is separately exposed on the wafer.

FIG. 11 shows an example of a diffused wafer by using both the example of the 2 × reticle in FIG. 10 and the example of the 5 × reticle in FIG.
Shown in

The size of the TEG chip area obtained by adding the TEG chips A and B is equal to ten product chips C on the wafer W.

This is because the number of the mask patterns 2AR and 2BR of the TEG chip drawn on the double reticle of FIG. 10 is five each, and therefore, the mask patterns 5AR and 5AR of the TEG chip drawn on the five times reticle of FIG. The number of TEG chips A and B on the wafer was different from the number of 5RBs, and the number of TEG chips A and B on the wafer was drawn on two types of reticles having different magnifications.
This is because it becomes the least common multiple of the number of mask patterns of the chip.

[0025]

As described above, in order to reduce the stepper processing time for the PR exposure step,
When reticles having different magnifications are used together, the number of mask patterns of the TEG chip in the mask pattern arrangement region of the n-times reticle is larger than that of the m-times reticle.

Accordingly, when the TEG chip is exposed on the wafer by the stepper in the PR process, at least n
There has been a problem that the number of TEG chips is equal to or larger than the number of mask patterns of the double reticle TEG chips.

[0027]

According to the method of manufacturing a semiconductor chip of the present invention, n
When using reticles with different magnifications of m and m,
The number of mask patterns of the TEG chips in the mask pattern arrangement region of the TEG chip arranged on the reticle of the n magnification is changed to the number of the mask patterns of the TEG chips in the mask pattern arrangement region of the TEG chip arranged on the reticle of the m magnification. The remaining number of the mask pattern arrangement region of the TEG chip is set to be a dark portion. Here, the number of the mask patterns of the TEG chips arranged on the reticle of the m magnification is set to be equal to or less than the number of the TEG chip patterns that can be arranged on the reticle of the m magnification, and the remaining portion of the mask pattern arrangement region of the TEG chip is determined. , Can be dark.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 shows a double reticle (n magnification) used in the method of manufacturing a semiconductor chip according to the first embodiment of the present invention.
A reticle), and FIG. 2 is a 5-fold reticles used in like manner (m ratio of the reticle).

FIG. 3 shows an example of a wafer when exposed using both the double reticles of FIG. 1 and the five times reticles of FIG.

FIG. 4 shows an example of an exposure method when exposing the wafer of FIG. 3 using the double reticle of FIG.
FIG. 5 shows an example of an exposure method when exposing the wafer of FIG. 3 using the five-fold reticle of FIG.

In the double reticle shown in FIG. 1, a light-shielding band 2BL of a dark portion provided inside a frame 2WAK of a dark portion is provided.
D1 and 2BLD2 are mask patterns 2C of product chips.
This is for separately exposing the mask patterns 2AR and 2BR of the R and TEG chips on the wafer.

TEG chip mask pattern arrangement area 2
A mask pattern 2AR of one TEG chip is provided at the center of ARA1, and a dark portion 2BLTEG corresponding to the mask pattern of two TEG chips is provided on both sides thereof.

Similarly, a mask pattern 2BR of one TEG chip is provided at the center of the mask pattern arrangement region 2BRA1 of the TEG chip, and a dark portion 2BLT corresponding to the mask pattern of two TEG chips is provided on both sides thereof.
An EG is provided.

When such a reticle as shown in FIG. 1 is used twice, the mask pattern arrangement area 2ARA of the TEG chip is used.
In both 1 and 2BRA1, only one TEG chip A or B is exposed on the wafer W by the dark portion 2BLTEG.

Therefore, the method of exposing the product chip C, the TEG chip A and the TEG chip B on the wafer W using the double reticle of FIG. 1 is as shown in FIG.

That is, as can be seen from the number of areas of the product chip exposure area 2SC indicated by the solid line, the number of times of exposure of the product chip is 14, and one TEG chip A is provided in each of the TEG chip exposure areas 2SA and 2SB of the double reticle. , B are exposed.

In the quintuple reticle shown in FIG. 2, a dark shielding band 5BL provided inside a dark outer frame 5WAK is provided.
D1 and 5BLD2 are mask patterns 5C of product chips.
This is to expose the mask patterns 5AR and 5BR of the R and TEG chips separately on the wafer.

TEG chip mask pattern arrangement area 5
A mask pattern 5AR of one TEG chip is provided on one side (left side in the figure) of ARA1, and a dark portion 5BLTEG corresponding to the mask pattern of one TEG chip is provided on the other side (right side in the figure). I have.

Similarly, one TE (left side in the drawing) is located on one side (left side in the figure) of the mask pattern arrangement area 5BRA1 of the TEG chip.
A mask pattern 5BR of the G chip is provided, and a dark portion 5BLTEG corresponding to the mask pattern of one TEG chip is provided on the other side (the right side in the figure).

Using such a five-fold reticle of FIG. 2,
As in FIG. 4, only one TEG chip A or B is exposed on the wafer W by the dark portion 5BLTEG in each of the mask pattern arrangement regions 5ARA1 and 5BRA1 of the TEG chip.

Therefore, the method of exposing the product chip C and the TEG chips A and B on the wafer W by using the 5-fold reticle of FIG. 2 is as shown in FIG.

That is, in FIG. 5, the product chip exposure area 5SC indicated by the solid line is the same as the conventional one, and the number of times of exposure of the product chip is 78 times, and one TEG chip is provided in each of the 5 × reticle TEG chip exposure areas 5SA and 5SB. A and B are exposed.

FIG. 6 shows a 2 × reticle (n magnification) used in the method of manufacturing a semiconductor chip according to the second embodiment of the present invention.
A reticle), FIG. 7 is a 5-fold reticles used in like manner (m ratio of the reticle).

In the double reticle shown in FIG. 6, a dark shading band 2BL provided inside a dark outer frame 2WAK is provided.
D1 and 2BLD2 are mask patterns 2C of product chips.
This is for separately exposing the mask patterns 2AR and 2BR of the R and TEG chips on the wafer.

TEG chip mask pattern arrangement area 2
A mask pattern 2AR of a total of two TEG chips is provided at the center and the left side of ARA2, and a total of three TEG chips are provided on both sides thereof.
Dark area 2BLTE corresponding to mask pattern of EG chip
G is provided.

Similarly, a total of two TEG chip mask patterns 2BR are provided at the center and the left side of the TEG chip mask pattern arrangement area 2BRA2, and a dark portion 2 corresponding to a total of three TEG chip mask patterns is provided on both sides thereof.
BLTEG is provided.

The 5 × reticle shown in FIG. 7 is provided with two mask patterns 5CR of the product chip of the 5 × reticle, similarly to the 5 × reticle of FIG. Two mask patterns 5AR of the 5 × reticle are provided in the mask pattern arrangement area 5ARA2 of the TEG chip, and the 5 × reticle TEG is provided.
Two mask patterns 5BR of a 5 × reticle TEG chip are provided in the mask pattern arrangement region 5BRA2 of the chip.

Then, the mask pattern arrangement area 5ARA2
Also, no dark portion is provided in the mask pattern arrangement region 5BRA2.

FIG. 8 shows an example of a wafer when exposure is performed using both the 2 × reticle of FIG. 6 and the 5 × reticle of FIG.

TEG chip mask pattern arrangement area 2
The number of the mask patterns 2AR and 5AR of the TEG chips of ARA2 and 5ARA2 and the number of the mask patterns 2BR and 5BR of the TEG chips of the TEG chips of the TEG chip are 2 respectively.
The number of TEG chips including the TEG chip A and the TEG chip B is equal to two product chips C on the wafer in FIG.

[0052]

As described above, in the method of manufacturing a semiconductor chip according to the present invention, when a reticle having a different magnification is used in combination in order to shorten the time of the exposure processing step, a TEG chip having a reticle of at least n magnification is used. The problem that the number of TEG chips is increased to be equal to or more than the number of mask patterns can be solved, and the number of product chips can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing a double reticle used in a method for manufacturing a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a five-fold reticle used in the method for manufacturing a semiconductor chip according to the first embodiment of the present invention.

FIG. 3 is a view showing a wafer according to the first embodiment in a case where exposure is performed by using a double reticle of FIG. 1 and a 5-fold reticle of FIG. 2 together;

FIG. 4 is a view showing an example of an exposure method when exposing the wafer of FIG. 3 using the double reticle of FIG. 1;

FIG. 5 is a diagram showing an example of an exposure method when exposing the wafer of FIG. 3 using the quintuple reticle of FIG. 2;

FIG. 6 is a diagram showing a double reticle used in a method of manufacturing a semiconductor chip according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a five-fold reticle used in a method of manufacturing a semiconductor chip according to a second embodiment of the present invention.

FIG. 8 is a view showing a wafer according to a second embodiment in the case where exposure is performed by using the double reticle of FIG. 6 and the 5-fold reticle of FIG. 7 together;

FIG. 9 is a view 5 showing a conventional method for manufacturing a semiconductor chip;
It is a figure showing a double reticle.

FIG. 10 is a diagram showing a double reticle used in a conventional method for manufacturing a semiconductor chip.

11 is a diagram showing a wafer of the prior art in the case where exposure is performed by using the 5-times reticle in FIG. 9 and the 2-times reticle in FIG. 10 in combination.

[Explanation of symbols]

2CR 2x reticle product chip mask pattern 2AR, 2BR 2x reticle TEG chip mask pattern 2ARA1, 2BRA1, 2ARA2, 2BRA2
2 × reticle TEG chip mask pattern placement area 2BLTEG 2 × reticle TEG chip mask pattern placement area dark area 2BLD1, 2BLD2 2 × reticle light-shielding band 2WAK 2 × reticle outer frame (dark section) 5CR 5 × reticle product Chip mask pattern 5AR, 5BR Mask pattern of 5 × reticle TEG chip 5ARA1, 5BRA1, 5ARA2, 5BRA2
5X reticle TEG chip mask pattern arrangement area 5BLTEG 5X reticle TEG chip mask pattern arrangement area 5BLD1, 5BLD2 5X reticle light-shielding band 5WAK 5X reticle outer frame (dark area) C Product chips A, B TEG chip W wafer 2SC 2X reticle product chip exposure area 2SA, 2SB 2X reticle TEG chip exposure area 5SC 5X reticle product chip exposure area 25A, 5SB 5X reticle TEG chip exposure area

Claims (2)

(57) [Claims] 1. A light-shielding band having a fixed width is provided between a mask pattern arrangement region of a product chip and a mask pattern arrangement region of a test element group chip, and the mask pattern arrangement of the product chip is separated by the light-shielding band. An area and a mask pattern arrangement area of the test element group chip are separated, and a mask pattern of the test element group chip in the mask pattern arrangement area of the test element group chip is arranged in parallel with the light shielding band. Reticles having different magnifications of n magnification and m magnification (where n <m),
Product chips and test elements on one semiconductor wafer
In the method of manufacturing a semiconductor chip for manufacturing a group chip, the number of mask patterns of the test element group chips arranged on the reticle having the n magnification is determined by changing the number of mask patterns of the test element group chips arranged on the reticle having the m magnification. The number of mask patterns is equal to or less than the number of mask patterns, and the remaining portion of the mask pattern arrangement region of the test element group chip arranged on the reticle having the n magnification is a portion that does not transmit light. A method for manufacturing a semiconductor chip. 2. The number of mask patterns of test element group chips arranged on the reticle having the m magnification is the same as the number of chip patterns of test element group chips which can be arranged on the reticle having the m magnification. 2. The method according to claim 1, wherein the remaining portion of the mask pattern arrangement region of the test element group chip is made a portion that does not transmit light when the number is smaller than that.