JP3022842B2 - IC card reading / writing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reading data from a card-shaped storage medium having a built-in semiconductor storage circuit,
The present invention also relates to an IC card reading / writing device for writing data into the device.

[0002]

2. Description of the Related Art As shown in FIG. 4, a card-shaped storage medium incorporating a semiconductor storage circuit, a so-called IC card 30, communicates between a semiconductor storage device 31 such as an EEPROM and an IC card reading / writing device. A control device 32 for performing control for reading data from and writing data to the semiconductor storage device 31 by molding is molded into a plate shape by molding with plastic, and an IC is formed on the surface.
A plurality of terminals 35 to 42 for forming contacts by contacting contact pins of a contact head of a card reading / writing device are provided.

Incidentally, a power supply voltage (Vcc) terminal 35, a reset signal (RST) terminal 36, and a clock signal (CLK) terminal 3 provided on such an IC card 30 are provided.
7, data input / output (I / O) terminal 38, ground (GN)
D) Since the terminal 39 is extremely small in size, there is a problem that a short circuit or poor contact is likely to occur. Nevertheless, since the terminals 35 to 42 of the IC card 30 are exposed to the outside, the terminals can be easily cleaned with a cloth or the like. For example, it has been proposed to perform a terminal cleaning operation using a cleaning member as shown in Japanese Patent Application Laid-Open No. 60-15887, but when the terminal is damaged, etc. Even by such an operation, a normal contact cannot be secured.

In particular, when contact with one of the power supply voltage terminal and the ground terminal is not ensured, the reset signal (RST) terminal 36 and the clock signal (CLK) terminal 3
7, data input / output (I / O) terminal 38, ground (GN)
D) There is a problem that a current different from usual flows from the terminals 39 or the like or to these terminals, and the IC card 30 is accessed in an illegal state, thereby destroying the data of the IC card.

In order to solve such a problem, for example, as shown in Japanese Patent Application Laid-Open No. 9-330381, the reset signal terminal of the IC card is set to low level and the clock signal of the integrated circuit is controlled to low level. A method of applying a power supply voltage to a power supply voltage terminal and comparing the voltage of a data input / output terminal with a reference value has been proposed.

[0006]

According to this, a contact failure between the power supply voltage terminal of the IC card and the corresponding contact of the contact head can be detected. There is a problem that the contact state cannot be detected, and in some cases, unauthorized access is performed and data in the semiconductor storage device is lost. The present invention has been made in view of such a problem, and an object of the present invention is to detect a contact state between a power supply voltage terminal and a ground terminal of an IC card and a contact pin of a contact head to thereby provide a semiconductor storage device. IC that can prevent data loss
An object of the present invention is to provide a card reading / writing device.

[0007]

According to the present invention, there is provided a contact head having contact pins for contacting terminals of an IC card.
An IC card read / write device having access control means for controlling communication with a C card;
Any two of the reset signal terminal, the clock signal terminal, and the data input / output terminal of the card are set to the L level, and the other terminal is set to the H level, and detected by the detecting means for detecting an abnormality in the current of the terminal. A contact state between a power supply voltage terminal of the IC card and the contact pin is determined. Further, one of two terminals of the reset signal terminal, the clock signal terminal, and the data input / output terminal of the IC card is set to H level, The terminal is set to the L level, and the abnormality of the current of the terminal is detected by the detection means to determine the contact state between the ground terminal of the IC card and the contact pin.

[0008]

When the contact pin is not in normal contact with the power supply voltage terminal or the ground terminal, an abnormal current flows through the reset signal terminal, the clock signal terminal, and the data input / output terminal. Then, the contact state between the power supply voltage terminal and the contact pin and the contact state between the ground terminal and the contact pin are detected.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention; FIG. 1 shows an embodiment of an IC card reading / writing apparatus.
The card conveying means 1 is composed of a motor 5 operated by a signal from an IC card detecting means 4 provided near the card insertion slot 3 of the conveying path 2 and a roller 6 connected to the motor 5. Roller 6 with spring 8 around 7
Is constantly biased toward the transport path 2 side.

When the IC card is stopped at a predetermined position, the contact head 9 supplies the power supply voltage (V) to the IC card 30.
cc) terminal 35, reset signal (RST) terminal 36, clock signal (CLK) terminal 37, data input / output (I /
O) Contact pins 10, 11, 1 at positions where contact can be made with terminal 38 and ground (GND) terminal 39.
2, 13 and 14, and the IC card 3
0 is detected to reach a predetermined position, the contact pins 10 to 10 are driven by driving means 19 such as a solenoid.
14 is configured to elastically contact the terminals 35 to 39 of the IC card 30.

FIG. 2 shows an embodiment of an IC card reading / writing apparatus.
The IC card 30 is connected to the contact pins 10 and 14 that contact the power supply voltage terminal 35 and the ground terminal 39 of the C card 30.
To supply a constant voltage suitable for driving the.

The access control means 21 resets each of the contact pins 11 and 12 connected to the terminals 36 and 37 of the IC card 30 only when an access denial signal from the contact inspection means 22 described later is not input. A signal and a clock signal are supplied to access and read data of the semiconductor memory device from the contact pin 13 contacting the data input / output terminal 38, and read the semiconductor memory device 4
5 is written. On the other hand, when an access denial signal is input from the contact inspection means 22, access to the IC card 30 is stopped.

At the time of checking the state of contact between the power supply voltage terminal 35 and the contact pin 10, the IC card 30
Of the reset signal terminal 36, the clock signal terminal 37, and the data input / output terminal 38 are set to L level, the other terminal is set to H level, and the contact state between the ground terminal 39 and the contact pin 14 is inspected. Sometimes, any two terminals of the reset signal terminal 36, the clock signal terminal 37, and the data input / output terminal 38 are set to the H level,
One terminal is configured to be at the L level.

The contact inspection means 22 includes contact pins 11, 12, 1, which contact the reset signal terminal 36, the clock signal terminal 37, and the data input / output terminal 38 of the IC card 30.
3 is selected by the first switching means 23, and one of the contact pin 10 or the contact pin 14 that contacts the power supply voltage terminal 35, the ground terminal 39, and the contact pin 14 is selected by the second switching means 24. And contact pin 10
When the contact status with the contact pins 11, 12, which are in contact with the reset signal terminal 36, the clock signal terminal 37, and the data input / output terminal 38 set to the H level,
The voltage of the resistors R11, R12 and R13 connected to the reset signal terminal 3 which is set to L level when the contact state between the ground terminal 39 and the contact pin 14 is inspected.
6. Voltage detecting means 25 for detecting the voltages of the resistors R11, R12 and R13 connected to the clock signal terminal 37 and the data input / output terminal 38, and determining whether or not the voltage of the voltage detecting means 25 exceeds a reference value. A determination means for outputting an access denial signal to the access control means if the reference value is exceeded;
And an inspection signal output unit 27 that outputs a signal at the time of inspection, for example, immediately after an IC card is inserted, and activates the determination unit 26.

This reference value is applied to the resistors R11, R12, R13 when the power supply voltage terminal 35, the ground terminal 39 of the IC card 30 and the contact pins 10, 14 of the contact head 9 form a normal contact. It is set based on the voltage generated by the flowing current.

In this embodiment, the IC card 30 is inserted and the contact pins 10 to 1 of the contact head 9 are inserted.
When 4 makes elastic contact with the terminals 35 to 39 of the IC card 30,
A power supply voltage is supplied from the power supply voltage supply means 20 to the IC card 30, and the IC card 30 is activated (FIG. 3).

The test signal output means 27 outputs a test signal to the access control means 21 to set one of the reset signal terminal 36, the clock signal terminal 37, and the data input / output terminal 38, for example, the reset signal terminal 36 to the H level. The clock signal terminal 37 and the data input / output terminal 38 are set to L level. Then, the reset signal terminal 36 is selected by the first switching means 23, and the contact pin 14 contacting the ground terminal 39 is selected by the second switching means 24.

When the power supply voltage terminal 35 and the contact pin 10 are normally in contact with each other, most of the current due to the supplied power supply voltage flows from the power supply voltage terminal 35 to the ground terminal 39. If the contact with the contact pin 10 is abnormal, the voltage of only one reset signal terminal 36 set to the H level becomes the highest level. Extra current flows, and the voltage of the resistor R11 changes.

The judging means 26 judges that the contact between the contact pin 10 and the power supply voltage terminal 35 is defective by comparing the voltage of the resistor R11 with a reference value.

Similarly, the clock signal terminal 37 is set to the H level, and the reset signal terminal 36 and the data input / output terminal 38
Are both at L level, when the contact between the contact pin 10 and the power supply voltage terminal 35 is defective, the clock signal terminal 37 is at the highest level. Extra current flows, and the voltage of the resistor R12 changes.

Further, the data input / output terminal 38 is set to the H level, and the reset signal terminal 36 and the clock signal terminal 37 are set.
Are set to L level, if the contact between the contact pin 10 and the power supply voltage terminal 35 is defective, the data input / output terminal 38 is at the highest level. Excess current flows except at the time, and the voltage of the resistor R13 changes.

Therefore, by detecting the voltages of the resistors R11, R12, and R13 of the terminals set to the H level among the reset signal terminal 36, the clock signal terminal 37, and the data input / output terminal 38, the contact pin 10 and the power supply are detected. The presence / absence of a contact failure with the voltage terminal 35 can be determined.

Since the reset signal terminal 36 is held at the L level and the data input / output terminal 38 is held at the H level in the initial state in order to prevent an abnormal operation at the time of the inspection, the reset signal terminal 36 is also at the H level at the time of the inspection. Let it be maintained. On the other hand, the alternating signal is applied to the clock signal terminal 37 even in the normal state, and either the H level or the L level can be applied. It is desirable to set.

When it is confirmed that the power supply voltage terminal 35 and the contact pin 10 are normally in contact with each other in this manner, the inspection signal output means 27
1 to output an inspection signal to any one of the reset signal terminal 36, the clock signal terminal 37, and the data input / output terminal 38, for example, the reset signal terminal 36 at the L level, and the clock signal terminal 37 and the data input / output terminal 38 at the H level And Then, the first switching means 23 causes the reset signal terminal 3
6 and the contact pin 10 contacting the power supply voltage terminal 35 by the second switching means 24.

When the ground terminal 39 and the contact pin 14 are in normal contact, most of the current due to the supplied power supply voltage flows from the power supply voltage terminal 35 to the ground terminal 39. 14 is abnormal, the voltage of the reset signal terminal 36 becomes the lowest level.
An extra current other than the normal current flows from 5 to the reset signal terminal 36, and the voltage of the resistor R11 changes.

The judging means 26 compares the voltage of the resistor R11 with a reference value, and compares the contact pin 14 with the reset signal terminal 39.
Is determined to be bad.

Similarly, the clock signal terminal 37 is set to L level, and the reset signal terminal 36 and the data input / output terminal 38
Are set to H level, if the contact between the contact pin 14 and the ground terminal 39 is defective, the clock signal terminal 37 becomes the lowest level.
An extra current other than normal flows from 5 to the clock signal terminal 37, and the voltage of the resistor R12 changes.

Similarly, the data input / output terminal 38 is set to L level, and the reset signal terminal 36 and the clock signal terminal 37
Are at H level, if the contact between the contact pin 14 and the ground terminal 39 is defective, the data input / output terminal 38 is at the lowest level.
An extra current other than the normal current flows from 5 to the data input / output terminal 38, and the voltage of the resistor R13 changes.

Therefore, by detecting the voltages of the resistors R11, R12, and R13 of the terminals set to the L level among the reset signal terminal 36, the clock signal terminal 37, and the data input / output terminal 38, the contact pin 14 and the ground are detected. The presence / absence of a contact failure with the terminal 39 can be determined.

The reset signal terminal 36 is held at the L level in order to prevent an abnormal operation during the test, and the data input / output terminal 38 is held at the H level in the initial state. Let it be maintained. On the other hand, the alternating signal is applied to the clock signal terminal 37 even in the normal state, and either the H level or the L level can be applied. It is desirable to set.

If normal contact between the contact pin 10 and the ground terminal 39 cannot be confirmed, the access control means 21 outputs an access denial signal to output the IC card 3
Block access to 0.

In this way, at the stage where it has been confirmed that at least the contact pin 10 and the power supply voltage terminal 35 and the contact pin 14 and the ground terminal 39 are both in normal contact, the judging means 26 sets the access control means. 21
An access permission signal is output to the IC card 30 to enable reading of data from the IC card 30 and writing of data to the IC card 30.

In this embodiment, the reset signal terminal 36, clock signal terminal 37, data input / output terminal 3
Although the current flowing through 8 is detected as the resistance voltages R11, R12, and R13, it is clear that the same effect can be obtained by directly detecting the current.

[0034]

As described above, according to the present invention, any two terminals of the reset signal terminal, the clock signal terminal, and the data input / output terminal of the IC card are set at the L level, and the other terminal is set at the H level. The contact state between the power supply voltage terminal of the IC card and the contact pin is determined by detecting the abnormality of the current of the terminal by detecting means,
Further, any two terminals of the reset signal terminal, the clock signal terminal, and the data input / output terminal of the IC card are set to the H level, and the other terminal is set to the L level, and the abnormality of the current of the terminal is detected by the detection means. The contact state between the ground terminal of the IC card and the contact pin is determined, so that the contact state between the power supply voltage terminal and the contact pin and the contact state between the ground terminal and the contact pin are both detected, and the IC card is detected. Data can be prevented from being lost due to unauthorized access to the server.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of an IC card reading / writing device.

FIG. 2 is a block diagram showing one embodiment of the present invention.

FIG. 3 is a waveform chart showing an operation of the IC card.

FIG. 4 is a partial sectional perspective view showing an example of an IC card.

[Explanation of symbols]

 9 Contact Head 10-14 Contact Pin 22 Contact Inspection Means 30 IC Card 35 Power Supply Voltage Terminal 36 Reset Signal Terminal 37 Clock Signal Terminal 38 Data Input / Output Terminal 39 Ground Terminal

Continuation of the front page (56) References JP-A-9-330381 (JP, A) JP-A-4-323790 (JP, A) JP-A-1-140387 (JP, A) JP-A-63-137385 (JP) , A) Japanese Utility Model Hei 3-44756 (JP, U) Japanese Utility Model Application Showa 61-89964 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06K 17/00

Claims (3)

(57) [Claims] 1. An IC card read / write device comprising: a contact head having a contact pin for contacting a terminal of an IC card; and an access control means for controlling communication with the IC card. Any one of a signal terminal, a clock signal terminal, and a data input / output terminal is set to L level, and the other terminal is set to H level, and detected by detecting means for detecting an abnormality in current of the terminal, and the IC card is detected. A contact state between a power supply voltage terminal and the contact pin is determined. Further, any two terminals of a reset signal terminal, a clock signal terminal, and a data input / output terminal of the IC card are set to the H level, and the other terminal is set to the L level. An abnormality in the current of the terminal is detected by the detection means as a level, and the ground terminal of the IC card and the contact IC card reading and writing apparatus for determining the contact between the pin. 2. A reset signal terminal and a data input / output terminal are maintained at an L level and a clock signal terminal is maintained at an H level when determining a contact state between the power supply voltage terminal and the contact pin. 2. The IC card read / write according to claim 1, wherein the clock signal terminal and the data input / output terminal are maintained at the H level and the reset signal terminal is maintained at the L level when the contact state between the ground terminal and the contact pin is determined. apparatus. 3. A current-voltage conversion resistor is connected to a contact pin forming a contact with the reset signal terminal, the clock signal terminal, and the data input / output terminal, and the detecting means detects a voltage. An IC card reader / writer according to any one of the preceding claims.