JP3025516B2 - Demultiplexer circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a demultiplexer circuit (DEMUX) for separating a time-division multiplexed signal.

[Conventional technology]

FIG. 6 shows the basic configuration of a demultiplexer circuit.
FIG. 11 is a block diagram illustrating a configuration of a conventional one-to-two demultiplexer circuit.

In the figure, a time division multiplexed signal D is input from an input terminal 61.
It is input to each terminal D of a master-slave-begger three-stage D flip-flop (MST) 62 and a master-slave two-stage D flip-flop (DF1) 63. Clock C
K is clock terminal 64, T flip-flop (TF1) 65
And the internal clock CK2 is output. The internal clock CK2 is input to the non-inverted clock terminal CK of the D flip-flop 62 and the inverted clock terminal CK of the D flip-flop 63. D flip-flop 6
The terminals Q of 2 and 63 are connected to the time-division demultiplexed signal O, respectively.
1, O2 is outputted, it is taken out to an output terminal 66 _1, 66 _2.

Hereinafter, referring to the timing chart shown in FIG.
The operation of the two-to-two demultiplexer circuit will be described.

In the time-division multiplexed signal D, data A and data B are alternately time-division-multiplexed, and _An , _Bn ,
A _{n + 1} , B _{n + 1} , A _{n + 2} , B _{n + 2} ,... Are sequentially input.

In the timing diagram shown in FIG. 7 (a), the D flip-flop 62 takes in the time division multiplexed signal D at the rising timing of the internal clock CK2, so that the output terminal 66 ₁
The time-division multiplexing / demultiplexing signal O1 taken out by A _n , A _{n + 1} ,
A _{n + 2} , ... Further, D flip-flop 63, since taking the time division multiplexed signal D at the falling timing of the internal clock CK2, division demultiplexing signal O2 is B _n when obtained from an output terminal 66 _2, B _{n + 1,} B _{n +2} , ...

On the other hand, the timing chart of FIG.
With respect to the timing diagram of FIG. 7, the phase relationship between the time division multiplexed signal D and the internal clock CK2 is inverted (the operation of the T flip-flop 65 is shifted by the CK1 clock).
The time division multiplexing / demultiplexing signal O1 becomes _Bn-1 , _Bn , _{Bn + 1} ,..., And the time division multiplexing / demultiplexing signal O2 becomes _An , _{An + 1} , _{An + 2} ,. ing.

[Problems to be solved by the invention]

Thus, time-division depending on the phase relationship of the multiplexed signal D and the clock CK2, the output terminal 66 _1, 66 ₂ in division demultiplexing signals O1, O2 of the data to be incorrect when retrieved.

By the way, since the clock CK2 is determined in the initial state of the T flip-flop 65, the position of the output terminal of the time-division-multiplexed data is uncertain. Therefore, in the conventional one-to-two demultiplexer circuit, when the output terminal position of the time-division multiplexed and demultiplexed data is opposite to the predetermined position, the T flip-flop 65 is controlled to control the clock CK2.
Had to change the phase.

However, this control requires a high-speed control signal equivalent to the data rate, and it has been difficult to realize the control with a simple configuration.

The same applies to the 1: N demultiplexer circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a demultiplexer circuit capable of controlling the position of an output terminal of time-division multiplexed and separated data with a simple configuration.

[Means for solving the problem]

According to the present invention, a ^2n- bit time division multiplexed signal (n is a positive integer) is separated and output to ²ⁿ output terminals one bit at a time.
In a ²ⁿ demultiplexer circuit, 2 ⁱ bit shift registers (i = 0, 1, 2,..., N−1) and 2: 1 selectors are connected in cascade with n stages, and each stage is connected according to a control signal. A path in which the shift amount of the time-division multiplexed signal is 0 bits or a path of ²ⁱ bits is selected by a 2-to-1 selector, and the shift amount of the time-division multiplexed signal is set to 0 to (2 ⁿ −
1) It is provided with a data shift means which is set to any one of bits and is used for separation processing of ^2n- bit data.

(Operation)

In the 1: ²ⁿ demultiplexer circuit of the present invention, a data shift means is arranged at an input stage of a data separation unit for separating and outputting a ^2n- bit time-division multiplexed signal to ²ⁿ output terminals one bit at a time. Configuration.

That is, the data shift means, the shift amount of time division multiplexed signals of 2 ⁿ bits ^{0,2 0, 2 1, 2 2} , ..., 2 n -1 is set to one of the bits, adjusting each bit position By passing the data to the data separation unit, predetermined data can be separated and output to each output terminal regardless of the phase relationship between the time division multiplexed signal and the internal clock of the data separation unit.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a minimum configuration of a demultiplexer circuit according to the present invention.

In this embodiment, n = 1, and a configuration example of a one-to-two demultiplexer circuit will be described. The same components as those of the conventional one-to-two demultiplexer circuit shown in FIG. And replace it with the description. That is, a portion surrounded by a broken line is a conventional one-to-two demultiplexer circuit,
Here, it is called a one-to-two data separation unit.

In the figure, the feature of the present embodiment is that the 1-bit shift register 11 and the 2-to-1 selector 13 constituting the data shift means are the same as the conventional 1-to-2 demultiplexer circuit.
It is provided at the input stage of the two-to-two data separation unit 10.

That is, the time-division multiplexed signal D is input from the input terminal 61 to 1
Terminal D of bit shift register 11 and 2: 1 selector
It is input to 13 terminals D1. The clock CK branches and is input to the clock terminal CK of the 1-bit shift register 11.
The output of the 1-bit shift register 11 is a 2-to-1 selector 13
Is input to the terminal D2. The two-to-one selector 13 selects the input signal of the terminal D1 or the terminal D2 according to the selection control signal S input from the control terminal 15 to the terminal S, and the time division multiplexed signal in which each bit position is adjusted. It is input to the one-to-two data separation unit 10 as DI. Time-division multiplexing / demultiplexing signals O1 and O2 are output to terminals Q of D flip-flops 62 and 63 that constitute the one-to-two data separation unit 10, respectively.
₁ , 66 ₂ are taken out.

Here, the two-to-one selector 13 selects the input signal of the terminal D1 when the selection control signal S is logic “1”, and selects the logic “0”.
In this case, the input signal of the terminal D2 is selected. That is, the time division multiplexed signal DI becomes a time division multiplexed signal D shifted by one bit at S = 0, and remains the same at S = 1.

The delay of the two-to-one selector 13 is assumed to be sufficiently smaller than the cycle of the clock CK.

Hereinafter, the operation of this embodiment will be described with reference to the timing chart shown in FIG.

The phase relationship between the time-division multiplexed signal D and the internal clock CK2 in FIGS. 2 (a) and 2 (b) is shown in FIG.
(B) respectively. Therefore, FIG. 2 (a)
For the S = 1, the case of FIG. 2 (b) is a S = 0, which determines the data division demultiplexing signals O1, O2 when taken out to the output terminal 66 _1, 66 ₂ Is set.

When S = 1, as shown in FIG. 2 (a), the time division multiplexed signal D input to the input terminal 61 as the time division multiplexed signal DI is selected, and each of the D flip-flops 62 and 63 is selected. since the input to the division demultiplexing signals O1 when taken out to the output terminal 66 _{1, a n, a n + 1} , a n + 2, ... , and an output terminal
Division demultiplexing signal O2 when taken in 66 _2, B _n,
B _{n + 1} , B _{n + 2} ,.

Similarly, when S = 0, as shown in FIG. 2B, a one-bit shift register is used as the time-division multiplexed signal DI.
The time-division multiplexed signal D via 11 is selected and input to each D flip-flop 62,63. Therefore, the phase relationship between the time division multiplexed signal DI and the internal clock CK2 is the same as the state shown in FIG.

That is, division demultiplexing signals O1 when taken out to the output terminal 66 _{1, A n, A n + 1} , A n + 2, ... , and an output terminal 66 ₂
The time-division demultiplexed signal O2 taken out at _Bn , _{Bn + 1} , B
_{n + 2} , ...

Thus, using the shift register 11 and the selector 13,
By adjusting the shift amount (bit position) of the time division multiplexed signal DI input to the one-to-two data separation unit 10 by the selection control signal S, the phase relationship between the time division multiplexed signal D and the internal clock CK2 is affected. In addition, it is possible to set the output terminal position of the time-division multiplex-separated data.

FIG. 3 is a block diagram showing a general configuration example of a 1: M (= 2 ⁿ ) demultiplexer circuit.

In this configuration example, in the present configuration example, an M-1 bit shift register 31 and an M-to-1 selector 33 constituting a data shift means are arranged in the same manner as a conventional one-to-M demultiplexer circuit.
It is provided at the input stage of the M data separation unit 30.

That is, the time-division multiplexed signal D is input from the input terminal 61 to M
It is input to the terminal D of the -1 bit shift register 31 and the terminal D1 of the M-to-1 selector 33. The clock CK branches and is input to the clock terminal CK of the M-1 bit shift register 31. 1-bit shift output output from the M-1 bit shift register 31, 2-bit shift output,..., M-1
The bit shift outputs are supplied to the terminals of the M to 1 selector 33, respectively.
Input to D2, D3, ..., DM. M to 1 selector 33, the selection control signal S j-bit input from the control terminal 35 ₁ to 35 _j in the terminal S1～Sj (j is necessary to select one of D1~DM value) In response, one of the input signals at terminals D1 to DM is selected, and a one-to-M data separating unit is selected as time-division multiplexed signal DI.
Entered in 30.

Therefore, the time-division multiplexed signal DI output from the M-to-1 selector 33 is obtained by shifting the time-division multiplexed signal D from 0 bit to M-1 bit in accordance with the selection control signal S.

, OM are output to the terminals Q1, Q2,..., QM of the one-to-M data separation unit 30, respectively.
The output terminals 66 ₁ , 66 ₂ ,..., 66 _M are taken out.

Here, the signal sequence of the time-division multiplexed signal D is D _{p + 1} , D _{p + 2} ,
D _{p + 3} ,…, D _{p + M} , D _{p + M + 1} , D _{p + M + 2} ,…, D _{p + 2M} ,
Assuming that _{Dp + 2M + 1} , _{Dp + 2M + 2} ,..., The terminals D2, D3,.
Input in a bit-shifted state.

On the other hand, the time-division multiplexing / demultiplexing signals O1, O2,..., OM output from the one-to-M data separation unit 30 correspond to the time-division multiplexing / demultiplexing signal O1 in accordance with the phase relationship between the time-division multiplexing signal D and the internal clock.
Are D _{p + 1} , D _{p + M + 1} , D _{p + 2M + 1} ,..., And the time division demultiplexed signal O1 is D _{p + 2} , D _{p + M + 2} , D _{p + 2M + 2} ,..., And similarly in the following, the time-division demultiplexed signal O1 is
There is a “state M” in which D _{p + M} , D _{p + 2M} ,...

Therefore, when the 1 to M data separation unit 30, for example in the "state 2", in order to obtain a "D _{p + 1"} as the division demultiplexing signals O1 when taken out to the output terminal 66 _1, M-one
The selector 33 may be controlled to select the terminal D2.
Further, for example, when in the "state 1", in order to obtain a "D _{p + 2"} are as division demultiplexing signals O1 when taken out to the output terminal 66 _1, so as to select the terminal DM in M-to-1 selector 33 Should be controlled.

In this manner, the one-to-M data separation unit 30 can separate and output predetermined data to each output terminal according to the time division multiplex signal DI corresponding to the selection control signal S.

By the way, in the minimum configuration shown in FIG.
Although the delay time at 13 is neglected, the delay time of the M to 1 selector 33 shown in the general configuration example of FIG. 3 cannot be ignored according to the value of M. In particular, in an ultra-high-speed demultiplexer circuit, it is difficult to operate the shift register at high speed, and thus it is essential to reduce the delay time in the selector.

Therefore, it is desirable that M of the M to 1 selector be as small as possible. In this case, the shift register and the selector are arranged in a multi-stage configuration.

For example, in a one-to-M demultiplexer circuit, an N shift register and an N-to-1 selector and an MN-1 shift register and an M-N-1 to-one selector are cascade-connected in a two-stage configuration. Can be improved.

For high-speed operation, it is effective to limit the M-to-1 selector to the 2-to-1 selector.

On the other hand, as described in the general configuration example shown in FIG. 3, in order to arbitrarily set the output terminal position of the M-bit data of the time-division multiplexed signal D, the time-division multiplexed signal D
Is variable in terms of the period of the clock CK input to the one-to-M demultiplexer circuit.
What is shifted by 0 to M-1 clocks is required.

Here, the typical configuration is 1: 2 ⁿ (n is a positive integer)
FIG. 5 shows a configuration of an embodiment of the present invention which can generate 2 ⁿ kinds of time division multiplexed signals DI shifted by 0 to 2 ⁿ -1 clocks in a demultiplexer circuit, and realize the two-to-one selector. Shown in

In FIG. 5, a time division multiplexed signal D is supplied to an input terminal 61.
Is input to the 1 (2 ⁰⁾ bit shift register 51 ₀ terminal D and 2-to-1 selector 53 ₀ terminals D1 from. 1 output of the bit shift register 51 _0, 2: 1 selector 53 ₀ terminal D2
Is input to The output of 2-to-1 selector 53 ₀ 2 (2 ¹⁾
Is input to the bit shift register 51 ₁ in the terminal D and 2-to-1 selector 53 _first terminal D1. 2-bit shift register 5
The output of the 1 ₁ is input to the 2-to-1 selector 53 _first terminal D2.

Thereafter, the 2 ^i- bit shift register 51 _i and the 2: 1 selector 53 _i are sequentially connected in cascade, and the output of the 2: 1 selector 53 _n−2 is connected to the terminal D of the 2 ⁿ⁻¹ bit shift register 51 _n−1 and 2
The signal is input to the terminal D1 of the _one- to-one selector 53n _-1 . The output of the 2 ^n-1 bit shift register 51 _n-1 is input to the 2-to-1 selector 53 _n-1 of the terminal D2, it is taken out as an output of 2-to-1 selector 53 _n-1 time division multiplexed signals DI , And is input to the 1: ²ⁿ separation unit 50.

The clock CK branches into each shift register 51 _{0 to} 51 _n-1
Clock terminal CK.

An _n- bit selection control signal S is input to each terminal S of the two-to-one selectors 53 _{0 to} 53 _n−1 .

Pair 2 ⁿ terminal Q1 of the data separation unit 50, Q2, ..., the Q2 ^n,
When each division demultiplexing signals O1, O2, ..., O2 ⁿ is output, the output terminals 66 _1, 66 _2, ..., extracted to 66 ₂ ^n.

By controlling each two-to-one selector in such a configuration, the time division multiplexed signal D can be shifted by 2 ⁿ -1 bits from a bit, and predetermined data can be separated and output to each output terminal. .

〔The invention's effect〕

As described above, the demultiplexer circuit of the present invention
By adding a data shift means with a simple configuration,
The output terminal position of each time-division multiplex-separated data can be arbitrarily set.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a minimum configuration of a demultiplexer circuit according to the present invention. FIG. 2 is a timing chart for explaining the operation in the minimum configuration. FIG. 3 is a block diagram showing a general configuration example of a 1: M (= 2 ⁿ ) demultiplexer circuit. FIG. 4 is a diagram illustrating the operation principle of a general configuration example. FIG. 5 is a block diagram showing a configuration of an embodiment of the present invention. FIG. 6 is a block diagram showing a configuration of a conventional one-to-two demultiplexer circuit. FIG. 7 is a timing chart for explaining the operation of the conventional one-to-two demultiplexer circuit. 10: 1-to-2 data separation unit, 11: 1-bit shift register, 13: 2-to-1 selector, 15: control terminal, 30 ...
1 to M data separation unit, 31 ... M-1 bit shift register, 33 ... M to 1 selector, 35 ... Control terminal, 50 ... 1
2 ⁿ data separation unit, 51 ₀ … 1 (2 ⁰ ) bit shift register, 51 _n-1 ... 2 ^n-1 bit shift register, 53 ... 2
One-to-one selector, 61 input terminal, 62 D flip-flop (MST), 63 D flip-flop (DF1), 64
… Clock terminal, 65… T flip-flop (TF1), 6
6 Output terminal.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-1442639 (JP, A) JP-A-3-20558 (JP, A) JP-A-63-60606 (JP, A) JP-A-63-63 60637 (JP, A) JP-A 1-159438 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 3/00-3/26 H03M 9/00

Claims (1)

(57) [Claims] 1. A pair for separating and outputting a 2 ^n- bit time division multiplexed signal (n is a positive integer) bit by bit to 2 ⁿ output terminals.
In a ²ⁿ demultiplexer circuit, a 2 ⁱ bit shift register (i = 0, 1, 2,..., N−1) and a 2: 1 selector are connected in cascade with n stages, and each stage is connected according to a control signal. A path having a shift amount of the time-division multiplexed signal of 0 bits or a path of ²ⁱ bits is selected by a 2-to-1 selector,
The shift amount of the time-division multiplexed signal is set to any of 0 to (2 ⁿ -1) bits depending on the selected combination and 2 ⁿ
A demultiplexer circuit comprising a data shift means for performing bit data separation processing.