JP3142357B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus, and more particularly, to a signal processing circuit of an image scanner using an image sensor. 2. Description of the Related Art In recent years, a signal processing circuit of an image scanner using an image sensor such as a CCD is required to have a variable gain according to the density of a document or a figure to be processed, and a variable gain amplifier is used. When the gain of the amplifier is changed, in order to keep the clamp level at the output terminal of the amplifier constant, the input terminal (V
There is a demand for a signal processing device capable of appropriately changing the clamp level viewed from in).

[0002]

2. Description of the Related Art Conventionally, in an image sensor signal processing circuit (signal processing circuit), in order to compensate for the influence of the ambient temperature and the fluctuation of the light source between the start of use and the continuous use, the clamp level is reduced. It is necessary to perform setting (key clamp), for example, at the time of initial setting for starting use of the image scanner, or at predetermined time intervals. Conventionally, this key clamp simply sets the clamp level to a reference voltage (for example, VR
H).

However, when the gain of an amplifier (amplifier) at the subsequent stage of the level clamp circuit is made variable, the clamp voltage at the input terminal of the amplifier greatly differs between when the gain is large and when the gain is small. I have.

[0004]

As described above, in the conventional signal processing circuit using a variable gain amplifier, the clamp voltage at the input terminal of the amplifier greatly differs between when the gain is large and when the gain is small. Therefore, when the key is simply clamped to the reference voltage VRH at the time of the key clamping, a number of subsequent clamping operations need to be repeated. as a result,
It takes a long time to complete the clamping operation.

The present invention has been made in view of the above-mentioned problems of the conventional signal processing apparatus, and has as its object to end a clamping operation in a signal processing circuit using a variable gain amplifier in a short time.

[0006]

FIG. 1 is a diagram for explaining the principle of a signal processing apparatus according to the present invention. According to the present invention, a coupling capacitor 2 connected to the image sensor 4 and the image sensor 4 connected via the coupling capacitor 2 to amplify the output of the image sensor 4 so that the degree of amplification is variable. An amplifier 3 and a level clamp circuit 1 for clamping a level at an input of the amplifier 3, and a key clamp voltage to be clamped by the level clamp circuit 1 is set according to the amplification degree of the amplifier 3. There is provided a signal processing device characterized by the following.

[0007]

According to the signal processing device of the present invention, the key clamp voltage to be clamped by the level clamp circuit 1 can be set according to the amplification degree of the amplifier 3. by this,
In the image sensor signal processing device including the variable gain amplifier, the level clamp operation can be completed quickly regardless of the gain setting of the amplifier.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a signal processing apparatus according to the present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining the principle of the signal processing device according to the present invention. In the figure,
Reference numeral 1 denotes a level clamp circuit which performs charge injection for level clamp. Reference numeral 2 denotes a coupling capacitor for holding a charge for level clamping. Reference numeral 3 denotes a variable gain amplifier whose gain can be controlled from the outside, and amplifies a signal from the sensor to an appropriate level with a gain set by a gain setting signal (G signal). 0 is an image sensor (for example, CCD: Charged
Coupled Device), and outputs a signal according to the intensity of light hitting the light receiving unit.

FIG. 2 is a block diagram showing an example of the level clamp circuit in FIG. As shown in the figure,
The level clamp circuit 1 includes a key clamp circuit 11 and a charge injection circuit 12. Key clamp circuit 11
Is a circuit for generating a voltage for key clamping, and includes a reference voltage VRH (high potential voltage) and a reference voltage VRL (low potential voltage).
Generates a voltage necessary for the key clamp according to the G signal. The charge injection circuit 12 is for setting the clamp level accurately after the coarse adjustment of the clamp level by the key clamp operation.

FIG. 3 is a circuit diagram showing an example of the charge injection circuit in FIG. As shown in the figure, the charge injection circuit 12 includes a plurality of capacitance C ₀ -C _3, and switches S0 ~
S3, SR, SC are provided. Here, the capacitances C ₁ , C ₂ , C
The value of _3, for example, twice the value of the capacitance C ₀ (e.g., 1.38 _pF), 4 _times, have been eight times, switches S0 to S3, S
By controlling R and SC, predetermined capacitors C _{0 to} C ₃ are selected (a plurality of capacitors can be selected) and connected between the input terminal (Vin) of the amplifier 3 and the reference voltage (VRH or VRL) to accurately The clamp level is set. The setting of the clamp level (key clamp) is performed, for example, at the time of initial setting for starting the use of the image scanner, or at predetermined time intervals.

FIG. 4 is a diagram showing an embodiment of the signal processing device of the present invention. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 4, reference numeral 3A is an operational amplifier of a variable gain amplifier, and 3B is a circuit for changing the gain, and the gain is changed by switching a switch by a G signal (gain setting signal). . An A / D converter 5 converts an analog signal amplified by the variable gain amplifier 3 into digital data. The image sensor (CCD) 4 has a positive polarity type and a negative polarity type. Here, a high level is output when dark (a high potential is output in black and a low potential is output in white). Consider an image sensor.

In FIG. 4, a timing signal T, a gain setting signal G, and A / D conversion data (output of an A / D converter 5) D are supplied to a level clamp circuit 1, and an input terminal (Vin) of an amplifier 3 is provided. Is performed. FIG. 5A is a diagram showing an example of the level clamp circuit in FIG. In the figure, reference numeral 13 denotes a circuit for performing timing generation and charge injection amount calculation, and includes a key clamp circuit 11 and a charge injection circuit 12.
To output various control signals.
In FIG. 5 (a), S0 to S3, SR and SC are charge injection circuits 1
2 and the switches S0 to S in FIG.
3, shows signals for controlling the switching of SR and SC. That is, the capacitances C _{0 to} C ₃ are selected by the control signals S ₀ to S ₃ to determine the charge injection amount, and the control signal SR is used to inject the charge into the coupling capacitor 2.
The control signals SG and SK are supplied to the key clamp circuit 1
1, the key clamp voltage is set by the control signal SG, and the key clamp is performed by the control signal SK. In FIG. 5A, the reference voltage VRM of the intermediate potential is used.
The intermediate reference voltage VRM is, for example, a predetermined value between the high potential reference voltage VRH and the low potential reference voltage VRL by the circuit shown in FIG. 5 (b). And the relation between the reference voltages is VRH> V
RM> VRL.

In the above-described embodiment of the signal processing apparatus of the present invention, when the variable gain amplifier 3 is set to the large gain state, the clamp control circuit 11 shown in FIG.
As a result, the switch SG is connected to the VRM side, the switch SK is turned on at the key clamp timing, and the key clamp operation is performed so that the key clamp level becomes VRM. On the other hand, when the variable gain amplifier 3 is set to the small gain state, the key clamp operation is performed with the switch SG connected to the VRH side. Here, in the present embodiment, the case where the image sensor (4) has the negative polarity has been described. That is, when the variable gain amplifier 3 is set to the small gain state, the high potential reference voltage VRH is selected. The key clamp operation is performed to approach the high potential reference voltage VRH. However, when the image sensor (4) has a positive polarity, the key clamp operation is performed to approach the low potential reference voltage VRL. .

Next, the operation for actually performing the level clamp (key clamp) will be described. FIG. 6 is a diagram showing the operation of the signal processing device of the present invention when the gain of the amplifier (variable gain amplifier) is small, and FIG. 7 is a diagram showing the operation of the signal processing device of the present invention when the gain of the amplifier is large. It is. Here, FIGS. 6 (a) and 7 (a)
6B shows the signal waveform of the input terminal Vin of the amplifier 3 in the state where the adjustment is being performed. FIGS. 6B and 7B show the Vin voltage and the key clamp timing in the state where the adjustment is being performed. Is shown.

First, a shield pixel (a pixel which is shielded so that light does not hit the light receiving portion) of the image sensor is read. The key clamp switch (SK) is closed in synchronization with the pixel signal portion of this signal to perform the key clamp operation. That is, as shown in FIG. 6 (b), when the gain of the amplifier is small, the high-potential reference voltage VRH is used as the clamp level and the input terminal V of the amplifier 3 is set.
Rough adjustment is performed so that the level of in becomes the high-potential reference voltage VRH, and thereafter, the clamp level is accurately set by the charge injection circuit 12. Here, the above explanation is
When the image sensor (4) has a negative polarity, the image sensor (4) has a positive potential.
Similar processing is performed with RL as the clamp level. 6 (a) and 6 (b), the switch SK
Immediately after the key clamp timing when
The waveform is distorted to the high level side due to reset noise.

As shown in FIG. 7 (b), when the gain of the amplifier is large, the reference voltage VRM of the intermediate potential is used as a clamp level, and the level of the input terminal Vin of the amplifier 3 is adjusted to the reference voltage of the intermediate potential. Rough adjustment is performed so as to achieve VRM, and thereafter, the clamp level is accurately set by the charge injection circuit 12. In this case, regardless of the polarity of the image sensor (4), the adjustment is, of course, performed using the reference voltage VRM of the intermediate potential as the clamp level. As in the case of FIG. 6, in FIGS. 7A and 7B, the waveform is distorted to the high level immediately after the key clamp timing when the switch SK is turned on, which is caused by reset noise. .

As described above, according to the present embodiment, the amplifier 3
By changing the voltage of the key clamp in accordance with the magnitude of the gain, the time required for the charge injection operation after the key clamp can be reduced, and the time required for the level clamp operation can be reduced. FIG. 8 is a diagram showing another embodiment of the signal processing device of the present invention, and FIG. 9 is a diagram showing still another embodiment of the signal processing device of the present invention.

In the key clamp circuit 11 shown in FIG. 5A, the key clamp level is switched between a high potential reference voltage VRH and an intermediate potential reference voltage VRM (switch SG).
The key clamp circuit 1 shown in FIG.
In 1 ′, a plurality of resistors R _{1 to} R _(n−1) are provided between a high-potential reference voltage VRH and a low-potential reference voltage VRL and selected by a plurality of switches SG _{1 to} SG _(n). , A key clamp level of a predetermined potential is set. Even in this case, for example, when the image sensor has a negative polarity, if the gain of the amplifier is small, the high-potential reference voltage V
The voltage on the RH side is set to the clamp level, and if the gain of the amplifier is large, a voltage close to the intermediate potential reference voltage VRM is set to the clamp level. Here, the circuit 1
3 ′ is a key clamp circuit 11 ′ and a charge injection circuit 1
2 is generated.

A key clamp circuit (D / A converter) 14 shown in FIG.
And outputs a signal of a voltage level corresponding to the signals E _{0 to} E _(k) converted according to Similarly to the key clamp circuit 11 ′, for example, when the image sensor has a negative polarity, if the gain of the amplifier is small, the key clamp circuit 14 sets the high-potential reference voltage VRH side voltage to the clamp level, and If the gain of the amplifier is large, a voltage close to the reference voltage VRM of the intermediate potential is output to be a clamp level. Also, the circuit 13 "
Generates a control signal corresponding to the key clamp circuit 14 and the charge injection circuit 12.

In the above description, it is needless to say that the key clamp circuit, the charge injection circuit, and the like can have various configurations other than those described above.

[0021]

As described above in detail, according to the signal processing device of the present invention, in the image sensor signal processing device including the variable gain amplifier, the level clamp operation can be quickly completed regardless of the gain setting of the amplifier. Can be done.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of a signal processing device according to the present invention.

FIG. 2 is a block diagram illustrating an example of a level clamp circuit in FIG. 1;

FIG. 3 is a circuit diagram illustrating an example of a charge injection circuit in FIG. 2;

FIG. 4 is a diagram showing one embodiment of the signal processing device of the present invention.

FIG. 5 is a diagram illustrating an example of a level clamp circuit in FIG. 4;

FIG. 6 is a diagram illustrating an operation when the gain of the amplifier is small in the signal processing device of the present invention.

FIG. 7 is a diagram illustrating an operation when the gain of the amplifier is large in the signal processing device of the present invention.

FIG. 8 is a diagram showing another embodiment of the signal processing device of the present invention.

FIG. 9 is a diagram showing still another embodiment of the signal processing device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Level clamp circuit 2 ... Coupling capacitor 3 ... Variable gain amplifier 3A ... Op amp 3B ... Feedback circuit for making gain variable 4 ... Image sensor 5 ... A / D converter 11, 11 '... Key clamp circuit 12 ... Charge Injection circuit 13, 13 ', 13 "Clamp timing generation and charge injection amount calculation circuit 14 A / D converter for key clamp level setting 13, 13', 13" Clamp timing generation and charge injection amount calculation circuit G ... Gain Setting signal D: Clamp level correction amount calculation data E0 to E (k): Key clamp level generation D / A converter data S0 to S3 (S (m)): Charge injection amount setting data SG: Key clamp level Setting switches SG1 to SG (m) ... key clamp level setting data SK ... key clamp switch SR Charge injection timing T ... clamping circuit operation timing signal VRH, VRM, VRL ... reference voltage

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/407 H04N 5/16

Claims (5)

(57) [Claims] 1. A coupling capacitor (2) connected to an image sensor (4), and an output of the image sensor (4) connected to the image sensor (4) via the coupling capacitor (2). (3) that amplifies the signal with a variable amplification factor, and a level clamp circuit (1) that clamps a level at an input of the amplifier (3), and a key clamp that is clamped by the level clamp circuit (1). A signal processing device wherein a voltage is set according to an amplification degree of the amplifier (3). 2. The key clamp voltage set by the level clamp circuit (1) is set to an intermediate potential voltage (VRM) when the amplification degree of the amplifier (3) is large. 2. The signal processing apparatus according to claim 1, wherein when the amplification degree in 3) is small, the voltage (VRH, VRL) becomes a high potential or a low potential. 3. A key clamp voltage set by the level clamp circuit (1) when the amplification degree of the amplifier (3) is small, and a low potential voltage (1) when the image sensor (4) has a positive polarity. VRL), and when the image sensor (4) has a negative polarity, a high potential voltage (VRH). 4. A key clamp voltage set by said level clamp circuit (1) is set by extracting from a plurality of resistors provided between said high potential and low potential voltages (VRH, VRL). 2. The signal processing device according to claim 1, wherein: 5. A high-potential and low-potential voltage (VRH) that outputs a key clamp voltage set by the level clamp circuit (1) and an output of a conversion table that outputs a value corresponding to the degree of amplification of the amplifier (3). , VRL), the signal is set by an output of a D / A converter that converts the voltage into an analog voltage.