JP3150631B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device such as a dot matrix type liquid crystal display module used for a display of a notebook personal computer or a monitor display of a personal computer.

[0002]

2. Description of the Related Art In recent years, a liquid crystal display device such as a dot matrix type liquid crystal display module has been widely used as a display of a notebook personal computer or a monitor display of a personal computer.

[0003] A conventional liquid crystal display device is hereinafter referred to as a TFT (Thin) which is a kind of dot matrix type liquid crystal display module.
An in-film-transistor type liquid crystal display module will be described as an example.

FIG. 2 is a block diagram of a conventional TFT liquid crystal display module (hereinafter simply referred to as a TFT liquid crystal module) which is one of the dot matrix type liquid crystal display modules. Hereinafter, the operation of the conventional liquid crystal display device will be briefly described with reference to this block diagram.

In FIG. 2, a connector 201 provided on a TFT liquid crystal module is provided with a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal, a dot clock signal and a plurality of signals from an external circuit (not shown) such as a personal computer. Data signal and power are supplied. The details of these signals will be described later with reference to the timing chart shown in FIG. When each signal supplied in this manner is input to the timing controller 202 through the connector 201, the timing controller 202 performs signal processing specific to the liquid crystal module such as inversion and rearrangement on the data signals, A signal necessary for driving the source driver IC 203 and the gate driver IC 204 is generated.

[0006] The DCDC converter 205 generates a voltage necessary for driving the liquid crystal in the liquid crystal panel 206 from the power supplied to the connector 201 and supplies the voltage to the gate driver IC 204. The source driver IC 203 and the gate driver IC 204 are connected to a source signal line and a gate signal line of the liquid crystal panel 206, and supply a signal for driving the liquid crystal through each signal line.

FIG. 3 shows timings of a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal, a dot clock signal and a data signal group supplied to a general TFT liquid crystal module. Here, the data signal group is
It is an 18-bit length of 6 bits × 3 (RGB). Also,
The number of pixels to be displayed will be described assuming that RGB is one pixel, 640 pixels horizontally and 480 pixels vertically.

First, at the falling timing 304 of the vertical synchronizing signal, after detecting vertical synchronizing, a period 302
, The acquisition of the horizontal effective data of the first line is started. Here, the period 302 is a vertical data start preparation period. A line refers to 640 horizontal pixels, and after the horizontal effective data of the first line is captured, data up to the 480th line is sequentially captured. The period from when all the data of the 480th line is fetched to the fall of the next vertical synchronization signal is a period 301 called a vertical front porch. Generally, the period 301 and the period 302
Together with the vertical blanking period.

As for the timing within one line, the horizontal synchronization is detected at the falling timing 314 of the horizontal synchronization signal in the same manner as in the case of the vertical, and the capture of the data of the first pixel is started after the horizontal data start preparation period 312. I do. When data of 640 pixels is captured, the next horizontal synchronization signal is input after a period 311 called a horizontal front porch. Generally, the period 311 and the period 312 are collectively called a horizontal blanking period.

[0010] These signals are all synchronized with the dot clock signal. In this conventional example, another signal is taken in at the falling timing of the dot clock signal.

[0011]

However, in the above-described conventional liquid crystal display device, the vertical data start preparation period 302, the horizontal data start preparation period 312, and the like differ depending on the liquid crystal module maker or model. When driving, the driving conditions must be changed for each manufacturer and model.

Therefore, by using the data enable signal without changing the vertical data start preparation period 302 and the horizontal data start preparation period 312 for each maker or model, a driving method for absorbing the difference between the maker or model is adopted. The case of adoption has increased. This data enable signal will also be described with reference to the timing chart of FIG.

In FIG. 3, the data enable signal is
Active (hereinafter H
high), and becomes inactive (hereinafter, low) during the invalid data period. That is, the signal is Low during the horizontal blanking period and the vertical blanking period, and is High during the other periods. If this signal is used, data can be fetched at the same time as the data enable signal becomes High without counting the vertical data start preparation period after detecting vertical synchronization.

Similarly, in the case of horizontal, after the horizontal synchronization is detected, only the data enable signal is monitored without counting the horizontal data start preparation period. Good.

However, some manufacturers have considered that the use of the data enable signal does not require the vertical synchronization signal and the horizontal synchronization signal, and there have been cases where the drive is performed without using the vertical synchronization signal and the horizontal synchronization signal. That is, since the vertical blanking period is much longer than the horizontal blanking period, the low period of the data enable signal is monitored, and if the low period of the data enable signal is longer than a certain period, the vertical synchronization is not performed. Because you can judge.

After that, if the data of the first line is taken in from the next rise of the data enable signal, there is no need to input the vertical synchronizing signal and the horizontal synchronizing signal.

The problem here is the problem of compatibility with the related art. In the description so far, there are three types of driving methods. These methods are summarized as follows (see Table 1).

[0018]

[Table 1] The first driving method uses a vertical synchronizing signal and a horizontal synchronizing signal, does not use a data enable signal, counts horizontal and vertical data start preparation periods, and takes in a data signal after a predetermined period.

The second driving method uses a vertical synchronizing signal and a horizontal synchronizing signal, and uses a data enable signal during a data start preparation period. The third driving method does not use the vertical synchronizing signal and the horizontal synchronizing signal, but performs all synchronization detection only with the data enable signal.

If all of the above three types of driving methods are supported, the versatility of the liquid crystal module is improved, but a mechanism for setting which driving method is used to input signals is required. For example, a small switch (for example, a dip switch) or the like is provided on the back surface of the liquid crystal module, and a method of changing the setting for each destination or a method of setting whether or not a jumper resistor is mounted can be considered.

However, in this case, there is a problem that the cost of the switch and the like increases, and a management system for changing the setting for each destination is required separately. In view of the above, the present invention is directed to a method of driving an input signal to a dot matrix type liquid crystal display module or the like, even if a signal of any driving method is input among input signals based on a plurality of different specifications. A liquid crystal display device that can automatically detect and display the image correctly without having to be aware of the difference in the timing specifications and without having to change the settings due to the difference. I will provide a.

[0022]

In order to solve the above-mentioned problems, a liquid crystal display device of the present invention automatically discriminates a driving method from a plurality of input signals to a dot matrix type liquid crystal display module and the like, It is characterized in that the corresponding data is taken in correctly.

As described above, even if a signal of any one of the input signals based on a plurality of different specifications is input to the dot matrix type liquid crystal display module or the like, the drive method of the input signal is automatically detected. The liquid crystal module can function normally and display an image correctly without being aware of the difference in the timing specifications and without having to change the setting due to the difference.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A liquid crystal display device according to a first aspect of the present invention comprises a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal, a dot clock signal, and a plurality of data signals which can be inputted as input signals. In a liquid crystal display device having a digital interface having an input terminal, the digital interface detects a vertical synchronization signal and a horizontal synchronization signal from a vertical synchronization signal and a horizontal synchronization signal when a data enable signal is not input, and outputs the vertical synchronization signal. When no horizontal sync signal is input, vertical sync and horizontal sync are detected from the data enable signal. When all signals are input, vertical sync and horizontal sync are respectively detected from the vertical sync signal and the horizontal sync signal. It has the function of detecting and detecting the display position information from the data enable signal. The detection method of the synchronization signal, and automatically switch configured in real time.

According to this configuration, as a method of interpreting the input signal, first, the data enable signal is kept low for a certain period.
Alternatively, when the signal is fixed at High, vertical synchronization and horizontal synchronization are detected from the vertical synchronization signal and the horizontal synchronization signal, respectively, and a data signal is taken in based on a predetermined blanking timing specification. When the signal, the vertical synchronizing signal, and the horizontal synchronizing signal are correctly input, the vertical synchronizing signal and the horizontal synchronizing signal are detected from the vertical synchronizing signal and the horizontal synchronizing signal, respectively, and the data is taken in based on the rising timing of the data enable signal. Third, when the vertical synchronizing signal and the horizontal synchronizing signal are fixed at Low or High for a certain period, each signal of vertical synchronizing and horizontal synchronizing is detected only from the data enable signal to acquire data. By automatically determining the driving method from a plurality of input signals. It captures the corresponding data correctly.

Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be specifically described with reference to the drawings.
FIG. 1 shows a block diagram of a timing controller TC1 in the liquid crystal display device of the present embodiment. This corresponds to the timing controller 202 in the block diagram of the conventional TFT liquid crystal display module shown in FIG. In this embodiment, a liquid crystal module having a number of horizontal dots of 640 pixels and a number of vertical pixels of 480 pixels, which is general for a portable personal computer, will be described.

The TFT which is the liquid crystal display device of the present embodiment
The conventional TF described with reference to FIG.
As in the case of the T liquid crystal module, a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal, a dot clock signal, and a data signal having an 18-bit width are supplied from an external circuit (not shown). It is input to the timing controller TC1.

In the timing controller TC1 as the digital interface, the horizontal / vertical synchronization signal monitor circuit 101 monitors whether the vertical synchronization signal and the horizontal synchronization signal are normally input. In particular,
The number of dot clocks in the High period and Low period of the vertical synchronizing signal is counted. If this period is larger than a predetermined count, it is determined that the vertical synchronizing signal is not input. Similarly, the horizontal synchronization signal H
If the high period and the low period are longer than the predetermined period, it is determined that the horizontal synchronization signal is not input.

Further, the data enable signal monitor circuit 102 constantly monitors the data enable signal,
If the high period and the low period are longer than the predetermined period, it is determined that the data enable signal has not been input.

The above horizontal / vertical synchronization signal monitor circuit 101
The presence / absence of each signal is determined by the data enable signal monitor circuit 102, and the interpretation method of the input signal is determined as follows based on this information.

As a first interpretation method, when the horizontal synchronizing signal and the vertical synchronizing signal are normally input, and the data enable signal is fixed at Low or High for a certain period, the vertical synchronizing signal and the horizontal synchronizing signal are respectively converted. The vertical synchronization and the horizontal synchronization are detected, and a data signal is fetched based on a predetermined blanking timing specification.
Hereinafter, the mode in which the input signal is interpreted in this manner is referred to as mode 1.

As a second interpretation method, when the horizontal synchronizing signal, the vertical synchronizing signal, and the data enable signal are all normally input, the detection of the vertical synchronizing signal and the horizontal synchronizing signal is detected from the vertical synchronizing signal and the horizontal synchronizing signal. Then, data capture is started based on the rising timing of the data enable signal. Hereinafter, the mode in which the input signal is interpreted in this manner is referred to as mode 2.

As a third interpretation method, when the vertical synchronizing signal and the horizontal synchronizing signal are fixed at Low or High for a certain period, the vertical synchronizing / horizontal synchronizing detection and data fetching are performed only from the data enable signal. Hereinafter, the mode in which the input signal is interpreted in this manner is referred to as mode 3.

The mode transmission circuit 103 selects one of mode 1, mode 2 and mode 3 based on information from the horizontal / vertical synchronization signal monitor circuit 101 and the data enable signal monitor circuit 102, based on the signal specification currently input. It has a function of transmitting such mode information to the synchronization signal selection circuit 107.

Reference numerals 104, 105 and 106 denote synchronization detection circuits corresponding to mode 1, mode 2 and mode 3, respectively. The synchronization signal selection circuit 107 indicates the mode information based on the mode information from the mode transmission circuit 103. The synchronization detection circuit corresponding to the mode of the input signal is selected. The data signal is taken in based on the synchronization signal from the synchronization detection circuit selected in this way.

The data signal processing circuit 108 performs data inversion processing or the like on the data signal fetched as described above to generate signals necessary for driving the liquid crystal and the source driver IC and the gate driver IC. .

As described above, the driving method can be automatically determined from a plurality of input signals to the dot matrix type liquid crystal display module and the like, and the corresponding data can be correctly taken in.

As described above, the driving method of the input signal is automatically detected even if the signal of any driving method among the input signals based on a plurality of different specifications is inputted to the dot matrix type liquid crystal display module or the like. The liquid crystal module can function normally and display an image correctly without being aware of the difference in the timing specifications and without having to change the setting due to the difference.

In this embodiment, the types of input signals are mode 1, mode 2, and mode 3, but are not limited thereto.

[0040]

As described above, according to the present invention, the drive system can be automatically determined from a plurality of input signals to a dot matrix type liquid crystal display module or the like, and the corresponding data can be correctly taken in. .

Therefore, even when a signal of any one of the input signals based on a plurality of different specifications is input to the dot matrix type liquid crystal display module or the like, the drive method of the input signal is automatically detected. It is possible,
The liquid crystal module can function normally and display an image correctly without being aware of the difference in the timing specifications and changing the setting due to the difference, and the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a block diagram of a timing controller of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a TFT type liquid crystal display module which is a conventional liquid crystal display device.

FIG. 3 is an explanatory diagram of various signal groups input to a general TFT type liquid crystal display module.

[Explanation of symbols]

 Reference Signs List 101 horizontal / vertical synchronization signal monitoring circuit 102 data enable signal monitoring circuit 103 mode transmission circuit 104 mode 1 synchronization detection circuit 105 mode 2 synchronization detection circuit 106 mode 3 synchronization detection circuit 107 synchronization signal selection circuit 108 data signal processing circuit

Claims (1)

(57) [Claims] 1. A liquid crystal display device comprising a digital interface having a plurality of input terminals capable of inputting a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal, a dot clock signal and a plurality of data signals as input signals. The interface detects the vertical synchronization and the horizontal synchronization from the vertical synchronization signal and the horizontal synchronization signal when the data enable signal is not input, and detects the vertical synchronization and the horizontal synchronization from the data enable signal when the vertical synchronization signal and the horizontal synchronization signal are not input. Synchronization and horizontal synchronization are detected. When all signals are input, a function to detect vertical synchronization and horizontal synchronization from the vertical synchronization signal and horizontal synchronization signal, respectively, and display position information from the data enable signal is provided. And a method for detecting these synchronization signals,
A liquid crystal display that automatically switches in real time.