JP3158587B2 - Thin film transistor panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor panel used for an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art A thin film transistor panel (hereinafter referred to as a TFT panel) used for an active matrix liquid crystal display device has the following structure.

FIGS. 3 and 4 are a plan view of a part of a conventional TFT panel and an equivalent circuit diagram thereof.
The panel includes, on a transparent substrate 1 made of glass, a plurality of transparent pixel electrodes 2 arranged in a row direction and a column direction, a plurality of thin film transistors 3 respectively connected to the pixel electrodes 2, and a plurality of thin film transistors connected to the thin film transistors 3. The gate lines GL and the data lines DL are provided, each gate line GL is wired between each pixel electrode column, and each data line DL is wired between each pixel electrode row. .

The thin film transistor 3 generally has an inverted stagger structure. The thin film transistor 3 includes a gate electrode G connected to a gate line GL formed on the substrate 1, a gate insulating film 4 covering the gate electrode G, The semiconductor layer 5 formed on the gate insulating film 4 and the source and drain electrodes S,
D. The gate insulating film 4 of the thin film transistor 3 is formed on almost the entire surface of the substrate 1 so as to cover the gate line GL.

The pixel electrode 2 and the data line DL
Are formed on the gate insulating film (transparent film) 4, the source electrode S of the thin film transistor 3 is connected to the pixel electrode 2, and the drain electrode D is connected to the data line DL.

The active matrix liquid crystal display element comprises a frame-like sealing material comprising the above-mentioned TFT panel and a counter panel (not shown) in which a counter electrode (transparent electrode) is formed on a transparent substrate and an alignment process is performed thereon. And a liquid crystal is sealed between the panels.

By the way, in the active matrix liquid crystal display device, in order to reduce the fluctuation of the potential held in the pixel electrode 2 during the non-selection period, a storage capacitor Cs is provided in each of the pixel electrodes 2 in the TFT panel. Provided.

3 and 4, CL is a capacitor line for constituting the storage capacitor Cs. The capacitor line CL is provided on the substrate 1 (below the gate insulating film 4) for the pixel electrode of each row. It is formed in parallel with the gate line GL so as to face each one side edge.

The storage capacitor Cs is composed of the capacitor line CL, the pixel electrode 2 and the gate insulating film 4 therebetween. The storage capacitor accumulates the electric charge applied to the pixel electrode 2 when the pixel electrode 2 is selected (when the thin film transistor 3 is turned on). The storage capacitor holds the potential of the pixel electrode 2 during the non-selection period. You. Note that the capacitor line CL is connected to a reference potential (ground potential).

[0010]

However, in the above-mentioned conventional TFT panel, since one capacitor line CL is provided for each pixel electrode column, the same number of pixel electrode columns on the substrate 1 is provided. Has to be formed.

An object of the present invention is to provide a TFT panel in which storage capacitors can be formed on all pixel electrodes by forming capacitor lines of almost half the number of pixel electrode columns.

[0012]

According to the TFT panel of the present invention, one gate line is provided between every two rows of pixel electrodes, and one thin film transistor of each of the pixel electrodes on both sides of the gate line is provided. The data lines are connected to the gate lines wired between the columns , and the data lines are wired two by two between each pixel electrode row. Of the thin film transistors connected to the same gate line, the data lines are connected to the gate lines. The thin film transistor of the pixel electrode in one column is connected to the data line adjacent to one side of the pixel electrode row, the thin film transistor of the pixel electrode in the other column is connected to the data line adjacent to the other side of the pixel electrode row, and Different
Connected to the gate line via the thin film transistor
Capacitor lines having a width spanning the pixel electrodes of both columns are provided corresponding to the pixel electrodes of the two adjacent columns, and storage capacitors are formed between the capacitor lines and the pixel electrodes of the two columns. It is characterized by the following.

[0013]

In the TFT panel of the present invention, a gate line is wired between every two columns of pixel electrodes, and two rows of pixel electrodes are arranged adjacent to each other without a gate line interposed therebetween. A capacitor line having a width extending over both of the pixel electrodes is provided correspondingly, and a storage capacitor is formed between the capacitor line and the two columns of pixel electrodes. It can be shared by the storage capacitors of two rows of pixel electrodes, and therefore, the number of capacitor lines required to form storage capacitors for all the pixel electrodes may be approximately half the number of pixel electrode rows.

In this TFT panel, there is only one gate line between every two rows of pixel electrodes, but as described above, each of the thin film transistors of the pixel electrodes on both sides of the gate line is connected to the pixel electrode. Of the thin film transistors connected to the same gate line, and a thin film transistor of a pixel electrode in a column on one side of the gate line among the thin film transistors connected to the same gate line. If the thin film transistors of the pixel electrodes in the other column are connected to the data lines adjacent to one side of the electrode row and the data lines adjacent to the other side of the pixel electrode row, the thin film transistors of all the pixel electrodes are driven. Can be.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a plan view of a part of a TFT panel, and FIG. 2 is an equivalent circuit diagram thereof. In FIGS. 1 and 2, those corresponding to the conventional TFT panel shown in FIGS. 3 and 4 are denoted by the same reference numerals, and the description of the same parts as those of the conventional TFT panel is omitted.

In this TFT panel, the gate line GL
Are arranged one by one between every two rows of pixel electrodes, and the two rows of pixel electrodes 2 are adjacent to each other without a gate line GL interposed therebetween.

The gate line GL is a common line for simultaneously supplying a gate signal to the thin film transistor 3 of the pixel electrode 2 in the adjacent column on one side and the thin film transistor 3 of the pixel electrode 2 in the adjacent column on the other side. ing.

The thin film transistors 3 of the pixel electrodes 2 in the columns on both sides of the gate line GL are arranged on the side of the pixel electrode 2 on the side of the gate line GL so as to be shifted in the length direction of the gate line GL. The gate electrode G of the thin film transistor 3 in which the source electrode S is connected to the pixel electrode 2 in the column on one side of the gate line GL is formed on one side of the gate line DL and the other side of the gate line GL The gate electrode G of the thin film transistor 3 in which the source electrode S is connected to the pixel electrode 2 of the column is formed on the other side of the gate line DL.

Further, two data lines DL are arranged between each pixel electrode row. Of the thin film transistors 3 and 3 connected to the same gate line GL, one data line DL is connected to one column of the gate line DL. The drain electrode D of the thin film transistor 3 of the pixel electrode 2 is connected to the data line DL adjacent to one side of the pixel electrode row, and the drain electrode D of the thin film transistor 3 of the pixel electrode 2 on the other side of the gate line DL is It is connected to a data line DL adjacent to the other side of the pixel electrode row.

On the other hand, the capacitor lines CL are provided between the two columns of the pixel electrodes 2 and 2. This capacitor line CL is formed to have a width that extends over both of the two columns of pixel electrodes 2, 2, and the storage capacitor Cs of the pixel electrode 2 of one of the two columns of pixel electrodes 2, 2 is Is formed between the side edge of the pixel electrode 2 and a half width region of the capacitor line CL. The storage capacitor Cs of the pixel electrode 2 in the other column is connected to the side edge of the pixel electrode 2 It is formed between the other half width region of the capacitor line CL.

In this embodiment, the width of the capacitor line CL is made almost twice as large as the width of the capacitor line in the conventional TFT panel.
And the pixel electrodes 2 and 2 of both columns, respectively,
The capacitor line and the pixel electrode in the T panel are opposed to each other with substantially the same area, and the storage capacitor Cs of each pixel electrode 2 has substantially the same capacity as the storage capacitor of the conventional TFT panel.

In this TFT panel, the gate line GL
Are wired two by two between every two rows of pixel electrodes,
The pixel electrode 2 in one of the two columns of the pixel electrodes 2
Is connected to the gate line GL adjacent to the pixel electrode 2 in the one column, and the thin film transistor 3 of the pixel electrode 2 in the other column is connected to the gate line GL adjacent to the pixel electrode 2 in the other column. A capacitor line having a width spanning both pixel electrodes 2, 2 corresponding to between the two columns of pixel electrodes, while adjoining pixel electrodes 2, 2 in two columns without a gate line GL interposed therebetween. CL is provided, and storage capacitors Cs are formed between the capacitor lines CL and the two columns of pixel electrodes 2 and 2 respectively. Therefore, one capacitor line CL is connected to the storage capacitors of the two columns of pixel electrodes 2. Can be shared by Cs.

Therefore, according to the above TFT panel,
The number of capacitor lines required to form storage capacitors for all pixel electrodes 2 is ２ of the number of pixel electrode columns when the number of pixel electrode columns is even, and 1 when the number of pixel electrode columns is odd. Therefore, the storage capacitors Cs can be formed on all the pixel electrodes 2 only by forming capacitor lines of almost half the number of pixel electrode columns.

In this TFT panel, the number of data lines is twice that of a conventional TFT panel (TFT panel having the same number of pixel electrodes). However, since the number of gate lines is １ ／, the gate line GL is The total number of lines DL is the same as the conventional TFT panel.

In the above-mentioned TFT panel, there is only one gate line DL between every two columns of pixel electrodes. However, as described above, the gate line DL is connected to the pixel electrode of a column adjacent to one side thereof. 2 and the thin film transistor 3 of the pixel electrode 2 in the column on both sides of the gate line DL as a shared line for simultaneously supplying a gate signal to the thin film transistor 3 of the other column and the thin film transistor 3 of the pixel electrode 2 in the column adjacent to the other side. The thin film transistors connected to the same gate line GL are connected to the gate lines DL between the pixel electrodes, and two data lines DL are arranged between each pixel electrode row. The thin film transistor 3 of the pixel electrode 2 in the other column is connected to the thin film transistor 3 of the electrode 2 on the data line DL adjacent to one side of the pixel electrode row. If connect the data 3 to the data lines DL adjacent to the other side of the pixel electrode row, it is possible to drive the TFT 3 of all the pixel electrodes 2.

That is, the active matrix liquid crystal display device using the above-mentioned TFT panel is provided with each gate line G
L, a gate signal (scanning signal) is sequentially applied to turn on the thin film transistors 3 by two columns of pixel electrodes simultaneously, and in synchronization with this, data signals of two columns of pixel electrodes are applied to two data lines DL, respectively. Time-division driving can be performed by a driving method.

This active matrix liquid crystal display element has two gate lines GL as described above.
Since the thin film transistors 3 of the pixel electrodes 2 in a column can be driven, a drive duty can be increased, and the number of gate lines can be increased, so that a large screen can be realized.

[0028]

According to the TFT panel of the present invention, one gate line is wired between every two columns of pixel electrodes, and the thin film transistors of the pixel electrodes in the columns on both sides of the gate line are connected to the pixel. The data line is connected to the gate line between the electrodes, and two data lines are arranged between each pixel electrode row. Of the thin film transistors connected to the same gate line, the thin film transistor of the pixel electrode on one side of the gate line Is connected to the data line adjacent to one side of the pixel electrode row, the thin film transistor of the pixel electrode in the other side column is connected to the data line adjacent to the other side of the pixel electrode row, and between the pixel electrodes in the two columns. Correspondingly, a capacitor line having a width extending over the pixel electrodes in both columns is provided, and a capacitor line between the capacitor line and the pixel electrodes in the two columns is provided. Due to the respectively form a storage capacitor, only form a substantially half of the capacitor line of pixel electrode columns, it is possible to form the storage capacitor to all the pixel electrodes.

[Brief description of the drawings]

FIG. 1 is a plan view of a part of a TFT panel showing one embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the TFT panel.

FIG. 3 is a plan view of a part of a conventional TFT panel.

FIG. 4 is an equivalent circuit diagram of a conventional TFT panel.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Pixel electrode, 3 ... Thin film transistor, GL
... gate line, G ... gate electrode, 4 ... gate insulating film,
5: semiconductor layer, S: source electrode, D: drain electrode, D
L: data line, CL: capacitor line, Cs: storage capacitor.

Claims (1)

(57) [Claims] A plurality of pixel electrodes arranged in a row direction and a column direction on a transparent substrate, a plurality of thin film transistors respectively connected to the pixel electrodes, a plurality of gate lines and data lines connected to the thin film transistors, In a thin film transistor panel provided with a plurality of capacitor lines forming a storage capacitor between the pixel electrode and the pixel electrode, one of the gate lines is wired between every two columns of the pixel electrode, and both sides of the gate line All of the thin film transistors of the pixel electrodes of the column are connected to the gate lines wired between the columns , and the data lines are wired two each between the pixel electrode rows, and are connected to the same gate line. Among the connected thin film transistors, a thin film transistor of a pixel electrode in a column on one side of the gate line. Njisuta the data line adjacent to one side of the pixel electrode row, the thin film transistor of the other side of the column of the pixel electrode connecting to the data line adjacent to the other side of the pixel electrode row, and different
Connected to the gate line via the thin film transistor
Capacitor lines having a width extending over the pixel electrodes of both columns are provided corresponding to the pixel electrodes of two adjacent columns, and storage capacitors are formed between the capacitor lines and the pixel electrodes of the two columns. A thin film transistor panel characterized by the above-mentioned.