JP3159527B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a bipolar transistor characterized by ultra-high speed operation.

[0002]

2. Description of the Related Art As the miniaturization of bipolar transistors progresses and the thickness of the base becomes thinner, the high-frequency characteristics deteriorate due to an increase in the base resistance. To avoid this, if the impurity concentration of the base is increased, it is necessary to further increase the concentration of the emitter. This reduces the current injection efficiency by reducing the emitter band gap, that is, leads to a reduction in the current amplification factor. To prevent this, it is necessary to make the bandwidth of the emitter material larger than that of the base material. For this reason, a heterojunction bipolar transistor structure (HBT) is required.

[0003] Among HBTs, a heterostructure using a silicon-germanium mixed crystal is effective. Practical application is currently being promoted due to the good consistency of the crystal structure. In particular, HBTs based on silicon germanium are:
The field of LSI is mainly used. The GaAs HBT is superior in terms of the high speed of the transistor itself. For this reason, such a thing is used for a simple substance or a small-sized IC. As an example, silicon germanium type H
Putting BT into practical use is
Technology Digest, 1990, page 603 (IEDM Tech. Dig. (1990) p.6)
03). To use in the field of LSI,
A self-aligned structure and its manufacturing process are essential. In order to reduce the base resistance, it is necessary to reduce the size of the emitter, to reduce the distance between the intrinsic base region and the base electrode, and to further reduce the size of each region in order to reduce the parasitic capacitance. . For this purpose, it is important to realize such miniaturization with a self-aligned structure.

FIG. 4 is a cross-sectional view showing a process of an NPN transistor using silicon germanium having a self-aligned structure as a base according to the prior art.

As shown in FIG. 4A, a P-type polysilicon film 2 serving as a base electrode and an oxide film 3 are formed on an N-type silicon substrate 1 serving as a collector. Thereafter, using a resist (not shown) patterned in a predetermined region by photolithography as a mask, the oxide film 3 and subsequently the polysilicon film 2 are removed by etching. Thereafter, the resist is removed to expose the silicon substrate 1 which is a region for forming the intrinsic base and the emitter, and at the same time, a base electrode is formed.

Next, as shown in FIG. 4B, the oxide film grown on the entire surface is dry-etched with high anisotropy to form a silicon substrate 1.
The oxide film sidewall 4 is left on the side surface of the polysilicon film 2 in the vicinity of the exposed portion. Then, a P-type impurity in the polysilicon film 2 is introduced into the silicon substrate 1 by heat treatment to form a P-type external base layer 5. Further, a P-type silicon germanium mixed crystal layer 6 serving as a base layer is grown on the entire surface by using an ultra-high vacuum CVD method or the like.

Finally, as shown in FIG. 4C, an N-type polysilicon film 7 serving as an emitter electrode is formed, and N-type impurities in the polysilicon film 7 are introduced into the P-type silicon germanium mixed crystal layer 6 by heat treatment. Then, an N-type emitter layer 8 is formed.

FIG. 5 is a sectional view showing another process of an NPN transistor using silicon germanium having a self-aligned structure as a base according to the prior art.

As shown in FIG. 5A, a P-type polysilicon film 12 as a base electrode and an oxide film 13 are formed on an N-type silicon substrate 11 as a collector. Thereafter, using a resist (not shown) patterned in a predetermined region by photolithography as a mask, the oxide film 13 and subsequently the polysilicon film 12 are removed by etching. Thereafter, the resist is removed to expose the silicon substrate 11 which is a region where the intrinsic base and the emitter are formed, and at the same time, a base electrode is formed. Next, a P-type silicon germanium mixed crystal layer 14 serving as a base layer is grown on the entire surface by using an ultra-high vacuum CVD method or the like.

Then, as shown in FIG. 5B, a resist is applied on the entire surface and then etched back to remove the oxide film 13 and the P-type polysilicon film 12 by etching , thereby leaving the resist 15 in the concave portion. Using the resist 15 as a mask, the silicon-germanium mixed crystal layer 14 on the oxide film 13 is removed by etching.

Finally, as shown in FIG. 5C, after removing the resist, the oxide film grown on the entire surface is dry-etched with high anisotropy to remove the polysilicon film 12 in the vicinity where the silicon-germanium mixed crystal layer 14 is exposed. The oxide film sidewall 16 is left on the side surface. Then, P-type impurities in the polysilicon film 12 are introduced into the silicon substrate 11 by heat treatment,
The mold external base layer 17 is formed. Further, an N-type polysilicon film 18 serving as an emitter electrode is formed, and N-type impurities in the polysilicon film 18 are introduced into the silicon-germanium mixed crystal layer 14 by a heat treatment to form an N-type emitter layer 19.

As described above, according to this method, the emitter region and the base electrode lead-out portion can be formed in a self-aligned manner.
It is possible to reduce the size of the emitter beyond the limit of the photolithography and the distance between the intrinsic base region and the base electrode, thereby reducing the base resistance.

As shown in FIG. 4, an overlap between the P-type external base layer 5 and the P-type silicon germanium mixed crystal layer 6 serving as the base layer poses a problem. That is, if the amount of overlap between the impurities is insufficient, the breakdown voltage between the collector and the emitter is reduced. Further, if the P-type external base layer 5 is made deeper to obtain a sufficient overlap, the high frequency characteristics of the transistor deteriorate due to the effect of the peripheral components of the transistor. Such a problem is inevitable when the P-type silicon-germanium mixed crystal layer 6 serving as a base layer is grown after the formation of the oxide film sidewall 4.

To avoid this problem, a silicon germanium layer may be grown before forming the oxide film sidewall. However, if a silicon germanium layer is also formed on the oxide film on the polysilicon base electrode, a leak or short circuit occurs between the polysilicon emitter electrode and the polysilicon base electrode. As a countermeasure, use a selective growth technique of silicon germanium that does not grow on the oxide film and only grows on silicon, or mask the silicon germanium layer on silicon and etch only the silicon germanium layer on the oxide film There is a method of removing it.

The selective growth of silicon germanium is described, for example, in Applied Physics Letter 1988, 5th.
Vol. 2, page 2242 (Appl. Phys. Le
tt. 52 (1988) p. 2242). That is, the gas source molecular beam epitaxial method is used. Also, IEE Electron Device Letter, 1989, EDL-10, p. 159 (IEEE Electron Device L)
ett. EDL-10 (1989) p. 159). That is, low pressure CVD (L
This becomes possible by using the (RP) method.

[0016]

In the conventional gas source molecular beam epitaxy method, since a large amount of silane gas is stored in the reaction chamber, the growth rate is dangerous and the growth rate is unstable at the same time. Low pressure CVD for lamp heating control
According to the method, there is a great problem in atmosphere control, for example, it is difficult to seal a lamp annealing window of a large-diameter wafer under a high vacuum. As described above, it is very difficult to industrialize by selective growth.

On the other hand, those which have no selectivity but are advantageous for industrialization are disclosed in Applied Physics Letter, 1988, Vol. 53, p. 2555 (Appl. Phys. Le.
tt. 53 (1988) p. 2555). In this method, a hetero-emitter transistor using a silicon-germanium mixed crystal layer as a base is formed by a self-alignment technique using an ultra-high vacuum CVD method.

Next, in another configuration of the prior art, a method is used in which the silicon germanium layer on silicon is masked and only the silicon germanium layer on the oxide film is etched away. However, in this example, if the silicon germanium mixed crystal layer 14 is etched by using the resist 15 or the polysilicon film as a mask in which the recess of the polysilicon base electrode is etched back, the side of the oxide film 13 in the recess is also etched. Crystal layer 14
Remains. Therefore, even if the oxide film sidewall 16 is formed in a subsequent step, the insulation between the P-type polysilicon film 12 or the silicon germanium mixed crystal layer 14 serving as the base electrode and the polysilicon film 18 serving as the emitter electrode is formed at the corner of the base electrode. The thickness of the film becomes thin. For this reason, there are problems in withstand voltage and reliability. This is also the oxide film 1 on the polysilicon film 12.
Even if the silicon-germanium mixed crystal layer 14 is grown after the formation of the silicon nitride layer 3 and before the formation of the oxide film sidewalls 16, this is an unavoidable problem.

[0019]

[0020]

[Means for Solving the Problems] The above problems are solved.
In order to achieve this , the method of manufacturing a semiconductor device according to the present invention includes a first step of forming a nitride film on a silicon substrate of a first conductivity type;
A second step of forming a first polycrystalline silicon film of a second conductivity type on the nitride film, a third step of forming a first oxide film on the first polycrystalline silicon film, A fourth step of opening predetermined regions of the first oxide film and the first polycrystalline silicon film to expose the nitride film, and forming a fourth region of the first oxide film and the first polycrystalline silicon film. A fifth step of forming a second oxide film only on the side wall in the opening, and exposing the silicon substrate by etching away the exposed portion of the nitride film and a portion under the first polysilicon film. A sixth step, wherein the first oxide film, the second oxide film, the exposed portion of the silicon substrate, and the portion where the nitride film under the first polycrystalline silicon film is removed, Growing silicon germanium mixed crystal layer by ultra-high vacuum CVD It has a seventh step, an eighth step of forming a second polycrystalline silicon film of a first conductivity type serving as an emitter electrode on the silicon-germanium mixed crystal layer.

[0021]

According to the production process of the action semiconductor device of the present invention, ultra-high
Silicon germanium grown by vacuum CVD
The layer had no selectivity on oxide and on silicon
Between the oxide film and silicon,
Such as a side wall in an open opening where it is difficult to form a film.
Formed regularly. This allows silicon germanium mixed
Base of bipolar transistor based on crystalline layer
Electrodes, emitter electrodes and emitter regions are self-aligned
Formed, miniaturizing emitter dimensions and reducing base resistance
And the high-frequency characteristics of the transistor can be greatly improved .

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the cross-sectional views of the NPN transistor shown in FIG.

As shown in FIG. 1a, the specific resistance is 10Ωc.
The surface of the (111) or (100) P-type silicon substrate 21 of about m is masked with arsenic or antimony by using a resist (not shown) having a window opened in a predetermined region by photolithography as a mask. Ion implantation is performed at a dose of ¹⁵ cm ^-2 and an acceleration energy of 40 to 60 keV. After the resist is removed by plasma ashing in oxygen gas, heat treatment is performed at 1200 ° C. for about 30 minutes to obtain a sheet resistance of 50 to 100 at a junction depth of 1 to 2 μm.
An N-type buried collector layer 22 of about Ω / □ is formed.
Further, under the conditions of 1050 ° C. and about 80 Torr, using a gas of dichlorosilane and arsine, the specific resistance is 0.5Ωc.
An n-type epitaxial layer 23 of about m is grown to a thickness of 0.5 to 1 μm or less.

Next, S is formed on the entire surface of the N-type epitaxial layer 23.
Low pressure CVD using a mixed gas of iH ₂ Cl ₂ and NH ₃
Then, a silicon nitride film (not shown) having a thickness of about 120 nm is grown. This silicon nitride film removes the element isolation region using a resist pattern (not shown) formed of a photoresist as a mask. The removal is performed by RF etching using a mixed gas of chlorofluorocarbon and bromine. Thereafter, the N-type epitaxial layer 23 is subjected to RF dry etching using SF ₆ gas to have a depth of 0.5 μm, which is slightly larger than about half the thickness of the N-type epitaxial layer 23.
A silicon groove (not shown) is formed. Then, after removing the resist by oxygen plasma ashing, 8
An element isolation LOCOS film 24 having a thickness of 1 μm is selectively formed by pyro-oxidation at a high pressure of about atmospheric pressure using a silicon nitride film as a mask.
It grows to about m. As a result, the silicon trench is filled with the element isolation LOCOS film 24. Then, the silicon nitride film is removed with a phosphoric acid solution.

Next, as shown in FIG. 1B, a polysilicon film serving as a base electrode is formed by low-pressure CVD using silane gas. After the polysilicon film is grown to a thickness of about 400 nm, the sheet resistance of the polysilicon film serving as the base electrode is reduced by one.
In order to reduce it to about 00Ω / □, boron as an impurity diffusion source of the external base layer is introduced into a polysilicon film to be a base electrode by ion implantation at a dose of 5 × 10 ¹⁵ cm ⁻² and an energy of about 40 keV. Here, at the time of ion implantation, in order to prevent a decrease in transistor characteristics due to boron reaching the N-type epitaxial layer 23 through the polysilicon film serving as the base electrode, the thickness of the polysilicon film serving as the base electrode and the ion implantation of boron are prevented. Set energy conditions.

Next, using a resist pattern (not shown) opened to a size of about 1 μm as a mask, SF ₆ , C ₂
Anisotropic dry etching is performed using a mixed gas of ClF ₅ to remove the polysilicon film serving as a base electrode by etching. As a result, the N-type epitaxial layer 23 is exposed. An opening in the intrinsic base region 25 and a polysilicon film base electrode 26 are formed. Thereafter, the resist is removed by oxygen plasma ashing.

Then, a silicon germanium mixed crystal layer 27 is grown on the entire surface by a hot wall type ultrahigh vacuum CVD method at a back pressure of 10 ^-9 Torr. The degree of vacuum during growth is 10 ^-2
About Torr, a growth temperature of 500 to 600 ° C., silane and GeH _{4 as} a growth gas, and diborane as a doping gas. A silicon germanium mixed crystal layer 27 having a stacked structure of a silicon germanium layer of about 50 nm with a boron impurity concentration of about 5 × 10 ¹⁸ cm ⁻³ and a germanium mixed crystal ratio of about 20% and a silicon layer of about 30 nm is grown thereon. .
A silicon germanium layer is formed as a mixed crystal layer on the epitaxial layer 23 in the opening of the intrinsic base region 25 in a poly-form on the surface and side surfaces of the polysilicon base electrode 26.

Next, as shown in FIG. 1C, an oxide film 28 is grown on the entire surface to a thickness of about 500 nm by a normal pressure CVD method at 400 to 500 ° C. using silane gas and oxygen gas. 400-500
The oxide film 8 grown by the normal pressure CVD method at a temperature of 0 ° C. has poor coverage, and the thickness of the oxide film 28 on the surface of the epitaxial layer 23 near the opening of the intrinsic base region 25 and the side surface of the polysilicon base electrode 26 is poly. It is as thin as about half of the thick part on the silicon base electrode 26. Thereafter, oxide film 28 is formed only on polysilicon base electrode 26 by isotropic oxide film etching such as wet etching with hydrofluoric acid.
nm.

Next, as shown in FIG. 1D, an oxide film is grown on the entire surface by a reduced pressure CVD using a mixed gas of dichlorsilane and N ₂ O to a thickness of about 300 nm, and then at 900 ° C. for about 30 minutes in a nitrogen atmosphere. Heat treatment is performed to remove boron impurities in the polysilicon base electrode 26 from the intrinsic base region 25.
Is diffused into the N-type epitaxial layer 23 around the opening.
As a result, a P-type base contact layer 29 having a junction depth of about 0.1 μm is formed.

Thereafter, the grown oxide film is anisotropically etched in a mixed gas of CHF ₃ and oxygen to form an oxide film sidewall 30 on the side surface of the polysilicon base electrode 26. As a result, the emitter electrode lead-out opening 31 is formed in a self-aligned manner with the polysilicon base electrode 26. At this time, the polysilicon base electrodes 26 and 250n are located at any positions around the emitter electrode lead-out opening 31.
It becomes equidistant at intervals of about m.

Finally, the silane gas is decompressed by a low pressure
The polysilicon film grown by about 00 nm is dry-etched with a mixed gas of SF ₆ and C ₂ ClF ₅ using a resist pattern (not shown) exposed and developed while leaving a predetermined region as a mask to form a polysilicon emitter electrode 32. . After removing the resist by oxygen plasma ashing, arsenic is
The ions are implanted into the polysilicon emitter electrode 32 at about keV and about 5 × 10 ¹⁵ cm ⁻² . Then 850-90
Heat treatment at 0 ° C. for about 30 minutes or less in a nitrogen atmosphere;
Arsenic impurities are diffused into the silicon-germanium mixed crystal layer 27 through the emitter electrode lead-out opening 31 to form an N-type emitter layer 33 having a junction depth of about 30 nm.

Next, a second embodiment of the present invention in the same manufacturing method will be described with reference to the cross-sectional views of the NPN transistor shown in FIG.

First, similarly to the first embodiment, an N-type buried collector layer 42, an N-type epitaxial layer 43, an element isolation LOCOS film 44, a polysilicon base electrode 45, a silicon germanium mixed crystal are formed on the surface of a P-type silicon substrate 41. after forming the layer 46, as shown in FIG. 2a, SiH ₂
A silicon nitride film 47 is grown to a thickness of about 50 nm over the entire surface by low pressure CVD using a mixed gas of Cl ₂ and NH ₃ . Subsequently, a polysilicon film is formed on the entire surface by CVD under reduced pressure with silane gas for 500 times.
After the growth of about nm, etch back is performed under a highly anisotropic condition using a mixed gas of SF ₆ and C ₂ ClF ₅ , and the polysilicon film 48 is embedded in the concave portion of the intrinsic base region.

Next, as shown in FIG. 2B, the silicon nitride film on the polysilicon base electrode 45 is removed by RF etching in a mixed gas of Freon and bromine using the polysilicon film buried in the concave portion of the intrinsic base region as a mask. I do. Thereafter, the polysilicon film embedded in the concave portion of the intrinsic base region is removed by RF dry etching using SF ₆ gas. Further, an oxide film 49 of about 200 nm is formed on the surface of the polysilicon base electrode 45 by pyro-oxidation at 900 ° C. using the silicon nitride film remaining in the concave portion of the intrinsic base region as a mask, and then the silicon nitride film is removed with a phosphoric acid solution. I do.

The subsequent steps are the same as those in the first embodiment, and include a P-type base contact layer, an oxide film sidewall,
An emitter electrode lead-out opening, a polysilicon emitter electrode, and an N-type emitter layer are formed.

Next, a third embodiment, which is different from the above two examples, will be described with reference to the cross-sectional view of the NPN transistor shown in FIG.

In the third embodiment shown in FIG .
In the same manner as in the third embodiment , the N- type buried collector layer 62, the N-type epitaxial layer 63, and the element isolation LOCOS film 6
4 after the forming the P-type silicon substrate 61 surface, as shown in Figure 3a, a silicon nitride film 65 on the entire surface by low pressure CVD using a mixed gas of SiH ₂ Cl ₂ and NH ₃ 150n
m. Then, a polysilicon film 68 serving as a base electrode is grown to a thickness of about 400 nm by low-pressure CVD using silane gas. Subsequently, an oxide film 66 serving as an insulating film between the polysilicon electrodes is formed using a mixed gas of dichlorosilane and N ₂ O. It grows about 200 nm by the used low pressure CVD.

Next, similarly to the first and second embodiments, the sheet resistance of the polysilicon film serving as the base electrode is set to 1
In order to reduce it to about 00Ω / □, boron serving as an impurity diffusion source of the external base layer is changed to a dose of 1 × 10 ¹⁶ cm ⁻² ,
Oxide film by ion implantation with energy of about 60 KeV
It is introduced into the polysilicon film 68 through 66 . even here,
At the time of ion implantation, boron penetrates through the polysilicon film 68 to reach the N-type epitaxial layer 63, and the characteristics of the transistor are reduced.
The thickness of the polysilicon film 68 and the
Set conditions such as energy input .

Next, using a resist pattern (not shown) having a size of about 1 μm as a mask, the oxide film 46 is removed by dry etching using a mixed gas of CHF ₃ , ammonia and oxygen. SF ₆ and C ₂ ClF ₅
The polysilicon film serving as the base electrode is etched away by anisotropic dry etching with a mixed gas of As a result, the silicon nitride film 55 is exposed, and an opening of the intrinsic base region 67 and a polysilicon base electrode 68 are formed. After that, the resist is removed by oxygen plasma ashing.

Further, as shown in FIG. 3B, an oxide film having a thickness of about 300 nm is grown on the entire surface by low-pressure CVD using a mixed gas of dichlorosilane and N ₂ O.
Thereafter, the oxide film is anisotropically etched with CHF ₃ and oxygen gas to form an oxide film sidewall 69 on the side wall of the polysilicon base electrode 68 . As a result, the polysilicon base electrode 68 and the opening 7
0 is formed in a self-aligned manner. Thus, as in the first embodiment, the polysilicon base electrodes 68 and 250 can be formed in any direction around the emitter electrode lead-out opening 70.
It becomes equidistant at intervals of about nm.

Next, by isotropic etching such as wet etching using phosphoric acid solution, the silicon nitride film 65 of the opening of the intrinsic base region 67, further lower polysilicon base electrode 68, an opening portion of the intrinsic base region 67 The silicon nitride film 65 is removed from the end of the neighboring polysilicon base electrode 68 to a position where it enters about 0.3 μm.

Finally, as shown in FIG. 3C, the back pressure is 10 ^-9 To.
A silicon germanium mixed crystal layer 71 is grown on the entire surface by a hot wall type ultra-high vacuum CVD method at rr . No.
1. As in the second embodiment , the degree of vacuum during growth is 10 ⁻² T.
The growth temperature is 500 to 600 ° C., silane and GeH ₄ are used as the growth gas, and diborane is used as the doping gas. A silicon germanium mixed crystal layer 71 having a layered structure in which a silicon germanium layer having a boron impurity concentration of about 5 × 10 ¹⁸ cm ⁻³ and a germanium mixing ratio of about 20%, and a silicon layer of about 30 nm is stacked thereon. .

Then, the silane gas is decompressed by a low pressure
The polysilicon film grown to about 00 nm is dry-etched with a mixed gas of SF ₆ and C ₂ ClF ₅ using a resist pattern (not shown) exposed and developed leaving a predetermined region as a mask. Thereby, a polysilicon emitter electrode 62 is formed. Thereafter, the resist is removed by oxygen plasma ashing. Next, at about 60 keV, 5 × 10 ¹⁵ cm ⁻²
Implanting arsenic impurity in the polysilicon emitter electrode 62 on the order of ion implantation. Then, at 850-900 ° C, 3
0 minutes to less thermal treatment carried out in a nitrogen atmosphere, to diffuse arsenic impurities into the silicon-germanium mixed crystal layer 71 through the emitter electrode lead-out opening 60. This gives 3
An N-type emitter layer 73 having a junction depth of about 0 nm is formed. At the same time, the boron impurity in the polysilicon base electrode 58 is diffused into the silicon-germanium mixed crystal layer 71 around the opening of the intrinsic base region 67, and the junction depth becomes 0.1 μm.
A P-type base contact layer 74 of about m is formed.

As described above, the base and the emitter electrode of the silicon heterobipolar transistor based on the silicon germanium mixed crystal layer are formed of the polysilicon film, and the emitter region, the base electrode lead-out part, and the emitter electrode lead-out part are formed by the self. It can be formed consistently. Therefore, miniaturization of the emitter dimensions for reducing the base resistance, miniaturization of the distance between the intrinsic base region and the base electrode, and miniaturization of each region for reducing the parasitic capacitance can be achieved, thereby improving the high frequency characteristics of the transistor. Can be greatly improved. Further, the silicon-germanium mixed crystal layer base can be grown by an ultra-high vacuum CVD method which is advantageous in terms of industrialization although there is no selectivity on an oxide film and on silicon, and has a great advantage in practical use and cost.

[0045]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the semiconductor device is grown by ultra-high vacuum CVD.
Silicon germanium layer on the oxide film and silicon
Between the oxide film and silicon due to lack of selectivity for
Membranes, such as those sandwiched or sidewalls in steep openings
Can be stably formed even in places where it is difficult to form. This allows
Bipolar based on silicon germanium mixed crystal layer
Transistor base, emitter and emitter electrodes
The emitter region is formed in a self-aligned manner,
The thinning and the reduction of the base resistance can be achieved , and the high-frequency characteristics of the transistor can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention in order of steps.

FIG. 2 is a sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in order of steps.

FIG. 3 is a sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps;

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique in the order of steps.

FIG. 5 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique in a process order.

[Explanation of symbols]

 Reference Signs List 21 silicon substrate 22 buried collector layer 23 epitaxial layer 24 element isolation LOCOS film 25 intrinsic base region 26 polysilicon base electrode 27 silicon germanium mixed crystal layer 28 oxide film 29 base contact layer 30 oxide film sidewall 31 emitter electrode lead-out opening 32 poly Silicon emitter electrode 33 Emitter layer

Continuation of front page (56) References JP-A-3-76228 (JP, A) LPATTON, D .; L. HAR AME, J.M. M. C. STORK, and three others, "SiGe-base, Poly- emitter heterojunction bipolar trans istors", (USA), Digest of Technical Paper, Symposium on Physiol, 1989 Int.Cl. ⁷ , DB name) H01L 21/331 H01L 29/73

Claims (2)

(57) [Claims] A first step of forming a nitride film on a silicon substrate of a first conductivity type; and a second step of forming a first polycrystalline silicon film of a second conductivity type on the nitride film. A third step of forming a first oxide film on the first polycrystalline silicon film; and opening the predetermined regions of the first oxide film and the first polycrystalline silicon film to form the nitride film. A fifth step of forming a second oxide film only on sidewalls within openings of the first oxide film and the first polycrystalline silicon film; and A sixth step of exposing the silicon substrate by etching away an exposed portion and a portion under the first polycrystalline silicon film; and removing the first oxide film, the second oxide film, and the silicon substrate. The exposed portion and the nitride film under the first polycrystalline silicon film are removed. A seventh step of growing a silicon-germanium mixed crystal layer by an ultra-high vacuum CVD method, and forming a first conductive type second polycrystalline silicon film serving as an emitter electrode on the silicon-germanium mixed crystal layer. Eighth to form
And a method for manufacturing a semiconductor device. 2. A silicon-germanium mixed crystal layer having a thickness of 10 ^-7 T
The process according to claim 1 Symbol <br/> mounting of the semiconductor device and forming an ultra-high vacuum CVD method using 10 ^-1 Torr or less of decompression in the following back pressure orr.