JP3184118B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having a write data input signal line pair (write bus pair), and more particularly to a dynamic random access memory (DR).
AM).

[0002]

2. Description of the Related Art As shown in FIG. 8, a connection portion from a sense amplifier of a conventional DRAM to a common input / output data signal line (RWBS line) is a digit line pair, a sense amplifier pair, and a first transfer gate (TG) 1. , Second transfer gate (TG) 2, write data input signal line pair (write bus pair), read output signal line pair (read bus pair), write data control circuit 3, read data control circuit 7, common It is composed of input / output data signal lines (RWBS lines).

A conventional DRAM includes a write data control circuit 3 for connecting an RWBS line to a write bus pair, and TG1 and TG2 between the write bus pair, the digit line pair and the sense amplifier. ing.

FIG. 9 shows a write operation waveform diagram of a conventional DRAM.
Shown in In a conventional write operation, first, a write control signal (WCTRL) for selecting a circuit to operate at the time of writing is used.
Thereby, the write data control circuit 3 is activated. As a result, the RW to which write data has already been given to the outside
Data on the BS line is transmitted to the write bus pair.

Next, a Y switch (YSW) 1 selected by an address signal taken from the outside is activated, and TG1
Becomes conductive. Thereafter, only during a write operation, a write clock (W) for performing a clocking operation in synchronization with an external signal.
CLK) is in the operation period, TG2 becomes conductive, data of the write bus pair is transmitted to digit line pair 1, and TG2
1 and TG2, writing to a target memory cell is performed.

In the case of high-speed access such as burst write, the YSW changes continuously in synchronization with the clock. When this YSW is switched, WCLK becomes LO.
TG2 is turned off, and the TG2 is turned off to disconnect the write bus pair from the digit line pair.

When the YSW is changed, as shown in FIG. 10, the reset of YSW1 causes a delay in resetting of YSW1 and YSW2.
There is a possibility that a plurality of lines are temporarily activated, for example, when the line is activated. As a result, a cell other than the target cell is connected to the write bus pair, and cell data other than the target cell may be destroyed.

Therefore, according to the prior art, when the YSW is changed, the WCLK synchronized with the external signal generated during the write operation is used.
Therefore, it is necessary to perform control after disconnecting all digit line pairs and the write bus pairs.

[0009]

Problems with the prior art are as follows.
In a semiconductor memory device, in particular, the chip area is increased due to an increase in the number of elements in the array section. Therefore, it is necessary to reduce the area as much as possible. That is, it is impossible to reduce the chip area such as elements and signal lines.

[0010] The reason is that, in a place where there are many repetitive elements such as an array portion, writing to a target memory cell is controlled by a write bus pair for data transfer and a control signal line for preventing erroneous writing. This is because both the element and the signal line are minimized in the conventional control method, and it is difficult to further reduce the element and the signal line.

An object of the present invention is to provide a semiconductor memory device having a reduced chip area.

[0012]

According to the present invention, there is provided a semiconductor memory device comprising: a digit line pair comprising a plurality of memory cells and one sense amplifier; and a write data input signal line pair (write bus) having a plurality of digit line pairs connected. Pair) and a read output signal line pair (read bus pair), and a Y switch (YSW) for connecting the digit line pair selected by the selection signal generated by the address signal to the write bus pair and the read bus pair. A semiconductor memory device having a write data control circuit for controlling writing of data of a common input / output data signal line (RWBS line) to the write bus pair in synchronization with a clock; A precharge circuit for precharging the write bus pair to the same potential when the YSW is switched is provided.

The write data control circuit according to the present invention comprises:
By adding write control to the write bus pair, the chip area is reduced.

As a means for this, a period for precharging the signal line pair of the write bus pair to the same potential is provided by utilizing the characteristics of a sense amplifier that requires a difference potential for a write operation to an arbitrary memory cell. By changing the YSW, it has a function equivalent to the conventional one that prevents erroneous writing while reducing the number of elements.

According to the present invention, a write control signal is added to a data write signal line. For this reason, it is possible to reduce the number of signal lines and transfer gate circuits dedicated to write control in the array unit without requiring them.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a connection portion from a sense amplifier to an RWBS line of a DRAM of the present invention is a digit line pair, a sense amplifier, a first transfer gate 1 (TG) 1, a write bus pair, Read bus pair, write data control circuit 3, read data control circuit 7, RW
It is composed of BS line.

The present invention includes a write data control circuit 3 that connects the RWBS line and the write bus pair, and has a configuration in which TG1 is provided between the write bus pair, the digit line pair, and the sense amplifier.

FIG. 2 shows a waveform diagram of the write operation of the DRAM of the present invention. In the write operation, first, a write bus pair and an output signal of the write data control circuit 3 are connected by WCTRL for selecting a circuit that operates at the time of writing. Next, YSW1 selected by an address signal taken in from the outside
As a result, TG1 becomes conductive, and the write bus pair and the digit line pair are connected. At this time, read data
The control circuit is disabled by a read control signal not shown here.
It is activated, and the read bus pair and
The jet line pair becomes conductive, but does not affect the write operation.
No. Thereafter, the write data control circuit 3 is activated during the operation period of the WCLK for performing the clocking operation generated only at the time of writing in synchronization with the external signal, and the data on the RWBS line to which the write data has already been supplied from the outside is used. It is transmitted to the light bus pair. TG when YSW1 is already selected
1 is in a conductive state and the write bus pair and the data line pair are in a connected state, so that data of the write bus pair is transmitted to the digit line pair 1 and writing to a target memory cell is performed.

In the case of high-speed access such as burst write, the YSW changes continuously in synchronization with the clock. When this YSW is switched, WCLK becomes LO.
In the write data control circuit 3, both the write bus pair are precharged to a predetermined voltage while the WCLK is LOW. By doing so, the digit line pair that is instantaneously connected to the write bus pair also has the same potential, so that the data in the memory cell can be held as it is, and no data destruction occurs.

In a state other than the time of the write operation, the write data control circuit 3 is inactivated by the non-selected state WCTRL, and the write bus pair and the RWBS line are disconnected. It is in the impedance state.

[0021]

3 and 4 show a first embodiment of the present invention. FIG. 3 shows a connection state from a sense amplifier to a RWBS line of a DRAM of the present embodiment.
Sense amplifier, first transfer gate 1 (TG
1), a write bus pair, a read bus pair, a write data control circuit 3, a read data control circuit 7, and an RWBS line.

The DRAM of this embodiment has a write data control circuit 3 connecting the RWBS line and the write bus pair, and has a configuration in which TG1 is provided between the write bus pair, the digit line pair and the sense amplifier. I have.

FIG. 4 is a detailed diagram of the write data control circuit 3. The write data control circuit 3 includes a data control circuit 5 and a connection control circuit 6 (CCTRL). The write data control circuit 3 of the present embodiment has a configuration in which a data control circuit 5 and a CCTRL 6 are provided between the RWBS and the write bus.

In the write operation of the DRAM of the present invention, first, WCTRL for selecting a circuit to be operated at the time of write performs
CTRL 6 is activated, and the write bus pair and the output signal of data control circuit 5 are connected. Next, TG is performed by YSW1 selected by an address signal taken from outside.
1 becomes conductive, and the write bus pair and the digit line pair are connected.

Thereafter, the data control circuit 5 is activated during the operation period of WCLK for performing a clocking operation generated only at the time of writing in synchronization with an external signal, and the data on the RWBS line to which write data has already been supplied from the outside. Is transmitted to the light bus pair. TG when YSW1 is already selected
1 is in a conductive state, and the write bus pair and the digit line pair are in a connected state, so that data of the write bus pair is transmitted to the digit line pair 1 and writing to a target memory cell is performed.

In the case of high-speed access such as burst write, the YSW changes continuously in synchronization with the clock. When this YSW is switched, WCLK becomes LO.
The data bus is precharged to the VCC potential together with the write bus pair during a period when the WCLK is LOW by the data control circuit 5. By doing so, the digit lines that are instantaneously connected to the write bus pair also have the same potential, so that the data in the memory cell can be held as it is, and no data destruction occurs.

In a state other than the write operation, the same potential is output from the write data control circuit 3 by the WCLK during the operation stop period, but the WCTRL in the non-selected state is output.
As a result, the write bus pair and the output signal of the data control circuit 5 are disconnected by the CCTRL 6, and the write bus pair is in a high impedance state.

FIG. 5 shows a second embodiment of the present invention, in which the precharge of the write bus pair is set to the GND potential.

The present embodiment differs from the first embodiment only in the precharge potential and the data control circuit 5 of the write bus pair shown in FIG.

FIG. 6 shows a third embodiment of the present invention, in which the precharge of the write bus pair is performed at a potential of 1/2 VCC (HVC).
C).

In this embodiment, the precharge potential of the write bus pair and the data control circuit 5 shown in FIG.
But there is no fundamental difference in the control operation.

FIG. 7 shows a fourth embodiment of the present invention, in which the precharge of the write bus pair is set to the VCC potential.

This embodiment differs from the first embodiment only in the data control circuit 5 and the CCRTL 6 of the write bus pair shown in FIG.

[0034]

According to the present invention, the WCRTL signal and the TG2 transistor can be deleted for each array sense amplifier row without damaging the data when the YSW is continuously changed, as in the prior art. The chip area can be reduced.

For example, in a 0.35 μm process,
2.3 μm reduction is possible for each sense amplifier row, and 0.21 m for a 16M synchronous DRAM.
The chip area of m ² can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a write circuit in the vicinity of an array unit according to the present invention.

FIG. 2 is a waveform chart showing the operation of the write system of the present invention.

FIG. 3 shows a first embodiment of the present invention in which
It is a figure showing the example set as CC potential.

FIG. 4 is a diagram illustrating an example of a write data control circuit according to the first embodiment;

FIG. 5 shows a second embodiment of the present invention in which the precharge is G;
FIG. 7 is a diagram illustrating an example of a write data control circuit when the potential is set to an ND potential.

FIG. 6 shows a third embodiment of the present invention in which precharge is set to H;
FIG. 9 is a diagram illustrating an example of a write data control circuit when the potential is set to a VCC potential.

FIG. 7 shows a fourth embodiment of the present invention in which the precharge is V
FIG. 4 is a diagram illustrating an example of a write data control circuit when a CC potential is set.

FIG. 8 is a block diagram illustrating a configuration of a conventional write circuit near an array unit.

FIG. 9 is a waveform diagram showing the operation of a conventional write system.

FIG. 10 is a diagram illustrating an example in which a multi-address is provided when a YSW is switched.

[Explanation of symbols]

 1 TG1 (transfer gate for YSW) 2 TG2 (transfer gate for WCLK) 3 control circuit block for write data 4 BUF (buffer circuit) 5 data control circuit 6 CCTRL (connection control circuit) 7 control circuit for read data

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 11/4096

Claims (7)

(57) [Claims] 1. A digit line pair comprising a plurality of memory cells and one sense amplifier, a write data input signal line pair having a plurality of digit line pairs connected thereto , the digit line pair and the write data input signal line pair.
And a transformer provided between the
A write gate, a Y switch for controlling the transfer gate, and a common input / output data signal line pair written to the write data input signal line pair in synchronization with a clock.
Bar that switches the Y switch continuously in synchronization with
The semiconductor memory device characterized by having the write data control circuit of the write data input signal line pair during the strike write control is performed to the same potential. 2. The write data control circuit according to claim 1 , wherein
Precharge the input signal line pair for write data to the same potential
2. The method according to claim 1, wherein a precharge circuit is provided.
Placing the semiconductor memory device. 3. A write control signal for selecting the write data control circuit, and a write clock signal generated in synchronization with the clock and supplied to the write data control circuit, wherein the precharge circuit is 3. The semiconductor memory device according to claim 2, wherein the precharge is performed when the write control signal is in a selected state and the write clock signal is in an operation stop period. 4. The write data control circuit, when the write control signal is in a non-selected state, sets an output to a high level.
4. The semiconductor memory device according to claim 3 , wherein impedance is set. 5. The semiconductor memory device according to claim 3, wherein said precharge potential is a GND potential. 6. The method according to claim 6, wherein the potential of said precharge is Ｖ VCC.
4. The semiconductor memory device according to claim 3, wherein the potential is a potential. 7. The semiconductor memory device according to claim 3, wherein said precharge potential is a VCC potential.