JP3118407B2 - Digital video processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video processing apparatus for digitizing an analog composite video signal and performing reproduction processing.

[0002]

2. Description of the Related Art After converting an analog video signal into a digital video signal, it is digitally demodulated into a baseband signal in accordance with a digital video signal processing standard (for example, CCIR601), and is digitally processed. In a device that returns to a video signal, it is usual that a sampling clock is created in synchronization with a horizontal synchronization signal, and a luminance signal and a chrominance signal are demodulated and modulated according to the sampling clock. Specifically, a horizontal synchronizing signal is extracted from a digital video signal, a phase difference between the extracted horizontal synchronizing signal and a standard horizontal synchronizing signal is detected line by line, and a sampling clock is generated according to the phase difference. It is. This sampling clock generation method is called a Line Locked PLL method.
Since the horizontal and vertical synchronizing signals can be accurately extracted by sampling the analog video signal for digitization using the sampling clock thus obtained, the time between the horizontal and vertical synchronizing signals and the luminance signal can be obtained. It is possible to demodulate and modulate the luminance signal without deviating the positional relationship.

Aside from the line locked PLL system, a burst locked PLL system which generates a sampling clock in synchronization with a color burst signal in a digital video signal is also known. In the case of the burst locked PLL system, a color burst signal is extracted from a digital video signal, a phase difference between the extracted color burst signal and a standard color burst signal is detected, and a sampling clock is generated according to the phase difference. Is performed. If digital video processing is performed using a sampling clock obtained by the burst locked PLL system, color signals can be demodulated and modulated stably.

[0004]

SUMMARY OF THE INVENTION Line locked PLL
When the sampling clock is generated by the method,
Since the luminance signal is synchronized with the horizontal synchronizing signal, the temporal positional relationship between the sampled horizontal and vertical synchronizing signals and the luminance signal is normally maintained. However, VCR
(Video Cassette Recorder) and other video equipment have fluctuations and errors in the synchronization signal. If a color signal is processed using a sampling clock obtained based on the synchronization signal, the sampling clock fluctuates and the color signal is It cannot be properly processed, and, for example, color demodulation may cause color degradation. In addition, when the composite video signal is Y / C-separated into a luminance signal and a chrominance signal, the degree of separation is deteriorated.

On the other hand, when the sampling clock is generated by the burst locked PLL system, the color signal extracted from the sampled video signal is kept stable because the color signal is synchronized with the color burst signal. It is. However, in the luminance signal, the temporal positional relationship between the synchronization signal and the luminance signal may not be normally maintained due to fluctuation or error of the synchronization signal for each video device. In the case of digital video processing, the luminance signal and the chrominance signal are separated from the synchronizing signal, demodulated, and then modulated to add the synchronizing signal.
When separating the synchronizing signal from the luminance signal, the error or frequency fluctuation caused by the jitter component of each video equipment causes
Synchronization error may occur around the sampling clock. Digital demodulation and modulation of such out-of-sync luminance signals has the problem of deteriorating image quality.

An object of the present invention is to provide a digital video processing apparatus capable of processing both a luminance signal and a chrominance signal in synchronization with a synchronization signal.

[0007]

According to the digital video processing apparatus of the present invention, A / D conversion means for digitizing an analog composite video signal in accordance with a sampling clock signal, and digitalization by the A / D conversion means. Digital synchronization extracting means for separating and extracting a luminance signal and a color signal from a composite video signal; means for digitally demodulating a color signal to generate a color burst signal and a color difference signal; Means for generating a color phase error signal according to the phase difference; PLL means for generating the sampling clock signal at a frequency and phase according to the color phase error signal; and separation and extraction of an analog synchronizing signal from an analog composite video signal. An analog synchronization extracting unit, wherein the leading edge of the analog synchronization signal is the sampling clock signal Synchronous position detecting means for detecting which of the respective periods the period is equally divided and generating a position information signal indicating the detection result, and the luminance signal and the color difference signal in accordance with the position information signal Phase adjusting means for adjusting the phase of the
After synchronizing to the analog clock signal,
Means for separating and extracting the analog horizontal sync signal from the
Extracts phase difference between log horizontal sync signal and standard horizontal sync signal
And integrate it and output it as a synchronous phase error signal
Synchronous phase detection means, and the synchronous phase error signal
Corrects the color phase error signal and supplies it to the PLL means
, And digitized by A / D conversion means.
Digital horizontal sync signal and digital
Digital sync separator for separating and extracting vertical sync signal
And a signal indicating the phase difference output from the synchronous phase detecting means.
The digital horizontal synchronizing signal and the digital
Synchronization timing to adjust the output timing of the vertical synchronization signal
And a timing adjusting means .

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the video processing apparatus shown in FIG. 1, a video input samples an analog composite video signal output from a video reproducing apparatus such as a VCR (video cassette recorder) in accordance with an internal clock signal (sampling clock signal) described later. An A / D converter 1 for converting the digital video signal into a digital video signal is provided. The video signal digitized by the A / D converter 1 is supplied to a digital sync separation circuit 3 via an LPF (low-pass filter) 2. . The synchronization separation circuit 3 filters the digital video signal to extract a digital synchronization signal in the digital video signal, and generates a gate signal during a period in which the synchronization signal can be extracted. A digital synchronization AFC (automatic frequency control) circuit 4 and a synchronization dropout correction circuit 5 are connected to the synchronization separation output of the synchronization separation circuit 3. The digital synchronizing AFC circuit 4 generates a pseudo synchronizing signal at the time when the next digital synchronizing signal of the extracted one digital synchronizing signal is to be generated. The synchronization dropout compensating circuit 5 determines the dropout of the digital synchronization signal output from the synchronization separation circuit 3 according to the generation timing of the analog synchronization signal separated from the analog synchronization separation circuit 10 described later. Is supplied to the synchronization timing adjustment buffer 6 after compensating for the dropout of the digital synchronization signal by the pseudo synchronization signal.

The synchronous timing adjustment buffer 6 comprises two shift registers 36 and 37 and multiplexers 38 and 39, as shown in FIG. One shift register 3
6 is supplied with a digital horizontal synchronization signal from the synchronization dropout compensation circuit 5, and the other shift register 37 is supplied with a digital vertical synchronization signal from the synchronization dropout compensation circuit 5. These shift registers 36 and 37 have holding positions for 10 clocks. The multiplexer 38 selects and outputs one of the ten clock holding outputs of the shift register 36 in accordance with a phase information signal output from the synchronous phase detector 12 described later. Similarly, the multiplexer 39 is connected to the 10
One of the held outputs for the clock is selected and output according to a phase information signal output from a synchronous phase detector 12 described later.

The video input is connected to an analog sync separation slicer 7 in addition to the A / D converter 1 described above. The analog sync separation slicer 7 separates and extracts a sync signal from the analog video signal according to the gate signal from the sync separation circuit 3. The output of the analog sync separation slicer 7 is connected to a sync position detector 8. Synchronous position detector 8
Includes a duty correction circuit 31, D flip-flops (DFF) 32a to 32f, and an encoder 33, and receives a six-phase clock signal output from a clock generator 9 described later, as shown in FIG. , The six-phase clock signal is converted into a duty
After that, the falling edge position of the extracted synchronization signal is detected by the D flip-flops 32a to 32f and the encoder 33 to generate position information and generate an analog synchronization signal synchronized with the internal clock. . The synchronized analog synchronization signal is supplied to the analog synchronization separation circuit 10. D flip-flop 32a
.About.32f operate only when a gate signal is supplied from the synchronization separation circuit 3. Note that FIG. 3 shows the supply line of the gate signal only to the D flip-flop 32f, and the other D flip-flops 32a to 32f
The gate signal line to 32e is omitted. Also, 6
The phase clock signal is an internal clock signal (frequency 13.5 M
(Hz) is a signal having a phase difference obtained by dividing the cycle of (Hz) into six equal parts.
Further, the internal clock signal may be generated and used as a multi-phase clock signal other than six, for example, an eight-phase clock signal.

An analog sync separation circuit 10 separates an analog vertical sync signal and a horizontal sync signal from a synchronized analog sync signal with reference to a sync separation output from the sync separation circuit 3. The analog vertical synchronizing signal and the horizontal synchronizing signal are used as dropout detection switching timing of the synchronous dropout correction circuit 5 and are also supplied to the standard video detector 11 and the synchronous phase detector 12.

The standard video detector 11 has a clock counter (not shown) that is reset by a horizontal synchronizing signal, and calculates a difference between the total number of samples for each line obtained from the clock counter and the total number of samples at the time of the standard signal. To detect
The difference is integrated for about two frames, and if the maximum value and the minimum value of the integrated value are within two clocks, it is determined that the synchronization deviation is within the specified range. If the synchronization deviation is within the specified range,
The standard video detector 11 generates a non-specified signal, and generates a non-specified signal if the synchronization error is out of a specified range. The synchronization phase detector 12 also has a clock counter (not shown) reset by the horizontal synchronization signal, and detects a difference between the total number of samples for each line obtained from the clock counter and the total number of samples at the time of the standard signal. , A phase information signal corresponding to the difference is generated, and the difference is integrated and output as a phase control signal.

A comb filter 13 is connected to the output of the A / D converter 1. The comb filter 13 separates a digital luminance signal and a digital chrominance signal from the digital video signal output from the A / D converter 1 and outputs them. The digital luminance signal is supplied to a level control circuit 14, and the digital chrominance signal is supplied to a color decoder 15. The level control circuit 14 adjusts the level of the digital luminance signal and supplies it to the luminance data compensating circuit 16. The color decoder 15 outputs a digital color difference signal R-
A color burst signal is generated together with the Y signal and the BY signal. The digital color difference signal is supplied to a color difference data compensating circuit 17, and the color burst signal is supplied to a color phase detector 18.

The output signals of the standard video detector 11 are supplied to a luminance data compensating circuit 16 and a chrominance data compensating circuit 17, respectively. The luminance data compensating circuits 16 have phase characteristics different from each other by 60 degrees as shown in FIG. The filter comprises six filters 41a to 41f, a multiplexer 42 for selecting any one of the filters 41a to 41f, and a changeover switch 43 for relaying and outputting a selected output by the multiplexer 42 in response to an unspecified signal. When a signal is supplied, the digital luminance signal is output as it is via the changeover switch 43, and when an out-of-spec signal is supplied, any one of the six filters 41a to 41f according to the position information signal from the synchronous position detector 8 is supplied. 1 is selected, and the phase of the digital luminance signal is adjusted by the selected filter and output. The chrominance data compensating circuit 17 is also configured in the same manner as the luminance data compensating circuit 16, and outputs the digital chrominance signal as it is when the specified signal is supplied, and outputs the position information from the synchronous position detector 8 when the specified signal is supplied. The digital color difference signal is adjusted in phase according to the signal and output.

The color phase detector 18 detects a phase difference between the supplied color burst signal and a standard color burst signal, and generates a color phase error signal indicating the phase difference. The color phase error signal is supplied to a phase error control circuit 19. The phase error control circuit 19 adjusts the color phase error signal according to the phase control signal supplied from the synchronous phase detector 12 and outputs the adjusted signal. A D / A converter 21 is connected to an output of the phase error control circuit 19 via an LPF 20. The LPF 20 integrates the color phase error signal output from the phase error control circuit 19 and supplies it to the D / A converter 21. The D / A converter 21 converts the integrated color phase error signal into an analog signal. A master clock oscillation circuit (VCXO) is provided at the output of the D / A converter 21.
The master clock oscillation circuit 22 is a voltage-controlled crystal oscillation circuit, and generates a master clock signal with a frequency and a phase corresponding to an analogized color phase error signal. The reference frequency of the master clock signal is 40.5 MHz, but is not limited thereto. For example, when the eight-phase clock signal is generated as described above, the reference frequency is 54 MHz.

The master clock signal generated by the master clock oscillator 21 is supplied to the clock generator 9 described above. The clock generator 9 divides the master clock signal by three to generate an internal clock signal that controls the timing in the present apparatus, and also generates a six-phase clock signal having a phase different from each other by 60 degrees. Next, the operation of the video processing device having such a configuration will be described. First, a sync signal of an input composite video signal is separated by an analog sync separation slicer 7, and the separated sync signal is supplied to an analog sync separation circuit 10 as a sync signal synchronized with an internal clock signal in a sync position detection circuit 8. . The analog synchronization separation circuit 10 separates a synchronization signal synchronized with the internal clock signal into a horizontal synchronization signal and a vertical synchronization signal. Based on the number of internal clocks for each cycle of the separated horizontal synchronization signal, the standard video detector 11 determines whether or not the synchronization deviation of the horizontal synchronization signal is within a specified range.

The six-phase clock signal supplied from the clock generator 9 to the synchronous position detecting circuit 8 has a phase relationship as shown in FIG. 5 with respect to the master clock signal. This 6
The duty ratio of the waveform of the phase clock signal is further adjusted by a duty correction circuit 31 in the synchronous position detection circuit 8 as shown in FIG.
It is corrected to about 30% as shown in FIG. The duty-corrected 6-phase clock signal is supplied to the D flip-flop 32
The synchronization signals from the analog synchronization separation slicer 7 are supplied to the data terminals of the D flip-flops 32a to 32f. As shown in FIG. 6A, two signals in the six-phase clock signal which are at a high level when the synchronization signal falls are detected by the D flip-flops 32a to 32f as shown in FIG. 6C. You. The outputs of the D flip-flops 32a to 32f are code-converted by the encoder 33, and the output signal of the encoder 33 becomes a 6-bit position information signal indicating the position of the synchronization signal. In the case of FIG. 6C, since the outputs of the D flip-flops 32c and 32d are at a high level, the output of the encoder 33 is the third phase (for example,
001000) is generated.

The input composite video signal is digitized by the A / D converter 1 and supplied to the digital sync separation circuit 3 via the LPF 2. The digital sync separation circuit 3 separates and outputs a sync signal in the digitized composite video signal. The separated digital synchronization signal is supplied to a digital synchronization AFC circuit 4 and a synchronization dropout compensation circuit 5. If no dropout occurs in the separated digital synchronization signal, the output horizontal and vertical synchronization signals of the digital synchronization separation circuit 3 are supplied to the synchronization timing adjustment buffer 6 as they are. If dropout occurs in the separated digital synchronization signal, the synchronization dropout compensation circuit 5 sets the digital synchronization A
The pseudo synchronization signal from the FC circuit 4 is output to the synchronization timing adjustment buffer 6.

The standard video detector 11 has a clock counter (not shown) reset by a horizontal synchronizing signal, and calculates a difference between the total number of samples for each line obtained from the clock counter and the total number of samples at the time of the standard signal. To detect
The difference is integrated for about two frames, and if the maximum value and the minimum value of the integrated value are within two clocks, it is determined that the synchronization deviation is within the specified range. If the synchronization deviation is within the specified range,
The standard video detector 11 generates a non-specified signal, and generates a non-specified signal if the synchronization error is out of a specified range. The synchronization phase detector 12 also has a clock counter (not shown) reset by the horizontal synchronization signal, and detects a difference between the total number of samples for each line obtained from the clock counter and the total number of samples at the time of the standard signal. , A phase information signal corresponding to the difference is generated, and the difference is integrated and output as a phase control signal.

In the synchronous timing adjustment buffer 6 to which the phase information signal is supplied, when the standard signal is supplied from the standard video detector 11, the shift register 3
At steps 6 and 37, the digital horizontal or vertical synchronizing signal is output without being shifted. However, when a non-standard signal is supplied from the standard video detector 11, the phase information signal is supplied to the multiplexers 38 and 39 in the synchronization timing adjustment buffer 6, and the shift registers 36 and 37 are provided.
Any one of the ten held outputs of the above is designated. Therefore,
The synchronization timing adjustment buffer 6 includes a shift register 36,
By selecting the holding position 37, the phase of the digital horizontal or vertical synchronizing signal is advanced or delayed by the number of clocks corresponding to the phase information signal, and the digital synchronizing signal adjusted in phase in this manner is output. .

On the other hand, the digital luminance signal output from the comb filter 13 is supplied to a luminance data compensating circuit 16 after its level is adjusted by a level control circuit 14. The digital color signal output from the comb filter 13 is supplied to a color difference data compensating circuit 17 as an RY signal and a BY signal by a color decoder 15. When a standard signal is supplied from the standard video detector 11 to the luminance data compensating circuit 16, the digital luminance signal whose level has been adjusted by the level control circuit 14 is output as it is via the switch 43. However, when a nonstandard signal is supplied from the standard video detector 11, the filter selection output of the multiplexer 42 is output via the switch 43 according to the position information signal supplied from the synchronous position detection circuit 8. That is, the phase of the digital luminance signal is adjusted by any one of the filters 41a to 41f corresponding to the position information indicated by the position information signal, and is output. On the other hand, in the color difference data compensating circuit 17 as well, when the standard signal is supplied from the standard video detector 11, the RY signal and the BY signal from the color decoder 15 are output as they are. However, when an out-of-spec signal is supplied from the standard video detector 11, the RY signal and the BY signal are phase-adjusted with a phase characteristic corresponding to the position information signal supplied from the synchronous position detection circuit 8 and output. Is done.

The color burst signal output from the color decoder 15 is supplied to a color phase detector 18 where the phase difference between the color burst signal and a standard color burst signal is detected, and a color indicating the phase difference is detected. The phase error signal is supplied to the phase error control circuit 19. The color phase error signal is level-adjusted in the phase error control circuit 19 according to the phase control signal supplied from the synchronous phase detector 12, and then output to the LPF 20. L
In the PF 20, the color phase error signal output from the phase error control circuit 19 is integrated, whereby the high frequency component of the color phase error signal is removed and the D / A converter 2
1 is supplied. The integrated color phase error signal is D
Since the signal is converted into an analog signal in the / A converter 21, the master clock oscillation circuit 22 generates a master clock signal at a frequency and a phase corresponding to the analog color phase error signal. This master clock signal is frequency-divided by 3 in a clock generator 9 to generate an internal clock signal, that is, a sampling clock signal.

As described above, in the digital video processing apparatus according to the present invention, the internal clock signal (13.5 MHz) is generated according to the color burst phase error between the color burst signal and the standard color burst signal. The period of the clock signal is divided into six equal parts, and it is detected which of the six equal parts the analog synchronizing signal separated from the composite video signal is located. The digital luminance signal is detected in accordance with the detected position information. In addition, since the phase of each of the color difference signals is adjusted, it is possible to compensate for the synchronization shift between the digital luminance signal and the color difference signal with high accuracy. Further, a phase error between the analog horizontal synchronizing signal synchronized with the internal clock and the standard horizontal synchronizing signal is detected, and a color burst phase error is adjusted according to the synchronizing phase error, thereby providing feedback to the internal clock signal generating system. Are doing. This makes it possible to compensate for irregular positional shifts of the synchronization signal between the internal clocks. In addition, by providing the synchronization timing adjustment buffer, a position shift such that the digital synchronization signal detected from the digital composite video signal is shifted by, for example, one sampling clock due to a jitter component of the video equipment is caused according to the phase information signal. Can be compensated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a synchronization timing adjustment buffer.

FIG. 3 is a diagram illustrating a partial configuration of a synchronous position detection circuit.

FIG. 4 is a diagram showing a specific configuration of a luminance data compensation circuit.

FIG. 5 is a diagram showing a master clock signal and a six-phase clock signal.

FIG. 6 is a waveform chart showing a synchronous position detection operation.

[Description of Signs of Main Parts]

 Reference Signs List 6 synchronization timing adjustment circuit 8 synchronization position detection circuit 12 synchronization phase detector 13 comb filter 16 luminance data compensation circuit 17 color difference data compensation circuit 18 color phase detector 19 phase error control circuit 22 master clock oscillation circuit

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-60-42996 (JP, A) JP-A-8-56369 (JP, A) JP-A-1-175480 (JP, A) JP-A-3- 235598 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 9/44-9/78

Claims (6)

(57) [Claims] 1. An analog composite video signal is sampled.
A / D conversion means for digitizing according to a clock signal
And a composite image digitized by the A / D conversion means.
A digital signal for separating and extracting a luminance signal and a chrominance signal from an image signal
Digital synchronization demodulation means for digitally demodulating the color signal and a color burst signal and
Means for generating a color difference signal and a standard color burst signal.
Means for generating a color phase error signal in accordance with the phase difference of said, and said frequency and phase according to said color phase error signal
PLL means for generating a sampling clock signal; and separating an analog synchronizing signal from the analog composite video signal.
Analog synchronization extracting means for separating and extracting, and the leading edge of the analog synchronization signal is
Any of the periods obtained by equally dividing the period of the lock signal into multiple
Location information indicating the location
Synchronous position detecting means for generating a signal, and the luminance signal and the color difference signal in accordance with the position information signal
Adjust the phasePhase adjusting means; Converting the analog synchronization signal to the sampling clock signal
After synchronizing to the analog
Means for separating and extracting the flat synchronization signal; Phase between the analog horizontal synchronization signal and the standard horizontal synchronization signal
Extract the difference and integrate it as a synchronous phase error signal
Synchronous phase detection means for outputting, The color phase error according to the synchronization phase error signal
Means for correcting the signal and supplying the corrected signal to the PLL means; Composite video digitized by the A / D conversion means
Digital horizontal sync signal and digital vertical from image signal
Digital synchronization separation means for separating and extracting a synchronization signal; A signal indicating a phase difference output from the synchronous phase detecting means
The digital horizontal synchronizing signal and the digital
Adjust the output timing of the vertical sync signal. Period
Adjusting means, A digital video processing device comprising: Means for generating a prescribed signal when the frequency of the analog horizontal synchronizing signal is substantially equal to the frequency of a standard horizontal synchronizing signal, wherein the phase adjusting means generates the luminance signal and the luminance signal when the prescribed signal is generated. claim 1, characterized in that directly outputs without phase adjustment of the chrominance signal
The digital video processing device according to the above. 3. When the frequency of the analog horizontal synchronizing signal is substantially equal to the frequency of a standard horizontal synchronizing signal, the synchronizing timing adjusting means generates the prescribed signal when the prescribed signal is generated. 9. The method according to claim 8, wherein the synchronizing signal and the digital vertical synchronizing signal are output without adjusting the output timing.
2. The digital video processing device according to 1. 4. The phase control means for adjusting a level of the color phase error signal according to the synchronization phase error signal, an integration means for integrating an output signal of the phase control means, and the integration means. D / A conversion means for converting the output signal of the D / A converter into an analog signal, means for generating a master clock signal at a frequency and a phase corresponding to the output analog signal of the D / A conversion means, and frequency division of the master clock signal And a sampling clock generating means for generating the sampling clock signal.
The digital video processing device according to claim 1 . 5. The sampling clock generating means includes means for dividing the master clock signal to generate a multi-phase clock signal composed of a plurality of clock signals having different phases from each other. The digital image processing device according to claim 1, wherein the position information signal is generated according to a phase clock signal and the analog synchronization signal. 6. A digital synchronizing said digital horizontal sync signal outputted from the separation unit and daisy according to claim 1, wherein a dropout compensation means for dropout compensation of the digital vertical synchronizing signal <br / > Tal video processing device.