JP3120983B2 - Capacitors in integrated circuits - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to the field of integrated circuits, and more particularly to forming capacitors in integrated circuits.

2. Description of the Related Art In the field of integrated circuits, in order to realize highly complex circuits in a small chip size of an integrated circuit and to reduce a cost per function, circuit elements in the smallest achievable surface area can be achieved. Is preferably formed. For circuits with capacitors, such as analog-to-digital converters (ADCs) and non-volatile memories that use capacitive coupling between the control and floating gates, the goal of large-scale integration is to have a small cross-section. It is necessary to provide a capacitor having a large capacitance. Particularly in the field of ADCs, the stability of the capacitance value over a range of applied voltages, as well as over a given temperature range,
This is another important condition for fast and accurate conversion.

Another consideration in the cost of manufacturing integrated circuits is that
The complexity of the manufacturing method. The complexity of the method may increase when trying to conserve surface area by increasing the number of interconnect levels. For example, the surface area of a given integrated circuit can be reduced by using two-level, rather than one-level, polysilicon gates and interconnects under the overlying metallization layer. However, the additional steps of depositing the additional polysilicon layer, depositing the additional dielectric layer, and patterning and etching this additional polysilicon layer and its contacts are required. The inclusion of the polysilicon layer increases the complexity of the method.

In addition, additional high temperature method steps performed after the formation of the diffusion junction may include additional diffusion of the diffused dopants used in forming the junction, resulting in a deeper junction, The greater directional diffusion is detrimental to the ability to scale the transistors in an integrated circuit.

Furthermore, it is desirable that the flow of the manufacturing method when manufacturing an integrated circuit such as an ADC be as compatible as possible with the flow of the manufacturing method for another integrated circuit such as a digital logic circuit. However, capacitors that require large numbers of ADCs and low voltage coefficients are not generally required in today's digital logic circuits. Incorporating a particular flow of the method to manufacture such capacitors at an early stage of the method tends to reduce the compatibility between the method of manufacturing ADCs and the method of manufacturing digital logic. There is.

Accordingly, it is an object of the present invention to provide a capacitor having a high capacitance ratio and therefore a large capacitance to surface area ratio.

It is another object of the present invention to provide a method for forming such a capacitor.

Another object of the present invention is to provide such a method that requires relatively low temperature processing.

It is another object of the present invention to provide a method for forming a capacitor.
It is to provide a method that requires only a level of polysilicon.

Another object of the present invention is to provide a capacitor having a small voltage coefficient of capacitance.

It is another object of the present invention to be able to manufacture at a later stage of the manufacturing method, thereby reducing the manufacturing steps of an integrated circuit prior to forming a capacitor for an integrated circuit that does not include such a capacitor. And a capacitor that can be standardized.

Other objects and advantages of the present invention will become apparent to those skilled in the art from the following description of the drawings.

Means and Action for Solving the Problems The present invention can be applied to an integrated circuit capacitor having a polysilicon electrode as a lower electrode and a metal layer as an upper electrode. After forming the patterned polysilicon layer, a multi-level dielectric is formed, in which the vias to the polysilicon lower electrode are etched. Thereafter, a capacitor dielectric is deposited. Preferably, the dielectric comprises an oxide / nitride layered dielectric. If desired, etch the contacts to the diffusion and the polysilicon electrode, deposit and pattern metal to form the upper electrode of the capacitor on the capacitor dielectric, and optionally, the diffusion and the polysilicon. Make contact to polysilicon.

FIG. 1 shows a simplified cross-sectional view of a metal-polysilicon capacitor 2 constructed in accordance with the present invention.
The capacitor 2 is formed on a field oxide 8 arranged on the surface of the D-type substrate 4 in this embodiment.
The lower plate of the capacitor 2 is formed of polycrystalline silicon,
In this embodiment, it is covered with a high temperature metal silicide. The silicide 14 is not essential for constructing the capacitor 2, but as will be described later, if the silicide coating is desired elsewhere on the integrated circuit containing the capacitor 2, Can be formed. This coating increases the stability of the capacitor 2. The capacitor dielectric for the capacitor 2 is comprised of a silicon dioxide layer 20 underlying the silicon nitride layer 22. In the embodiment shown in FIG. 1, the oxide 20 is 25 nm thick and the nitride 22 is 25 nm thick, but the capacitance ratio is about 1 fF / micron square. The upper electrode plate of the capacitor 2 is preferably formed by providing a titanium-tungsten alloy layer 24 below an aluminum layer or an aluminum alloy layer 30. The provision of the layer 24 makes it easier to manufacture the capacitor 2 as described later.
It is not indispensable for constituting the capacitor 2. Layer 24 and
30 may alternatively be pure aluminum, doped aluminum (such as copper-doped aluminum and silicon-doped aluminum), or a titanium-tungsten alloy layer underneath the copper-doped aluminum layer May be formed of any one of a number of standard metals used in metallizing integrated circuits, such as multilayer metal systems such as those described in US Pat.

Capacitor 2, which is configured as a metal-polysilicon capacitor as shown in FIG. 1, reduces the coefficient of capacitance with respect to voltage and the coefficient of capacitance with respect to temperature as compared to a polysilicon-polysilicon capacitor. Let
Thus, it was found to be improved. This stability is further improved when the underlying polysilicon is covered with a silicide coating. Compared to silicide polysilicon, non-silicide polysilicon has a poor voltage coefficient because, when the applied voltage increases, the polysilicon crystal grains adjacent to the capacitor dielectric become depleted, and This is to reduce the capacitance and thus increase the voltage coefficient of the capacitor. FIG. 7 is a graph showing the change in capacitance versus applied voltage for metal-to-non-silicide polysilicon capacitors and metal-to-silicide polysilicon (polycide) capacitors having equivalent dielectric coatings. The method used to form the capacitor 2 will become apparent from the description below, but the dielectric and upper plate of the capacitor 2 are formed using today's polysilicon.
It can be performed at a relatively low temperature as compared to forming a polysilicon capacitor.

2a to 2h, a method of forming the capacitor 2 of FIG. 1 will be described in detail. FIG. 2a shows a p-type substrate 4
FIG. 3 is a cross-sectional view of an integrated circuit manufactured partway through the process. The field oxide structure 8 is formed in a known manner, such as the well-known local oxidation (LOCOS) method. The polycrystalline layer is entirely deposited, patterned and etched to form polysilicon structures 10 and 12. As mentioned earlier,
Polysilicon structure 10 acts as the lower plate of capacitor 2. Although the polysilicon structure 12 is a structure unrelated to the capacitor 2, it is shown for convenience of explanation. Structures 10 and 12
The polysilicon layer used to form the gate is preferably heavily doped to make it relatively conductive, as in ordinary integrated circuits. Generally, the polysilicon layer is doped n-type and may be implanted with an n-type dopant or in-situ during its deposition. An n-type diffusion 6 is formed by ion implantation and then diffused into the surface of the p-type substrate 4 where it is not covered by the field oxide 8. Diffusion 6 is typically formed after the previously described polysilicon layer is formed and patterned, so that the source and drain regions of the MOS transistor are self-aligned with respect to the polysilicon gate electrode. To form

The diffusion 6 and the polysilicon structures 10 and 12 of FIG.
In each case, the state covered with the high-temperature metal silicide coating 14 is shown. As is well known, the subsequent silicidation prevents the polysilicon structure 10 and the polysilicon structure 10 from being shorted to the source and drain diffusions of the MOS transistor.
Preferably, sidewall oxide filaments 13 are formed on both sides of 12. The silicide coating is formed by depositing a high-temperature metal such as titanium, molybdenum or any high-temperature metal conventionally used for silicide coating, and then annealing to directly react the high-temperature metal with the underlying silicon. , Formed by forming a silicide coating 14. Such silicification by a direct reaction is well known. Thereafter, the unreacted high-temperature metal or high-temperature metal compound on the field oxide 8 is removed, leaving the structure shown in FIG. 2a. As previously mentioned, silicidation of the lower electrode polysilicon 10 is not essential, but as shown in FIGS. 1 and 2a, the polysilicon structure 10 and the diffusion 6 may be located elsewhere in the integrated circuit. Then, when silicidation is desired, this silicidation can be performed.
As described above, the silicification of the polysilicon electrode 10 increases the voltage stability of the capacitor 2.

After silicidation, a multilevel dielectric layer 16 is deposited on the surface of the integrated circuit by chemical vapor deposition or other conventional methods, as shown in FIG. 2b. Multi-level dielectric layer
16 may be any conventional dielectric material used to insulate the polysilicon layer from the overlying metallization.
One example of a common multilevel dielectric 16 is silicon dioxide doped with phosphorus (PSG) or silicon dioxide doped with boron and phosphorus (BPSG). The multi-level dielectric is doped to be a getter for such ionic contaminants in order to prevent mobile ionic contaminants such as sodium from reaching the underlying active components. Next,
As shown in FIG. 2c, at the location where the capacitor 2 is to be formed, a via 18 is formed through the multilevel dielectric 16 up to the silicide coating 14 (if present, otherwise polysilicon 10). Note that vias 18 are not formed at the same time as contact vias for polysilicon structure 12 or diffusion 6. These contacts will be formed later, as described below. Vias 18 are patterned according to conventional photolithography and are etched by a conventional wet or plasma etch for the specific material of multilevel dielectric 16.

Next, a capacitor dielectric material is deposited on the surface of the integrated circuit and brought into contact with the silicide coating 14 where the capacitor 2 is to be formed, as shown in FIG. 2d. In this embodiment, the capacitor dielectric is constructed by forming a 25 nm thick silicon nitride layer 22 on a 25 nm thick silicon dioxide layer 20. Preferably, both layers 20 and 22 are formed by low pressure chemical vapor deposition which can be performed at relatively low temperatures (eg, on the order of 800 ° C.). One example of a method of forming layers 20,22 is described in U.S. Pat. No. 4,697,330, issued Oct. 6, 1987, assigned to the assignee of the present invention.
No. After deposition of the layers 20, 22 by CVD, densification in an inert or oxygen atmosphere at a temperature on the order of 800 ° C. can be performed. Due to the low temperature at which the layers 20 and 22 are formed by LPCVD,
Additional vertical and lateral diffusion is reduced.

Note that, alternatively, one layer of dielectric material, such as a layer of silicon dioxide or an oxidized silicon nitride layer, may be used for the dielectric of capacitor 2. Pending US Patent Application No. 174,751 filed March 29, 1988
Additional layers of dielectric material, such as the oxide / nitride / oxide layered dielectric or nitride / oxide / nitride layered dielectric noted in the above paragraph, may alternatively be used as the capacitor dielectric. Good.

As an optional preferred step when forming the capacitor 2, a metal layer 24 is formed on the dielectric layers 20, 22 before etching the contacts to the polysilicon structure 12 and the diffusion 6. FIG. 2e shows the integrated circuit on which the layer 24 has been formed. A preferred metal for forming layer 24 is a titanium-tungsten alloy, which is deposited to a thickness on the order of 50 nm. As will be described in more detail below, the presence of layer 24 over the capacitor area allows for
The dielectric layers 20, 22 are protected.

Referring now to FIG. 2f, a mask material layer 27,
For example, a photoresist is shown on the surface of the metal layer 24. The mask material 27 is exposed and developed according to conventional photolithography to define contact locations 26 (for the polysilicon structure 12) and 28 (for the diffusion 6). After this,
This structure is subjected to a plasma etch (or alternatively a wet etch) to etch the metal layer 24 and the dielectric layers 22, 20 and 16, the polysilicon structure 12 at the contact location 26 and a diffusion at the contact location 28. Expose 6. Thereafter, when the mask material 27 is removed, the structure shown in FIG. 2G is obtained. Of course, in the illustrated example of the polysilicon 12 and the diffusion portion 6 covered with silicide, it is preferable to stop the contact etching at the silicide film 14.

Where the capacitor 2 is to be formed, a dielectric layer
Note that metal layer 24 remains in place above 20,22. After etching the contact vias and before depositing the metallization, it is common in normal semiconductor processing to perform a deglaze consisting of, for example, a plasma sputtering etch or immersion of the wafer in hydrofluoric acid. It is. This deglazing removes the structure to be contacted, eg, polysilicon 12 at contact location 26 and diffusion 6 at contact location 28, after contact etch and before metallization deposition. Natural oxides that may be removed. Of course, the presence of natural oxides at the contact locations 26, 28 makes the contacts resistive. Of course, this deglazing also etches any other exposed dielectric material. When the capacitor dielectric layers 20, 22 are subjected to glaze removal, of course, the layers 20, 22 themselves are also etched. However, the presence of the metal layer 24 protects the layer 22 from deglazing and keeps the dielectric of the capacitor 2 deposited.

In the embodiments described so far, the metal 24 is titanium-
In the case of using a tungsten alloy, wet deglazing with hydrofluoric acid or deglazing by plasma sputtering can be used. Further, it should be noted that the metal 24 may be formed of aluminum or a doped aluminum layer, such as aluminum doped with silicon, in which case glaze removal by plasma sputtering is preferred.

Instead of providing the metal layer 24, after the glaze removal step, the layers 20, 2
Layer 2 to make the remaining thickness of 2 as desired
2 may be deposited to a greater thickness. For this purpose, glaze removal must be performed under controlled conditions. Still alternatively, the wafer may be kept in an oxygen-free environment after the contact etch and before the metal deposition, so that no native oxide is formed at the contact locations 26,28. However, the use of the metal layer 24 eliminates these restrictions on glaze removal and material storage after contact etch, and eliminates the need for extra masking steps.

Referring to FIG. 2h, after contact etch and glaze removal, a metal layer 30 is deposited over the structure. Metal layer
30 may be any known composition suitable for forming an integrated circuit. One example of a metal layer 30 is a titanium-tungsten alloy having a thickness of about 300 nm that overlies a copper-doped aluminum layer sputtered to a thickness of about 750 nm. It should be noted that the sputtering of the metal layer 30 is generally performed at a relatively low temperature (about 350 ° C.). Of course, the thickness of the metal layer 30 fills the locations 26, 28 of the contacts to the polysilicon structure 12 and the diffusion 6, and the metal layer 24 in the recess above the polysilicon structure 10 where the capacitor 2 is. Make sure it is enough to cover. Metal layer
A pattern of a mask is defined on 30 to define the location of the metal layer of the integrated circuit, and both metal layer 30 and metal layer 24 are etched by a known metal etch. The metal layers 24 and 30 are naturally removed from the surfaces of the dielectric layers 20 and 22 where no metal connection is made. The result is the structure shown in FIG.

FIGS. 3 and 4 show a floating gate transistor using a capacitor 2 formed generally as described above. The transistors of FIGS. 3 and 4 do not form the silicide coating 14 previously described. Depending on your wish,
Of course, the transistors of FIGS.
May be used. 3 and 4, FIG. 1 and FIG.
The same reference numerals as in FIGS. 2a to 2h are used.

Referring to FIG. 3, the capacitor 2 is roughly the first
It is shown as shown. However, polysilicon 10 extends from beneath capacitor 2 to off the edge of field oxide 8 and overlaps thin gate oxide layer 9 in the moat region. As shown in the plan view of FIG.
The diffusion regions 40 and 42 are separated. Diffusion section 40 functions as a drain of the MOS transistor, and diffusion section 42 functions as a source. Polysilicon 10 is the capacitor 2 in the moat area
And extends over the field oxide 8 on the opposite side and is electrically isolated.

Accordingly, the floating gate transistors of FIGS. 3 and 4 have polysilicon 10 as the floating gate and metal layers 24 and 30.
(That is, the upper electrode plate of the capacitor 2) is used as a control gate. A capacitor 2 capacitively couples the signal applied to the metal layer 30 to the polysilicon 10 and is electrically programmable fixed memory (EPROM) and electrically erasable programmable fixed memory (EEPROM) devices. As usual,
3. Allows programming and reading of the floating gate transistors of FIGS. 3 and 4.

FIG. 5 shows another embodiment of a capacitor 2 constructed in accordance with the present invention. The capacitor 2 has a first electrode 110 made of an unreacted high-temperature metal or an unreacted high-temperature metal conductive compound formed on the field oxide 8 in the direct reaction silicidation process described above. . As described in pending U.S. patent application Ser. No. 938,653, when using titanium as the metal in a silicification reaction, where the metal titanium is not in contact with silicon, and where the metal is in contact with silicon On top of the silicide formed in place, a titanium nitride layer is formed when a silicidation reaction is performed in a nitrogen atmosphere. Instead, titanium oxide, oxidation /
A conductive compound, such as titanium nitride or a mixture of titanium nitride and titanium nitride, can be formed on the field oxide 8 by a silicidation method, depending on the conditions of the method. A conductive compound pattern is defined and etched to form a local interconnect 112 (connecting diffusion 6 to polysilicon structure 12) as described in pending U.S. Patent Application Serial No. 938,653. With the first plate 110 of the capacitor
Can be formed. Local interconnect 112 and first
After the patterning step of forming the electrode plate 112, the formation of the capacitor 2 is continued as described above for FIGS. 2b to 2h, resulting in the structure of FIG.

As previously mentioned, the first electrode 110 is capable of reacting with the high temperature metal layer used to form the silicide when the silicidation reaction is performed in an atmosphere that does not occur. It can be formed of unreacted metal. For example, when molybdenum silicide coating 14 is formed by a direct reaction using molybdenum as a high-temperature metal, local interconnect 112 and first electrode 110 are formed of molybdenum rather than the conductive compound.

FIG. 6 shows a capacitor according to another embodiment of the present invention. In this embodiment, the lower plate of capacitor 2 is formed by diffusion region 6, which is coated with a high temperature metal silicide as described above. As in the previously described embodiment, a capacitor is formed by etching the contacts in the multilevel dielectric 16, but the etch is not covered on the polysilicon layer as before, but is covered with silicide. It is performed only on the diffusion region 6. The capacitor dielectric is formed by a deposited oxide layer 20 underneath the nitride layer 22, as before, and the upper level of the capacitor 2 is formed by the two levels of metal 24, 30 as previously described. An electrode plate is formed. The lower plate is formed in the diffusion 6, but as before, after the multi-level dielectric 16 has been deposited, the formation of the capacitor is performed.

Note that in any of the embodiments described above, the capacitor is formed relatively late in the manufacturing flow, i.e., after forming the interconnect level of the transistor and the underlying polysilicon. . Therefore, the fabrication method used to form the integrated circuit including the capacitor of the present invention should be identical to that for other integrated circuits that do not include a capacitor, up to the point that the multilevel dielectric 16 is provided with an opening. Can be done. The ability to standardize the manufacturing flow in this way is an important advantage provided by the present invention, in addition to the advantages described above for capacitor performance.

Although the present invention has been described in detail with reference to preferred embodiments, this description is only an example and should not be construed as limiting the invention. In addition, from the above description, those skilled in the art will readily perceive various modifications to the details of the embodiments of the invention, as well as other embodiments of the invention. These modifications and other embodiments are within the scope of the invention as defined by the appended claims.

 The following items are further disclosed in connection with the above description.

(1) In a capacitor formed at a predetermined location on a surface of a semiconductor body, a lower electrode plate formed of a diffusion region formed on the surface and an edge of the lower electrode plate are overlapped. ,
So as not to overlap the capacitor part of the lower electrode plate,
A doped silicon dioxide coating disposed on the surface, and disposed on, in contact with, and in the capacitor portion of the lower plate and elsewhere on a multilevel dielectric; A capacitor dielectric layer, comprising a metal layer and having an upper electrode plate disposed on and in contact with the capacitor dielectric layer at a location overlapping the capacitor portion of the lower electrode plate Capacitors.

(2) In the capacitor described in (1), the upper electrode plate has a first metal layer in contact with the capacitor dielectric and a second metal layer in contact with the first metal layer. A capacitor composed of a metal layer.

(3) The capacitor according to the item (2), wherein the first metal layer is made of titanium and tungsten.

(4) The capacitor according to item (2), wherein the first metal layer is made of aluminum.

(5) The capacitor according to (1), wherein the lower electrode plate has a silicide coating disposed on the diffusion region.

(6) The capacitor according to item (1), wherein the capacitor dielectric is made of silicon dioxide.

(7) The capacitor according to item (1), wherein the capacitor dielectric is made of silicon nitride.

(8) The capacitor according to item (7), wherein the capacitor dielectric further includes silicon dioxide.

(9) The capacitor according to item (1), wherein the capacitor dielectric includes a silicon dioxide layer and a silicon nitride layer.

(10) The capacitor according to (9), wherein the silicon nitride layer is overlaid on the silicon dioxide layer.

(11) In the capacitor described in (10), the capacitor dielectric may further include a second dielectric layer overlapping the silicon nitride layer.
Having a silicon dioxide layer.

(12) The capacitor according to (9), wherein the silicon dioxide layer is overlaid on the silicon nitride layer.

(13) The capacitor according to (12), wherein the capacitor dielectric further comprises a second silicon nitride layer overlying the silicon dioxide layer.

(14) In a method of manufacturing a capacitor on a surface of a semiconductor body, a field dielectric structure is formed on the surface,
Defining a moat region not covered by the field dielectric structure, forming a lower plate of polycrystalline silicon over the field dielectric structure, and forming a multi-level dielectric layer entirely. Removing a portion of the multi-level dielectric layer over the lower plate, exposing a portion of the lower plate, and forming a capacitor dielectric over the exposed portion of the lower plate. Prior to the step of removing a portion of the multi-level dielectric layer overlying the moat region to expose a portion of the moat region and removing a portion of the multi-level dielectric layer over the moat region. Forming a first metal layer comprised of aluminum in contact with the capacitor dielectric and removing a portion of a multi-level dielectric layer over the moat region; Contact with the second metal layer Which comprises the step of forming.

(15) In the method described in (14), the step of forming the capacitor dielectric includes forming a silicon dioxide layer entirely and forming a silicon nitride layer on the silicon dioxide layer. Method.

(16) In the method described in (14), the step of forming the capacitor dielectric includes depositing a silicon dioxide layer entirely and depositing a silicon nitride layer on the silicon dioxide layer. Method.

(17) The method according to (16), wherein the step of depositing is performed by low-pressure chemical vapor deposition.

(18) In a method of manufacturing a capacitor on a surface of a semiconductor body, a field dielectric structure is formed on the surface to define a moat region not covered by the field dielectric structure. Forming a lower plate made of polycrystalline silicon, forming a multi-level dielectric layer as a whole, and removing a part of the multi-level dielectric layer above the lower plate. Exposing a portion of the lower electrode plate, forming a capacitor dielectric on the exposed portion of the lower electrode plate, forming a first metal layer in contact with the capacitor dielectric, Providing a patterned mask layer to expose a portion of the multi-level dielectric layer remote from the capacitor, removing the exposed portion of the multi-level dielectric layer, and removing the patterned mask layer; And remove the After the step of the glaze removal etch performed after removing the mask layer that defines the over down, removing a portion of the multilevel dielectric layer overlying the moat region,
Forming a second metal layer in contact with said first metal layer.

(19) The method according to (18), wherein the first metal is made of an alloy of titanium and tungsten.

(20) The method according to (19), wherein the step of performing the glaze removal etching comprises a wet etching of hydrofluoric acid.

(21) The method according to (19), wherein the step of performing the glaze removal etch comprises a plasma sputtering etch.

(22) The method according to (18), wherein the first metal is made of aluminum.

(23) The method described in (22), wherein the step of performing the glaze removal etch comprises a plasma sputtering etch.

(24) A capacitor formed at a predetermined location on the surface of the semiconductor body, comprising a field dielectric structure on the surface and a metal silicide film disposed on the field dielectric structure. A lower plate, a multi-level dielectric disposed on the surface overlying an edge of the lower plate and not present on a portion of the lower plate; A capacitor dielectric disposed on and in contact with the lower plate at a portion where the multi-level dielectric is not disposed thereon, and a capacitor dielectric disposed on and in contact with the multi-level dielectric; A capacitor having a body and an upper plate composed of a metal layer disposed on and in contact with the capacitor dielectric layer.

(25) In the capacitor according to the item (24), the upper electrode plate includes a first metal layer in contact with the capacitor dielectric, and a second metal layer in contact with the first metal layer. The configured capacitor.

(26) The capacitor according to (25), wherein the first metal layer contains titanium and tungsten.

(27) The capacitor according to the item (24), wherein the lower electrode plate is made of polycrystalline silicon covered with the metal silicide film.

(28) The capacitor according to item (24), wherein the capacitor dielectric is made of silicon dioxide.

(29) The capacitor according to the item (24), wherein the capacitor dielectric is made of silicon nitride.

(30) The capacitor according to item (29), wherein the capacitor dielectric further comprises silicon dioxide.

(31) The capacitor according to the item (24), wherein the capacitor dielectric includes a silicon dioxide layer and a silicon nitride layer.

(32) The capacitor according to item 8, wherein the silicon nitride layer overlaps the silicon dioxide layer.

(33) The capacitor according to (31), wherein the capacitor dielectric further comprises a second silicon dioxide layer overlying the silicon nitride layer.

(34) The capacitor according to (31), wherein the silicon dioxide layer is overlaid on the silicon nitride layer.

(35) The capacitor of (34), wherein the capacitor dielectric further comprises a second silicon nitride layer overlying the silicon dioxide layer.

(36) The capacitor according to the item (24), wherein the lower electrode plate is made of a conductive compound of a high-temperature metal.

(37) The capacitor according to the item (24), wherein the lower electrode plate is made of titanium nitride.

(38) In a floating gate transistor formed on a surface of a semiconductor body, a field dielectric structure on the surface, a source diffusion on the surface, a drain diffusion on the surface, and a capacitor portion are provided. A floating gate disposed over the field dielectric structure and having a gate portion extending from the field dielectric and spaced from a floating gate disposed between the source and drain regions and a capacitor portion of the floating gate. A multi-level dielectric disposed over the field dielectric structure at a location and overlying the edge of the floating gate; and a multi-level dielectric disposed over and in contact with a capacitor portion of the floating gate and remote from the floating gate. A capacitor dielectric disposed over the multi-level dielectric, and a metal disposed over and in contact with the capacitor dielectric. Floating gate transistor having a configured control gate.

(39) In the floating gate transistor described in the paragraph (38), the control gate has a first metal layer in contact with the capacitor dielectric and a second metal layer in contact with the first metal layer.
Floating gate transistor composed of a metal layer.

(40) The floating gate transistor according to the item (39), wherein the first metal layer includes titanium and tungsten.

(41) The floating gate transistor of (38), wherein the capacitor dielectric comprises silicon dioxide and silicon nitride.

(42) The floating gate transistor according to the item (38), wherein the capacitor dielectric comprises a silicon dioxide layer and a silicon nitride layer.

(43) The floating gate transistor according to the item (42), wherein the silicon nitride layer overlies the silicon dioxide layer.

(44) In a method of manufacturing a capacitor on a surface of a semiconductor body, a field dielectric structure is formed on the surface,
Defining the moat area not covered by the field dielectric structure, forming a lower plate made of polysilicon overlying the field dielectric structure, forming a multi-level dielectric layer entirely Removing a portion of the multi-level dielectric layer overlying the lower plate to expose a portion of the lower plate and forming a capacitor dielectric over the exposed portion of the lower plate; Removing a portion of the multi-level dielectric layer overlying the moat region to expose a portion of the moat region and contacting a capacitor dielectric overlying the lower plate to form a metal layer; Forming an upper electrode plate to be formed.

(45) In the method described in (44), the metal layer is also in contact with an exposed portion of the moat region, and a selected portion of the metal layer is removed to define an interconnect pattern. A method comprising the step of limiting.

(46) In the method of paragraph (44), the step of forming an upper plate comprises removing the capacitor dielectric prior to removing a portion of a multi-level dielectric layer overlying the moat region. Forming a first metal layer in contact with the first metal layer and removing a portion of the multi-level dielectric layer overlying the moat region, and then contacting the first metal layer with a second metal layer. A method comprising forming.

(47) In the method described in (46), the second metal layer is also in contact with an exposed part of the moat region, and further, a selected one of the first and second metal layers is formed. A method comprising removing portions to define an interconnect pattern.

(48) The method according to (47), wherein the first metal layer includes titanium and tungsten.

(49) In the method described in (44), the step of forming the capacitor dielectric includes forming a silicon dioxide layer entirely and forming a silicon nitride layer on the silicon dioxide layer. Method.

(50) In the method described in (44), the step of forming a capacitor dielectric includes depositing a silicon dioxide layer entirely and depositing a silicon nitride layer over the silicon dioxide layer. Method.

(51) The method according to (50), wherein the step of depositing is performed by low-pressure chemical vapor deposition.

(52) The method according to (44), further comprising, prior to the step of forming the entire multilevel dielectric, overlapping the field dielectric structure away from the lower plate. Removing a portion of the multi-level dielectric layer overlying the moat region to expose a portion of the moat region, comprising forming a polysilicon structure over the polysilicon structure. A method of removing a portion of the level dielectric layer to expose a portion of the polysilicon structure.

(53) In the method described in (52), the metal layer is in contact with the moat region and the exposed portion of the polysilicon structure, and further, a selected portion of the metal layer is removed. A method comprising the step of defining an interconnect pattern.

(54) In the method described in (52), the step of forming the upper plate includes removing the portion of the multi-level dielectric layer overlying the mode region and the polysilicon structure. Forming a first metal layer in contact with the capacitor dielectric and removing a portion of a multi-level dielectric layer overlying the mode region; and then contacting the first metal layer with a second metal layer. Forming a metal layer of

(55) In the method described in (53), the second metal layer is in contact with an exposed part of the moat region, and further, a selected one of the first and second metal layers is formed. A method comprising removing portions to define an interconnect pattern.

(56) The method according to the item (54), wherein the first metal layer contains titanium and tungsten.

(57) In a method of manufacturing a capacitor on a surface of a semiconductor body, a field dielectric structure is formed on the surface, and a lower electrode plate made of polycrystalline silicon is formed on the field dielectric structure. Forming a polysilicon electrode at a position away from the lower electrode plate, forming a multi-level dielectric layer as a whole, and removing a portion of the multi-level dielectric layer above the lower electrode plate; Exposing a portion of the lower electrode plate, forming a capacitor dielectric on the exposed portion of the lower electrode plate, and forming a portion of the multi-level dielectric layer over the polysilicon electrode. Removing the portion of the polysilicon electrode to expose a portion of the polysilicon electrode and contact the capacitor dielectric overlying the lower plate to form an upper plate composed of a metal layer.

(58) In the method described in (57), the metal layer is also in contact with an exposed portion of the polysilicon electrode, and a selected portion of the metal layer is removed to form an interconnect pattern. A method comprising the step of limiting.

(59) In the method described in (57), the step of forming an upper plate may include removing the portion of the multilevel dielectric layer overlying the polysilicon electrode prior to the step of removing the capacitor dielectric. Forming a first metal layer in contact with the body and removing a portion of the multi-level dielectric layer overlying the polysilicon electrode, and then contacting the first metal layer with a second metal layer; A method comprising forming a layer.

(60) In the method described in the paragraph (57), the second metal layer is in contact with an exposed part of the polysilicon electrode, and further, a selected one of the first and second metal layers is provided. Removing the portions to define the interconnect pattern.

(61) The method according to (60), wherein the first metal layer contains titanium and tungsten.

(62) In the method described in (57), the step of forming the capacitor dielectric includes forming a silicon dioxide layer entirely and forming a silicon nitride layer on the silicon dioxide layer. Method.

(63) In the method of (57), the step of forming a capacitor dielectric comprises depositing a silicon dioxide layer entirely and depositing a silicon nitride layer over the silicon dioxide layer. Method.

(64) The method according to (63), wherein the step of depositing is performed by low-pressure chemical vapor deposition.

(65) In a method of manufacturing a capacitor on a surface of a semiconductor body, a field dielectric structure is formed on a selected portion of the surface, and the field dielectric structure contacts the silicon surface of the semiconductor body. A high-temperature metal layer was formed thereon, and the high-temperature metal layer was reacted to form a silicide at a position in contact with the silicon surface, and the high-temperature metal layer did not react to form a silicide. A selected portion is removed to define a lower electrode plate overlapping the field dielectric structure, an inter-level dielectric layer is formed entirely, and the lower electrode plate of the inter-level dielectric layer is formed. Removing a portion above the lower electrode to expose a portion of the lower plate, forming a capacitor dielectric over the exposed portion of the lower plate, and forming a capacitor dielectric over the lower plate. The upper electrode plate made of the metal layer is formed in contact with the body. The method comprising the step of.

(66) The method according to (65), wherein the high-temperature metal layer is made of titanium.

(67) The method according to the item (65), wherein a portion of the high-temperature metal layer overlapping the field dielectric structure is made of a conductive compound of titanium.

(68) The method according to the item (67), wherein the conductive compound of titanium is tan nitride.

(69) The capacitor according to the item (24), wherein the upper electrode plate is made of aluminum.

(70) The floating gate transistor according to (61), wherein the control gate is made of aluminum.

(71) A metal-polysilicon capacitor, a floating gate transistor including the capacitor, and a method of making the same have been described. A lower plate of the capacitor is formed over the field oxide structure, on which the multilevel dielectric is deposited. The multilevel dielectric is removed from the capacitor area and an oxide / nitride dielectric is deposited by LPCVD on the exposed lower plate as well as on the multilevel dielectric. Prior to the contact etch, a first titanium / tungsten layer is preferably deposited. Form contacts to moat and unrelated polysilicon. A metallized portion is provided entirely by sputtering, leaving a metallized portion filling the contact holes and a capacitor having an upper plate of titanium / tungsten and metal, excluding the metal and titanium / tungsten.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a completed capacitor constructed in accordance with a preferred embodiment of the present invention, and FIGS.
FIG. 3 is a cross-sectional view showing various steps in forming the capacitor shown in FIG.
FIG. 4 is a sectional view of the transistor, and FIG.
FIG. 5 is a plan view of a transistor, FIG. 5 is a cross-sectional view of another embodiment of a capacitor constructed according to the present invention, FIG. 6 is a cross-sectional view of another embodiment of a capacitor constructed according to the present invention, and FIG. 4 is a graph showing the change in capacitance versus applied voltage for a polysilicon capacitor and a metal-silicide polysilicon capacitor manufactured in accordance with the present invention. Explanation of main code 4: substrate 10: polysilicon structure (lower electrode) 14: silicide coating 16: multi-level dielectric 20: silicon dioxide layer (capacitor dielectric) 22: silicon nitride layer (capacitor dielectric) 24, 30: Metal layer (upper electrode)

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 27/115 29/788 29/792 (72) Inventor Howard L. Tigeler Meadow Creek, Ale, Texas, United States 505 (56) References JP-A-62-89338 (JP, A) JP-A-61-196566 (JP, A) JP-A-63-17544 (JP, A) JP 63-73549 (JP, A)

Claims (1)

(57) [Claims] 1. A capacitor in a MOS integrated circuit, comprising: a lower capacitor electrode plate made of metal silicide on polysilicon; and an insulating layer on the metal silicide. An opening for exposing a part of the metal silicide, a capacitor dielectric on the exposed part of the metal silicide, and an outer capacitor plate made of metal and arranged on the capacitor dielectric; The above capacitor, wherein an insulating filament is disposed on a side wall of the lower capacitor electrode plate.