JP3132208B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3132208B2 JP3132208B2 JP04354401A JP35440192A JP3132208B2 JP 3132208 B2 JP3132208 B2 JP 3132208B2 JP 04354401 A JP04354401 A JP 04354401A JP 35440192 A JP35440192 A JP 35440192A JP 3132208 B2 JP3132208 B2 JP 3132208B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- interlayer insulating
- region
- wiring layer
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000010410 layer Substances 0.000 claims description 56
- 239000000463 material Substances 0.000 claims description 31
- 239000011229 interlayer Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 19
- 230000000903 blocking effect Effects 0.000 claims description 14
- 230000001681 protective effect Effects 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 229910018594 Si-Cu Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910008465 Si—Cu Inorganic materials 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】この発明は、集積回路（ＩＣ）チップをそ
なえた半導体装置に関し、特にＩＣチップにおいて層間
絶縁膜に遮断溝を設けたことによりチップ端から層間絶
縁膜を介して素子領域に水分が浸入するのを阻止するよ
うにしたものである。[0001] The present invention relates to a semiconductor device equipped with an integrated circuit (IC) chips, moisture in the element region through an interlayer insulating film from the chip end in particular to the provision of the cutoff grooves in the interlayer insulating film in the IC chip It is designed to prevent intrusion.
【０００２】[0002]
【従来の技術】従来、ＩＣチップの保護構造としては、
図５，６に示すようなシールリング構造が知られてい
る。2. Description of the Related Art Conventionally, as a protection structure for an IC chip,
A seal ring structure as shown in FIGS.
【０００３】図５，６において、半導体基板１０の表面
には、複数のチップ内部領域３０Ａ，３０Ｂが形成され
ている。各チップ内部領域は、多数の回路素子及び多層
の配線により構成されるＩＣを含むもので、その周辺部
は、外部からの水分や不純物の浸入を防ぐために図５に
示すようなシールリング構造になっている。[0005] In FIGS. 5 and 6, a plurality of chip internal regions 30 A and 30 B are formed on the surface of a semiconductor substrate 10. Each chip internal area includes an IC composed of a large number of circuit elements and multilayer wiring, and its peripheral portion has a seal ring structure as shown in FIG. 5 to prevent intrusion of moisture and impurities from the outside. Has become.
【０００４】シールリング構造にあっては、基板表面に
形成されたフィールド絶縁膜１２の端部を覆ってチップ
内部領域３０Ａを取囲むように第１の層間絶縁膜１４
と、１層目の配線材層１６と、第２の層間絶縁膜１８
と、２層目の配線材層２０と、保護絶縁膜２２とが順次
に形成される。配線材層１６及び２０は、それぞれ１層
目及び２層目の配線を形成するのと同時に形成される。
また、保護絶縁膜２２としては、プラズマＣＶＤ（ケミ
カル・ベーパー・デポジション）法で形成される窒化シ
リコン膜を用いることが多い。In the seal ring structure, the first interlayer insulating film 14 is formed so as to cover an end portion of the field insulating film 12 formed on the substrate surface and surround the chip internal region 30A.
The first wiring material layer 16 and the second interlayer insulating film 18
And a second wiring material layer 20 and a protective insulating film 22 are sequentially formed. The wiring material layers 16 and 20 are formed simultaneously with the formation of the first and second wiring layers, respectively.
Further, as the protective insulating film 22, a silicon nitride film formed by a plasma CVD (chemical vapor deposition) method is often used.
【０００５】３０Ａ，３０Ｂ等の各チップ内部領域及び
その周辺のシールリング部を含む基板部分は、図６に示
すように縦横のスクライブ領域３２Ａ，３２Ｂに沿って
ウエハ状の基板１０をダイシングすることにより独立し
たＩＣチップとなる。As shown in FIG. 6, a wafer-like substrate 10 is diced along the vertical and horizontal scribe regions 32A and 32B for the chip portions including the chip inner regions 30A and 30B and the peripheral seal ring portion. Thus, an independent IC chip is obtained.
【０００６】[0006]
【発明が解決しようとする課題】上記した従来技術によ
ると、ダイシングを行なう際に、図６に示すようにチッ
プ内部領域３０Ａに達するような切り欠きＸが生ずるこ
とがある。図７は、このような切り欠きＸによりチップ
端３０Ｅに絶縁膜１２，１４，１８の端部が露出したＩ
Ｃチップ３０を示すもので、図５と同様の部分には同様
の符号を付してある。According to the above-mentioned prior art, when dicing is performed, a notch X may reach the chip inner region 30A as shown in FIG. FIG. 7 shows a case where the ends of the insulating films 12, 14, and 18 are exposed at the chip end 30E due to the notch X.
This shows the C chip 30, and the same parts as those in FIG. 5 are denoted by the same reference numerals.
【０００７】図７において、Ｎ型半導体基板１０の表面
には、Ｐ型ウエル領域１０Ｗが形成されており、ウエル
領域１０Ｗの表面には、フィールド絶縁膜１２の素子孔
内にＴａ，Ｔｂ等のＬＤＤ（Ｌｉｇｈｔｌｙ Ｄｏｐｅ
ｄ Ｄｒａｉｎ）構造のＭＯＳ型トランジスタが形成さ
れている。トランジスタＴａ，ＴｂのようなＩＣ構成用
の回路素子が形成された領域３０ａを素子領域と称す
る。In FIG. 7, a P-type well region 10W is formed on the surface of an N-type semiconductor substrate 10, and Ta, Tb, and the like are formed in the element hole of the field insulating film 12 on the surface of the well region 10W. LDD (Lightly Dope)
(d Drain) MOS transistor is formed. The region 30a in which circuit elements for IC configuration such as the transistors Ta and Tb are formed is referred to as an element region.
【０００８】第１の層間絶縁膜１４は、Ｔａ，Ｔｂ等の
トランジスタの１３Ｇ等のゲート電極層と１６Ｓ，１６
Ｄ等の１層目の配線材層との間に配置されるもので、例
えばＢＰＳＧ（ボロン・リンケイ酸ガラス）からなって
いる。配線材層１６Ｓ及び１６Ｄは、それぞれソース及
びドレインの配線として使用される。The first interlayer insulating film 14 is formed of a gate electrode layer such as 13G of a transistor such as Ta, Tb, etc.
It is arranged between the first wiring material layer such as D and is made of, for example, BPSG (boron phosphosilicate glass). The wiring material layers 16S and 16D are used as source and drain wirings, respectively.
【０００９】第２の層間絶縁膜１８は、１６Ｓ，１６Ｄ
等の１層目の配線材層と２０Ｄ等の２層目の配線材層と
の間に配置されるもので、例えばシリコンオキサイド膜
１８ａの上にスピン・オン・ガラス（ＳＯＧ）を回転塗
布して平坦状にＳＯＧ膜１８ｂを形成すると共に、ＳＯ
Ｇ膜１８ｂの上にシリコンオキサイド膜１８ｃを形成し
た構成になっている。配線材層２０Ｄは、絶縁膜１８に
設けた接続孔１８Ｐを介して配線材層１６Ｄと接続され
るもので、ドレイン配線として使用される。The second interlayer insulating film 18 is made of 16S, 16D
Is disposed between the first wiring material layer such as 20D and the second wiring material layer such as 20D. For example, spin-on glass (SOG) is spin-coated on the silicon oxide film 18a. The SOG film 18b is formed flat by
The structure is such that a silicon oxide film 18c is formed on the G film 18b. The wiring material layer 20D is connected to the wiring material layer 16D via a connection hole 18P provided in the insulating film 18, and is used as a drain wiring.
【００１０】ところで、チップ端３０ＥにＳＯＧ膜１８
ｂが露出すると、外部から水分（Ｈ2 Ｏ）がＳＯＧ膜１
８ｂを介してチップ内部に浸入する場合がある。特に有
機系のＳＯＧを用いると、水分が浸入する確率が著しく
高くなる。浸入した水分は、ＳＯＧ膜１８ｂ内を急速に
素子領域３０ａまで拡散する。そして、ＳＯＧ膜１８ｂ
内を拡散した水分は、徐々に下方に拡散していき、フィ
ールド絶縁膜１２中に正の固定電荷を発生させる。この
結果、Ｐ型ウエル領域１０Ｗの表面で導電型がＮ型に反
転し、例えばトランジスタＴａ及びＴｂの間にリーク電
流ＩL が流れて正常なトランジスタ動作を阻害する。Incidentally, the SOG film 18 is formed on the chip end 30E.
When b is exposed, moisture (H 2 O) is externally applied to the SOG film 1.
8b may enter the chip. In particular, when an organic SOG is used, the probability of intrusion of moisture is significantly increased. The infiltrated water rapidly diffuses in the SOG film 18b to the element region 30a. Then, the SOG film 18b
The water that has diffused inside gradually diffuses downward, and generates positive fixed charges in the field insulating film 12. As a result, the conductivity type at the surface of the P-type well region 10W is inverted to N type, for example, the leakage current I L between the transistors Ta and Tb flows to inhibit the normal transistor operation.
【００１１】また、ＳＯＧ膜１８ｂ内を拡散した水分
は、例えばＡｌ又はＡｌ合金からなる配線材層１６Ｓ，
１６Ｄ，２０Ｄ等にも到達し、これらの配線材層を腐食
させることがある。このため、配線の信頼性が低下す
る。The moisture diffused in the SOG film 18b becomes the wiring material layer 16S made of, for example, Al or an Al alloy.
It may reach 16D, 20D, etc., and may corrode these wiring material layers. Therefore, the reliability of the wiring is reduced.
【００１２】上記のような不都合をなくすには、切り欠
きＸが生じてもシールリング部に達しないようにスクラ
イブ領域３２Ａ，３２Ｂの幅（通常１００［μｍ］程
度）を広くすればよい。しかし、これでは、ウエハ１枚
から取れるチップの数が減るので、得策でない。In order to eliminate the above-mentioned inconvenience, the width of the scribe regions 32A and 32B (usually about 100 [μm]) may be increased so that the notch X does not reach the seal ring even if the notch X occurs. However, this is not advantageous because the number of chips that can be obtained from one wafer is reduced.
【００１３】この発明の目的は、スクライブ領域の幅を
広げることなく切り欠きに伴う水分浸入を防止すること
ができる新規な半導体装置を提供することにある。It is an object of the present invention to provide a novel semiconductor device which can prevent the penetration of water due to the notch without increasing the width of the scribe region.
【００１４】[0014]
【課題を解決するための手段】この発明に係る半導体装
置は、一方の主面において素子領域とこの素子領域を取
囲むスクライブ領域とが定められた半導体基板と、前記
素子領域内に形成された回路素子と、前記一方の主面に
おいて前記素子領域を覆って前記スクライブ領域まで広
がるように形成された第１の層間絶縁膜であって、前記
回路素子に対応する第１の接続孔が形成されたものと、
前記第１の接続孔を介して前記回路素子に接続されるよ
うに前記第１の層間絶縁膜の上に形成された第１の配線
層と、前記スクライブ領域の内側に沿って前記素子領域
を取囲むように前記第１の層間絶縁膜の端部を覆って形
成された第１の配線材層からなる第１のシールリング
と、前記素子領域を覆い且つ前記第１の配線層及び前記
第１のシールリングに重なるように前記第１の層間絶縁
膜の上に形成されると共に、前記スクライブ領域まで広
がるように塗布絶縁膜を用いて平坦状に形成された第２
の層間絶縁膜であって、前記第１の配線層に対応する第
２の接続孔が形成されたものと、前記第２の接続孔を介
して前記第１の配線層に接続されるように前記第２の絶
縁膜の上に形成された第２の配線層と、前記スクライブ
領域の内側に沿って前記素子領域を取囲むように前記第
２の層間絶縁膜の端部を覆って形成された第２の配線材
層からなる第２のシールリングと、前記素子領域を覆い
且つ前記第２の配線層及び前記第２のシールリングに重
なるように前記第２の層間絶縁膜の上に形成された保護
絶縁膜とを備えた半導体装置であって、前記第２の層間
絶縁膜には前記第１及び第２のシールリングより内側で
前記素子領域を取囲むように遮断溝を設けると共に、こ
の遮断溝を介在層を介し又は介さずに前記保護絶縁膜で
覆ったことを特徴とするものである。 A semiconductor device according to the present invention includes a semiconductor substrate having an element region defined on one main surface and a scribe region surrounding the element region, and a semiconductor substrate formed in the element region. A circuit element, and a first interlayer insulating film formed on the one main surface so as to cover the element region and extend to the scribe region, wherein a first connection hole corresponding to the circuit element is formed. And
A first wiring layer formed on the first interlayer insulating film so as to be connected to the circuit element through the first connection hole; and a device region along the inside of the scribe region. A first seal ring made of a first wiring material layer formed so as to surround an end of the first interlayer insulating film, and a first wiring layer and the first wiring layer which cover the element region; A second insulating film formed on the first interlayer insulating film so as to overlap the first seal ring and formed flat using an applied insulating film so as to extend to the scribe region;
An interlayer insulating film having a second connection hole corresponding to the first wiring layer, and a second connection hole connected to the first wiring layer via the second connection hole. A second wiring layer formed on the second insulating film, and an end portion of the second interlayer insulating film formed so as to surround the element region along the inside of the scribe region. A second seal ring made of a second wiring material layer formed on the second interlayer insulating film so as to cover the element region and overlap the second wiring layer and the second seal ring. A semiconductor device provided with a protective insulating film, wherein a cut-off groove is provided in the second interlayer insulating film so as to surround the element region inside the first and second seal rings. The blocking groove is covered with the protective insulating film with or without an intervening layer. It is intended to.
【００１５】[0015]
【作用】この発明の半導体装置によれば、ダイシング時
に第１及び第２のシールリングを越えて素子領域の近傍
に生じた切り欠きによってＳＯＧ等の塗布絶縁膜がチッ
プ端の側壁に露出しても、塗布絶縁膜の露出部から浸入
する水分は、遮断溝で遮断され、素子領域まで到達しな
い。 According to the semiconductor device of the present invention, the notch formed near the element region beyond the first and second seal rings during dicing exposes the coating insulating film such as SOG on the side wall of the chip end. However, moisture entering from the exposed portion of the coating insulating film is blocked by the blocking groove and does not reach the element region.
No.
【００１６】[0016]
【実施例】図１，２は、この発明の一実施例に係るＩＣ
チップを示すもので、図７と同様の部分には同様の符号
を付して詳細な説明を省略する。1 and 2 show an IC according to an embodiment of the present invention.
It shows a chip, and the same parts as those in FIG.
【００１７】ＩＣチップ３０は、Ｎ型半導体基板１０、
Ｐ型ウエル領域１０Ｗ、フィールド絶縁膜１２等を含む
もので、素子領域３０ａには、ＬＤＤ構造のＭＯＳ型ト
ランジスタＴａ，Ｔｂ等の回路素子が形成されている。The IC chip 30 includes an N-type semiconductor substrate 10,
Circuit elements such as MOS transistors Ta and Tb having an LDD structure are formed in the element region 30a, including the P-type well region 10W, the field insulating film 12, and the like.
【００１８】基板上面には、ＰＳＧ及びＢＰＳＧをそれ
ぞれ１００［ｎｍ］及び６００［ｎｍ］の厚さに順次に
堆積して１０００℃でＢＰＳＧをフローすることにより
第１の層間絶縁膜１４を形成する。絶縁膜１４に所要の
接続孔を形成した後、基板上面にスパッタ法等によりＷ
Ｓｉ、Ａｌ合金（例えばＡｌ−Ｓｉ−Ｃｕ）、ＷＳｉを
順次に被着してその被着層をパターニングすることによ
り１層目の配線材層１６Ｓ，１６Ｄ，１６Ｑを形成す
る。配線材層１６Ｓ，１６Ｄは、それぞれソース，ドレ
インの配線として使用される。配線材層１６Ｑは、図６
のＸのような切り欠きの到達点より内側で素子領域３０
ａを取囲むように図２の１８Ｑのようなパターンで形成
される。On the upper surface of the substrate, a first interlayer insulating film 14 is formed by sequentially depositing PSG and BPSG to a thickness of 100 [nm] and 600 [nm] and flowing BPSG at 1000 ° C. . After forming required connection holes in the insulating film 14, W is formed on the upper surface of the substrate by sputtering or the like.
The first wiring material layers 16S, 16D, and 16Q are formed by sequentially depositing Si, an Al alloy (for example, Al—Si—Cu), and WSi and patterning the deposited layer. The wiring material layers 16S and 16D are used as source and drain wirings, respectively. The wiring material layer 16Q is formed as shown in FIG.
Element region 30 inside the notch reaching point like X in FIG.
A is formed in a pattern like 18Q in FIG.
【００１９】次に、基板上面には、第２の層間絶縁膜１
８を形成する。すなわち、プラズマＣＶＤ法によりシリ
コンオキサイド膜１８ａを５００［ｎｍ］の厚さに形成
した後、ＳＯＧ膜１８ｂを約３００［ｎｍ］の厚さに塗
布し、４００℃でキュアする。そして、プラズマＣＶＤ
法によりシリコンオキサイド膜１８ｃを４００［ｎｍ］
の厚さに形成する。Next, a second interlayer insulating film 1 is formed on the upper surface of the substrate.
8 is formed. That is, after the silicon oxide film 18a is formed to a thickness of 500 [nm] by the plasma CVD method, the SOG film 18b is applied to a thickness of about 300 [nm] and cured at 400 ° C. And plasma CVD
The silicon oxide film 18c to 400 [nm]
Formed to a thickness of
【００２０】次に、レジスト層をマスクとするドライエ
ッチング処理等により層間絶縁膜１８に接続孔１８Ｐ及
び遮断溝１８Ｑを形成する。このとき、遮断溝１８Ｑ
は、図２の１８Ｑのようなパターンで配線材層１６Ｑに
達するように形成する。遮断溝１８Ｑの幅としては、溝
に堆積する膜が溝の側壁を十分被覆するのに必要な幅が
あればよく、例えば１〜２［μｍ］以上の適当な値に設
定することができる。Next, a connection hole 18P and a blocking groove 18Q are formed in the interlayer insulating film 18 by dry etching using a resist layer as a mask. At this time, the blocking groove 18Q
Are formed so as to reach the wiring material layer 16Q in a pattern like 18Q in FIG. The width of the blocking groove 18Q may be any width as long as the film deposited on the groove sufficiently covers the side wall of the groove, and may be set to an appropriate value of, for example, 1 to 2 [μm] or more.
【００２１】次に、基板上面には、スパッタ法等により
Ａｌ合金（例えばＡｌ−Ｓｉ−Ｃｕ）を被着してその被
着層をパターニングすることにより配線材層２０Ｄ，２
０Ｑを形成する。配線材層２０Ｄは、接続孔１８Ｐを介
して配線材層１６Ｄに接続されるもので、ドレイン配線
として使用される。配線材層２０Ｑは、遮断溝１８Ｑを
介して配線材層１６Ｑと接続され、ＳＯＧ膜１８ｂを介
しての水分浸入を阻止すべく作用する。Next, an Al alloy (for example, Al—Si—Cu) is deposited on the upper surface of the substrate by sputtering or the like, and the deposited layer is patterned to form a wiring material layer 20D, 2D.
Form 0Q. The wiring material layer 20D is connected to the wiring material layer 16D via the connection hole 18P, and is used as a drain wiring. The wiring material layer 20Q is connected to the wiring material layer 16Q via the cutoff groove 18Q, and acts to prevent moisture from entering through the SOG film 18b.
【００２２】この後、基板上面には、プラズマＣＶＤ法
により窒化シリコンを堆積して保護絶縁膜２２を形成す
る。なお、チップ内部領域の周辺部は、図５に示したよ
うなシールリング構造にすることができる。この場合、
配線材層１６，２０は、それぞれ配線材層１６Ｓ，２０
Ｄと共通の工程で形成される。Thereafter, silicon nitride is deposited on the upper surface of the substrate by a plasma CVD method to form a protective insulating film 22. The peripheral portion of the chip inner area can have a seal ring structure as shown in FIG. in this case,
The wiring material layers 16 and 20 are respectively composed of the wiring material layers 16S and 20S.
D is formed in the same step as D.
【００２３】上記のような処理が終ったウエハ状の基板
を図６に示したようなスクライブ領域に沿ってダイシン
グすることによりＩＣチップ３０が得られる。The IC chip 30 is obtained by dicing the wafer-like substrate after the above processing along the scribe area as shown in FIG.
【００２４】ダイシングの際に図６のＸのような切り欠
きが生じたことによりチップ端３０Ｅに層間絶縁膜１８
の端部が露出したとしても、外部からＳＯＧ膜１８ｂを
介して浸入する水分（Ｈ2 Ｏ）は、遮断溝１８Ｑにて遮
断され、素子領域３０ａまで到達しない。遮断溝１８Ｑ
の外方においてＳＯＧ膜１８ｂの下方では浸入水分によ
り絶縁膜１２中に正電荷が発生し、ウエル領域１０Ｗの
表面の導電型を反転させるが、トランジスタ動作に支障
はない。また、配線材層１６Ｓ，１６Ｄ，２０Ｄ等への
水分浸入が阻止されるので、配線腐食が抑制される。When a notch like X in FIG. 6 is formed during dicing, the interlayer insulating film 18 is formed on the chip end 30E.
Even if the end portion is exposed, moisture (H 2 O) entering from outside via the SOG film 18b is blocked by the blocking groove 18Q and does not reach the element region 30a. Blocking groove 18Q
Outside the SOG film 18b, a positive charge is generated in the insulating film 12 by the infiltration moisture under the SOG film 18b, and the conductivity type of the surface of the well region 10W is inverted, but this does not hinder the transistor operation. In addition, since the penetration of moisture into the wiring material layers 16S, 16D, 20D and the like is prevented, wiring corrosion is suppressed.
【００２５】図３，４は、遮断溝部の変形例を示すもの
である。図３の構造は、図１の構造において配線材層２
０Ｑを省略し、遮断溝１８Ｑを保護絶縁膜２２のみで覆
ったものである。図４の構造は、図１の構造において配
線材層１６Ｑ，２０Ｑを省略し、遮断溝１８Ｑを保護絶
縁膜２２のみで覆ったもので、外部取出し用のパッド電
極を横切って設置できるので、パッド電極の近傍に設け
るのに好適である。FIGS. 3 and 4 show modifications of the blocking groove. The structure of FIG. 3 is different from the structure of FIG.
0Q is omitted, and the blocking groove 18Q is covered with only the protective insulating film 22. The structure of FIG. 4 is obtained by omitting the wiring material layers 16Q and 20Q from the structure of FIG. 1 and covering the cut-off groove 18Q with only the protective insulating film 22, and can be installed across the pad electrode for external extraction. It is suitable to be provided near the electrode.
【００２６】[0026]
【発明の効果】以上のように、この発明の半導体装置に
よれば、ＩＣチップの外周部において第１及び第２のシ
ールリングより内側で層間絶縁膜に遮断溝を設けて水分
浸入を阻止するようにしたので、ダイシング時に第１及
び第２のシールリングを越えて素子領域の近傍に切り欠
きが生じても、チップ内部で導電型反転や配線腐食が生
ずるのを防止することができ、高信頼のＩＣ装置を実現
可能となる効果が得られる。 As described above, according to the semiconductor device of the present invention, a cutoff groove is provided in the interlayer insulating film on the outer peripheral portion of the IC chip inside the first and second seal rings to prevent moisture from entering. With this configuration, even if a notch is formed near the element region beyond the first and second seal rings during dicing, it is possible to prevent conductivity type inversion and wiring corrosion inside the chip. The effect of realizing a reliable IC device is obtained.
【００２７】その上、スクライブ領域の幅を広げる必要
がないので、ウエハ１枚当りのチップ収率を減らさなく
て済む利点もある。Furthermore, since it is not necessary to increase the width of the scribe region, there is an advantage that the chip yield per wafer does not need to be reduced.
【図面の簡単な説明】[Brief description of the drawings]
【図１】 この発明の一実施例に係るＩＣチップを示す
基板断面図である。FIG. 1 is a substrate sectional view showing an IC chip according to an embodiment of the present invention.
【図２】 図１のＩＣチップの上面図である。FIG. 2 is a top view of the IC chip of FIG. 1;
【図３】 遮断溝部の変形例を示す断面図である。FIG. 3 is a cross-sectional view showing a modification of the blocking groove.
【図４】 遮断溝部の他の変形例を示す断面図である。FIG. 4 is a cross-sectional view showing another modified example of the blocking groove.
【図５】 従来のＩＣチップ保護構造を示す基板断面図
である。FIG. 5 is a substrate sectional view showing a conventional IC chip protection structure.
【図６】 基板上面の素子領域配置を示す上面図であ
る。FIG. 6 is a top view showing the arrangement of element regions on the upper surface of a substrate.
【図７】 従来のＩＣチップにおける導電型反転現象を
説明するための基板断面図である。FIG. 7 is a cross-sectional view of a substrate for explaining a conductivity type reversal phenomenon in a conventional IC chip.
１０：半導体基板、１０Ｗ：ウエル領域、１２：フィー
ルド絶縁膜、１４：第１の層間絶縁膜、１６Ｓ，１６
Ｄ，１６Ｑ：１層目の配線材層、１８：第２の層間絶縁
膜、１８ａ，１８ｃ：シリコンオキサイド膜、１８ｂ：
ＳＯＧ膜、１８Ｑ：遮断溝、２０Ｄ，２０Ｑ：２層目の
配線材層、２２：保護絶縁膜、３０：ＩＣチップ、３０
ａ：素子領域、３０Ｅ：チップ端。10: semiconductor substrate, 10W: well region, 12: field insulating film, 14: first interlayer insulating film, 16S, 16
D, 16Q: first wiring material layer, 18: second interlayer insulating film, 18a, 18c: silicon oxide film, 18b:
SOG film, 18Q: blocking groove, 20D, 20Q: second wiring material layer, 22: protective insulating film, 30: IC chip, 30
a: element region, 30E: chip end.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｈ０１Ｌ 29/78 (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/316 H01L 21/318 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 identification code FI H01L 29/78 (58) Investigated field (Int.Cl. 7 , DB name) H01L 21/316 H01L 21/318
Claims (3)
域を取囲むスクライブ領域とが定められた半導体基板
と、 前記素子領域内に形成された回路素子と、 前記一方の主面において前記素子領域を覆って前記スク
ライブ領域まで広がるように形成された第１の層間絶縁
膜であって、前記回路素子に対応する第１の接続孔が形
成されたものと、 前記第１の接続孔を介して前記回路素子に接続されるよ
うに前記第１の層間絶縁膜の上に形成された第１の配線
層と、 前記スクライブ領域の内側に沿って前記素子領域を取囲
むように前記第１の層間絶縁膜の端部を覆って形成され
た第１の配線材層からなる第１のシールリングと、 前記素子領域を覆い且つ前記第１の配線層及び前記第１
のシールリングに重なるように前記第１の層間絶縁膜の
上に形成されると共に、前記スクライブ領域まで広がる
ように塗布絶縁膜を用いて平坦状に形成された第２の層
間絶縁膜であって、前記第１の配線層に対応する第２の
接続孔が形成されたものと、 前記第２の接続孔を介して前記第１の配線層に接続され
るように前記第２の絶縁膜の上に形成された第２の配線
層と、 前記スクライブ領域の内側に沿って前記素子領域を取囲
むように前記第２の層間絶縁膜の端部を覆って形成され
た第２の配線材層からなる第２のシールリングと、 前記素子領域を覆い且つ前記第２の配線層及び前記第２
のシールリングに重なるように前記第２の層間絶縁膜の
上に形成された保護絶縁膜とを備えた半導体装置であっ
て、 前記第２の層間絶縁膜には前記第１及び第２のシールリ
ングより内側で前記素子領域を取囲むように遮断溝を設
けると共に、この遮断溝を介在層を介し又は介さずに前
記保護絶縁膜で覆ったことを特徴とする半導体装置。A semiconductor substrate having an element region defined on one main surface and a scribe region surrounding the element region; a circuit element formed in the element region; A first interlayer insulating film formed so as to cover a region and extend to the scribe region, wherein a first connection hole corresponding to the circuit element is formed; A first wiring layer formed on the first interlayer insulating film so as to be connected to the circuit element, and a first wiring layer surrounding the element region along the inside of the scribe region. A first seal ring formed of a first wiring material layer formed so as to cover an end of the interlayer insulating film; and a first wiring layer covering the element region and the first wiring layer and the first wiring layer.
A second interlayer insulating film which is formed on the first interlayer insulating film so as to overlap the seal ring and is formed flat using an applied insulating film so as to extend to the scribe region. A second connection hole corresponding to the first wiring layer is formed, and the second insulating film is connected to the first wiring layer via the second connection hole. A second wiring layer formed thereon, and a second wiring material layer formed to cover an end of the second interlayer insulating film so as to surround the element region along the inside of the scribe region. A second seal ring comprising: a second wiring layer covering the element region and the second wiring layer;
And a protective insulating film formed on the second interlayer insulating film so as to overlap with the seal ring of (1), wherein the first and second seals are provided on the second interlayer insulating film. A semiconductor device, wherein a blocking groove is provided so as to surround the element region inside a ring, and the blocking groove is covered by the protective insulating film with or without an intervening layer.
を重ねて形成されると共に該複数の絶縁膜のうち少なく
とも１つが前記塗布絶縁膜からなっている請求項１記載
の半導体装置。2. The semiconductor device according to claim 1, wherein the second interlayer insulating film is formed by stacking a plurality of insulating films, and at least one of the plurality of insulating films is formed of the coating insulating film. .
請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein said intervening layer comprises a wiring material layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04354401A JP3132208B2 (en) | 1992-12-16 | 1992-12-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04354401A JP3132208B2 (en) | 1992-12-16 | 1992-12-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06188240A JPH06188240A (en) | 1994-07-08 |
| JP3132208B2 true JP3132208B2 (en) | 2001-02-05 |
Family
ID=18437314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04354401A Expired - Fee Related JP3132208B2 (en) | 1992-12-16 | 1992-12-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3132208B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6211600B1 (en) | 1998-03-25 | 2001-04-03 | Dover Europe Gmbh | Surface acoustic wave component |
| KR100712052B1 (en) * | 2004-03-29 | 2007-05-02 | 야마하 가부시키가이샤 | Semiconductor device and manufacturing method therefor |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4434606B2 (en) | 2003-03-27 | 2010-03-17 | 株式会社東芝 | Semiconductor device and method for manufacturing semiconductor device |
| JP2004296905A (en) | 2003-03-27 | 2004-10-21 | Toshiba Corp | Semiconductor device |
-
1992
- 1992-12-16 JP JP04354401A patent/JP3132208B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6211600B1 (en) | 1998-03-25 | 2001-04-03 | Dover Europe Gmbh | Surface acoustic wave component |
| KR100712052B1 (en) * | 2004-03-29 | 2007-05-02 | 야마하 가부시키가이샤 | Semiconductor device and manufacturing method therefor |
| KR100727697B1 (en) | 2004-03-29 | 2007-06-13 | 야마하 가부시키가이샤 | Semiconductor Wafer and Manufacturing Method Thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06188240A (en) | 1994-07-08 |
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