JP3288099B2 - Nonvolatile semiconductor memory device and rewriting method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EEPROM (Electr
The present invention relates to an electrically rewritable nonvolatile semiconductor memory device such as an erasable programmable read only memory (IC) and a method for rewriting the same.

[0002]

2. Description of the Related Art (Reference 1) "Electrically Programmable Memory Device with Single Transistor and Manufacturing Method Thereof":
-127179 (Reference 2) "Design of CMOS LSI": Supervised by Takuo Sugano, 1989, P172-173 (Reference 3) "Current and Future Prospects of Flash Memory": IEICE, ICD91-134 (Reference) 4) "Flash memory using word negative voltage erase method": IEICE, ICD91-135

Many storage elements of electrically rewritable and nonvolatile semiconductor memories have been proposed since the early 1980's. Among them, a typical example is an E having a floating gate as a charge holding layer.
EPROM memory cells, which are described in Documents 1-4.

EEP using this floating gate
The ROM memory cell includes a crystalline semiconductor silicon substrate,
Source and drain diffusion layers formed by doping the substrate surface with impurities of the opposite conductivity type to the substrate impurities (for example, in the case of a P-type substrate doped with boron as an impurity,
The source and drain diffusion layers are N-type layers doped with arsenic or phosphorus), a channel region for conducting minority carriers between the source and drain diffusion layers, a thin oxide film on the channel region, It has a polycrystalline silicon floating gate provided on the oxide film, and a polycrystalline silicon control gate provided on the floating gate via a thin insulating film.

EEP using the floating gate
The operating principle of the ROM memory cell is as follows. That is,
Charges (electrons or holes) are injected into an electrically isolated floating gate surrounded by an insulating film and accumulated, thereby changing the threshold voltage of the memory cell. Use as stored information.

FIGS. 12 and 13 show a configuration example of a conventional EEPROM memory cell using a floating gate (this configuration is described in References 1 and 2).

In the configuration of this example, one N-channel enhancement type MO is used to store 1-bit information.
S transistor (transistors 20, 21, 2 in FIG. 12)
2 or 23) and one memory cell (24, 25, 26 or 27 in FIG. 12) having a floating gate. Accordingly, information of 4 bits can be stored in the range shown in FIG.

In FIG. 12, reference numerals 200 and 201 are word lines. The word line 200 is connected to the gate of the N-channel enhancement MOS transistor 18 for byte selection and the gates of the transistors 20 and 21 described above. The word line 201 is connected to the gate of the N-channel enhancement type MOS transistor 19 for byte selection and the gates of the transistors 22 and 23 described above.

In FIG. 1, reference numerals 203 and 204 denote bit lines. Bit line 203 is connected to the drains of transistors 20 and 22, and bit line 204 is connected to transistor 2
1, 23 are connected to the drains.

Reference numeral 202 denotes a sense line, which is connected to the drains of the transistors 18 and 19.

Further, the source of the transistor 18 is connected to the control gate 206 of the memory cells 24 and 25 (the control gate of polycrystalline silicon is usually formed integrally with the wiring. The same applies to the following description). Is connected to the control gate 207 of the memory cells 26 and 27.

Further, the source of the transistor 20 and the drain of the memory cell 24, the source of the transistor 21 and the drain of the memory cell 25, the source of the transistor 22 and the drain of the memory cell 26, and the source of the transistor 23 and the drain of the memory cell 27 Are each a common N
It is composed of type impurity diffusion layers 208, 209, 210, 211 and is electrically connected to each other.

Reference numeral 205 denotes a source line connected to the sources of the memory cells 24 to 27.

The threshold voltage of each of the transistors 18 to 23 is, for example, 1V.

FIG. 13 is a sectional view taken along the line AB in FIG. In the figure, 220 is a P-type silicon substrate, 205 ', 208, and 203' are N-type impurity diffusion layers, and 223 and 224 are silicon thermal oxide films (gate oxide films). Also, 22 out of the silicon thermal oxide film 224
The portion 5 is very thin compared to the other portions of the silicon thermal oxide film 224 and the silicon thermal oxide film 223 (for example, the thickness of the other portions of the silicon thermal oxide film 224 and the silicon thermal oxide film 223). Is 50 nm, the film thickness of the portion 225 is 10 nm).

Reference numeral 226 denotes a floating gate formed of, for example, polycrystalline silicon, and reference numeral 206 denotes a control gate formed of, for example, polycrystalline silicon.
Is an insulating film between the floating gate 226 and the control gate 206 (for example, a thermal oxide film of about 25 nm).

Further, reference numeral 200 denotes a gate of the transistor 20 (see FIG. 12) formed of, for example, polycrystalline silicon (integrated with the word line 200 in FIG. 12).
228 is an insulating layer, and 203 is a bit line mainly made of, for example, aluminum. Reference numeral 229 denotes a contact hole for connecting the bit line 203 to the N-type impurity diffusion layer 203 'forming the drain of the transistor 20. Note that the floating gate 226 is
The entire area is surrounded by an insulating film, and is electrically insulated from other conductive portions.

FIG. 14 shows an electrical equivalent circuit of each of the memory cells shown in FIGS. In the figure, 206 is a voltage V _g applied at the control gate, 208 the voltage V _d applied at the drain, 205 ', the voltage V _s is applied at the source, 220 a voltage V _sub is applied at the substrate . The oxide film 224 and the insulating film 227 in FIG. 13 can each be expressed electrically as capacitance, and the capacitance between the floating gate 226 and the control gate 206 is represented by C.
_ip , the capacitance between the floating gate 226 and the drain 208 is C _d , the floating gate 22
Let C _{s be} the capacitance between C.6 and source 205 ′ and C _sub be the capacitance between floating gate 226 and substrate 220. Here, assuming that the potential of the floating gate 226 is _Vf , by the law of conservation of electric charge,

C _ip (V _g −V _f ) = C _s (V _f −V _s ) + C _sub (V _f −V _sub ) + C _d (V _f −V _d ) (1) In this equation (1) , V _s = V _sub = V _d = 0, V _f = V _g · R _p, where R _p = C _ip / (C _ip + C _d + C _sub + C _s ) (2) R _p is called the “coupling ratio”. In general, an R _p = from 0.55 to 0.7.

Next, the rewriting and reading operations of the EEPROM having the above configuration will be described.

Referring to FIG. 12, when writing data to the memory cell 24, for example, the word line 200 is set to 20 V, the sense line 202 is set to 0 V, the bit line 203 is set to 20 V, and the source line 205 is opened.
0 and 21 are turned on, the control gate 206 is set to 0V,
The drain 208 of the memory cell 24 is about 18V (a value obtained by subtracting the threshold voltage of the transistor 20 from 20V (however,
Including the substrate effect. )). As a result, a voltage of about 7 V is induced in the floating gate 226 of the memory cell 24 (see FIG. 13). At this time, since the thickness of the portion 225 of the silicon thermal oxide film 224 shown in FIG. 13 is 10 nm, the floating gate 226 and the drain 208
Due to the potential difference between the 225 and the Fowler-Nordheim tunnel current (tunnel current according to the Fowler-Nordheim equation:
This is referred to as “FN tunnel current”. ) Flows. This F
The -N tunnel current generally flows when an electric field of 10 MV / cm or more is applied to an extremely thin oxide film (10 nm or less). Then, due to the FN tunnel current, holes are injected from the drain 208 into the floating gate 226, and the threshold value of the memory cell 24 decreases (for example, if the initial threshold value of the memory cell 24 is 2V, After writing, the voltage becomes -2 to -3 V). At this time, the word line 200
And the bit lines other than the bit line 203, in the figure, the voltage of the word line 201 and the bit line 204 is set to 0V.
By doing so, no high voltage is applied to the memory cells other than the memory cell 24, and therefore, writing is not performed.

When erasing the memory cell 24, for example, 20 V is applied to the word line 200 and 20 V is applied to the sense line 202.
By applying V to the bit line 203 and 0 V, the control gate 206 becomes about 18 V and the drain 208 becomes 0 V. As a result, about 11 V is induced in the floating gate 226 of the memory cell 24, the FN tunnel current flows through the portion 225, and electrons are
26, and the threshold value of the memory cell 24 increases (for example, 6 to 7 V). At this time, by setting the applied voltage of a word line other than the word line 200, for example, the word line 201 to 0 V, the control gate 207 is opened and the memory cells 26 and 27 are not erased. However, in this case,
Since 0 V is applied to all the bit lines, the control gate 2
All the memory cells connected to the same node as 06, for example, the memory cell 25 are erased.

When reading from the memory cell 24, for example, by applying 5 V to the word line 200, 3 V to the sense line 202, and 2 V to the bit line 203, the transistors 18 and 20 are turned on, and the memory cell 24 is turned on. 2
4 has a voltage of 2V and the control gate 206 has a voltage of 5V. At this time, the threshold voltage of the memory cell 24 is 6 to 7
When the voltage is as high as V, the memory cell 24 is off, and no current flows between its drain and source. on the other hand,
When the threshold voltage of the memory cell 24 is as low as -2 to -3 V, the memory cell 24 is turned on, and a current flows between its drain and source. By detecting the presence or absence (or magnitude) of the current, the stored information is read.

FIGS. 15 and 16 show examples of the configuration of another conventional EEPROM memory cell using a floating gate (this configuration is described in Documents 1, 3 and 4).

In FIG. 15, 30, 31, 32, 33
Is a memory cell, 300 and 301 are word lines, 30
2, 303 are bit lines. And the word line 300
Is connected to the control gates of the memory cells 30 and 31, and the word line 301 is connected to the control gates of the memory cells 32 and 33. The bit line 302 is connected to the memory cell 30,
The bit line 303 is connected to the drains of the memory cells 31 and 33. Also, 30
Reference numeral 4 denotes a source line, which is connected to the sources of the memory cells 30 to 33.

FIG. 16 is a sectional view taken along the line AB in FIG. In the figure, reference numeral 305 denotes a P-type silicon substrate; 302 'and 304' denote N-type impurity diffusion layers;
Is a thin (for example, 10 nm) silicon thermal oxide film (gate oxide film). Reference numeral 309 denotes a floating gate formed of, for example, polycrystalline silicon; reference numeral 300 denotes a control gate formed of, for example, polycrystalline silicon (integrated with the word line 300 in FIG. 14);
7 is a floating gate 309 and a control gate 300
(For example, 25 made of an oxide film and a nitride film).
nm insulating film). Further, 310 is an insulating layer, 302
Is a bit line mainly made of aluminum, for example. Reference numeral 308 denotes a contact hole for connecting the bit line 302 and the N-type impurity diffusion layer 302 '.

Next, the operation of rewriting and reading of the EEPROM having this configuration will be described.

Now, the threshold value in a state where no electric charge is injected into the floating gate of each memory cell is set to, for example, 2
V.

When writing to the memory cell 30 in FIG. 15, for example, the word line 300 is
1 is 0 V, bit line 302 is 5 V, bit line 303 is 0
V, the source line 304 is set to 0V. At this time, assuming that the coupling ratio of the memory cell is R _p = 0.6, about 7 V is induced in the floating gate 309 in FIG.
As a result, the drain 302 ′ and the source 3
04 ′, an electron channel layer is formed.
Drain 30 for high gate and drain voltages
Hot electrons are generated in the high electric field region near 2 ', and the hot electrons are injected into the floating gate 309 across the potential barrier between the silicon and the gate oxide film. This phenomenon is called "channel hot electron injection" (hereinafter referred to as "CHE injection"), and the CHE injection increases the threshold voltage of the memory cell 30 in FIG. Is performed. At this time, a current of 30 μA to 1 mA flows between the drain and the source of the memory cell 30 before the CHE injection occurs. In addition, the word line 301 and the bit line 30
3 is 0 V, no data is written to the memory cells 31 to 33.

When erasing the memory cell 30, for example, the word line 300 is set to -9V, and the word line 301 is set to 0.
V, the bit lines 302 and 303 are both opened, and the source line 304 is set to 5V. As a result, about −7 V is induced in the floating gate 309 of the memory cell 30, and the floating gate 30
Electrons are extracted from No. 9 to the source 304 'by the FN tunnel current. The threshold value of the memory cell 30 is reduced to 2 to 3 V by appropriately adjusting the amount of the extracted electrons by the control circuit. Also in this example, all the memory cells having a common control gate with the memory cell 30 via the word line 300, for example, the memory cell 31 are erased. The memory cells 32 and 33 are connected to the word line 3
Since 01 is 0V, it is not erased.

When reading data from the memory cell 30, for example, the word line 300 is set to 5V, the word line 301 is set to 0V, the bit line 302 is set to 1V, the bit line 303 is set to 0V.
By setting the source line 304 to 0 V, the memory cell 3
When the threshold value of 0 is high (for example, 6 to 8 V), no current flows between the drain and source of the memory cell 30, but when the threshold value is low (for example, 2 to 3 V), A current flows between the drain and the source of the cell 30.

[0032]

In the first conventional example shown in FIGS. 12 and 13, writing to a memory cell is performed by F
Since the charge is injected by using the -N tunnel current, there is an advantage that a relatively small current (for example, 10 to 1000 pA per memory cell) is required for the memory cell at the time of writing.

In the first conventional example, however, an isolation transistor for isolating memory cells from each other, such as transistors 20 to 23 in FIG. 12, is required to selectively perform writing in the cell array. Met. That is, when these isolation transistors 20 to 23 are not provided,
When writing is performed on, for example, the memory cell 24 by the method described above, writing is performed on all the memory cells connected to the bit line 203, for example, the memory cell 26 at the same time. As described above, when one isolation transistor is provided for one bit, the occupied area is, for example, 80 to 1
About 50 μm ^{2 is} required, which causes a problem that large-scale integration of the cell array is hindered.

On the other hand, the second conventional example shown in FIGS. 15 and 16 has an advantage that the isolation transistor is not required unlike the first conventional example, but the CHE injection from the vicinity of the drain at the time of writing is performed. There is a drawback that a large current is required for that part of the memory cell to use. That is, in the case of writing using the FN tunnel current, the necessary current amount is small. Therefore, even when using a power supply voltage of 3 V, for example, by providing a booster circuit such as a charge pump circuit in the integrated circuit, Operation with a single power supply voltage is possible. On the other hand, CHE from near the drain
In the case of writing by injection, a reduction in drain voltage is limited due to the need to generate hot electrons in that portion. For example, an integrated circuit having a minimum processing dimension of 0.8 μm and requiring 6 to 7 V is 0%. Even at the 0.5 μm level, it can only be reduced to 5V. For this reason, it was almost impossible to use a single power supply voltage with a reduced voltage.

Even if the drain voltage at the time of writing using CHE injection from the vicinity of the drain can be reduced to about 3 V, erroneous writing due to the drain voltage at the time of reading is more likely to occur. was there. That is, when writing is performed using CHE injection from near the drain, if the difference between the drain voltage at the time of writing and the drain voltage at the time of reading is small, erroneous writing is likely to occur due to the drain voltage at the time of reading, and the reliability of the memory is reduced. There is a problem that the property is reduced.

In short, the conventional CH from the vicinity of the drain
The writing method using the E injection has a problem that it is difficult to lower the power supply voltage as compared with the writing method using the FN tunnel current.

Accordingly, the present invention provides a method for rewriting a nonvolatile semiconductor memory device such as an EEPROM which does not require an isolation transistor and can be used with a reduced single power supply voltage. An object of the present invention is to provide a nonvolatile semiconductor memory device suitable for carrying out this method.

[0038]

In order to achieve the above-mentioned object, the present invention provides an electrically rewritable nonvolatile semiconductor memory device comprising a plurality of memory cells arranged in a matrix. Wherein each memory cell comprises a source and a drain, a channel region formed between the source and the drain, a charge holding layer provided on the channel region, and a charge holding layer provided on the charge holding layer. The memory cells are formed in a first well of a first conductivity type, and the first well is formed in a second well of a second conductivity type. The second well is formed in a semiconductor substrate of a first conductivity type, and the first well and the second well are electrically connected to the semiconductor substrate independently of each other. If something In addition, in each of the memory cells, a voltage is applied to a control gate of the memory cell so as to realize a write level and an erase level according to a change in a threshold voltage due to a difference in the amount of charge stored in the charge holding layer. And a bit line for applying a voltage to the drain of the memory cell, wherein the write level in a memory cell selected from the plurality of memory cells is provided.
A first voltage lower than a ground potential by the word line, a second voltage higher than the ground potential by the bit line, and a control gate electrically connected to a control gate of the memory cell. In the at least one first non-selected memory cell having a third voltage lower than the second voltage, which does not cause a tunnel phenomenon due to a potential difference between the bit line and the first voltage. In at least one second unselected memory cell having a drain electrically connected to a drain of the memory cell, a tunneling phenomenon occurs due to a potential difference between the word line and the second voltage. controlled by a high fourth voltage than the first voltage as not to cause
Have means to do so .

In the present invention, preferably, the charge holding layer is a floating gate.

In the present invention, more preferably, the first
Has a higher impurity concentration than the semiconductor substrate.

Preferably, in the present invention, the nonvolatile semiconductor memory device includes a source line for applying a voltage to a source of the memory cell, and sets the erase level in a memory cell selected from the plurality of memory cells. A fifth voltage by the word line and a sixth voltage lower than the fifth voltage by the source line and the bit line are used to make use of a potential difference between the fifth voltage and the sixth voltage. A negative charge is injected into a charge holding layer of the memory cell from the channel region of the memory cell by a tunnel phenomenon.
Control means.

In the present invention, preferably, the sixth power supply
Pressure is lower than ground potential.

[0043]

[0044]

According to the present invention, an EEPROM having a charge holding layer is provided.
When writing to a memory cell of a non-volatile semiconductor memory device such as the above, a negative charge is extracted from the charge holding layer by using a tunnel phenomenon. However, unlike the related art, a negative voltage is applied to the control gate of the selected memory cell. Is applied, and the presence or absence of a tunnel phenomenon, that is, writing is controlled by the level of the voltage applied to the drain (for example, 5 V and 0 V). The control gate of a non-selected memory cell having a drain electrically connected to the drain of the selected memory cell is connected to the memory in a state where the negative voltage is higher than the negative voltage and no negative charge is accumulated in the charge holding layer. By applying a voltage lower than the threshold voltage of the cell (for example, 0 V when the negative voltage is -8 V and the threshold voltage of the memory cell is 2 V), tunneling in the unselected memory cell is performed. Prevent the phenomenon.

At this time, in the nonvolatile semiconductor memory device of the present invention, each memory cell has a double well formed in a semiconductor substrate, for example, a P well formed in an N well formed in a P-type semiconductor substrate. And the potential of each well can be changed independently, so that the potential of the substrate portion of each memory cell, that is, the P well, is independent of the substrate portion of the peripheral circuit portion. Can be adjusted.

In the present invention, the "tunnel phenomenon"
Is not limited to FN tunneling according to the Fowler-Nordheim equation, but may be another tunneling phenomenon, for example, direct tunneling.

The "charge holding layer" is not limited to the floating gate, but means a layer capable of injecting and storing charges including a nitride insulating layer in a trap type EEPROM memory cell.

[0048]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a first embodiment of the present invention; FIG.

FIG. 2 is a connection diagram of an embodiment in which the present invention is applied to an EEPROM, and FIG. 1 is a sectional view taken along the line AB in FIG.

In FIG. 2, reference numerals 10, 11, 12, and 13 denote memory cells having floating gates,
01 is a word line, 102 and 103 are bit lines, and 104 is a source line. Word line 100 is connected to memory cells 10 and 1
The word line 101 is connected to the control gates of the memory cells 12 and 13. The bit line 102 is connected to the drains of the memory cells 10 and 12, and the bit line 103 is connected to the drains of the memory cells 11 and 13. Further, the source line 104 is connected to the sources of the memory cells 10 to 13.

In this embodiment, as shown in FIGS. 1 and 4, an N well 112 is formed in a P-type silicon substrate 105, and a P well 113 is formed in the N well 112. Each memory cell is connected to the P well 113
Is formed. The surface impurity concentration of the P well 113 is, for example, 1 × 10 ¹⁷ cm ⁻³ .

As shown in FIG. 4, the P well 113
It is formed in a form floating in the well 112. A high-concentration P-type impurity diffusion layer 301 and a high-concentration N-type impurity diffusion layer 302 for fixing the potentials of the P well 113 and the N well 112 are provided around the cell array, respectively.

Each memory cell, for example, the memory cell 10,
As shown in FIG. 1, N-type impurity diffusion layers 104 'and 102' constituting a source and a drain, a gate oxide film 106 having a thickness of about 10 nm formed by thermal oxidation, and formed on the gate oxide film 106 Gate 109 made of conductive polycrystalline silicon having a thickness of about 150 nm, an insulating film 107 made of an oxide film and a nitride film formed on the floating gate 109 and having a thickness of about 25 nm, Formed thickness 250
Control gate 1 made of conductive polycrystalline silicon of about nm
00. The control gate 100 is formed integrally with the word line 100 in FIG.

In this embodiment, FIGS. 1 and 4
As shown in FIG. 7, an N-type impurity diffusion layer 104 'constituting a source of a memory cell is surrounded by a P-type impurity diffusion layer 114 having an impurity concentration higher than that of a P well 113 (for example, 1 × 10 ¹⁸ cm ⁻³ ). It is in a state of being left.

In FIG. 1, reference numeral 110 denotes a channel region.
Its width is about 0.4-1 μm. Further, 111 is an insulating layer, 102 is a bit line mainly composed of aluminum, and 108 is this bit line 102 and N which is a drain.
This is a contact hole for connecting with the impurity diffusion layer 102 '.

In this embodiment, the threshold value of the memory cell when no charge is injected into the floating gate 109 is about 2 V, which is the write level.

FIG. 3 shows a plan view of the memory cell of this embodiment. In the figure, reference numeral 150 denotes an N-type impurity diffusion layer (a drain and a source and a source line of a memory cell);
Is a word line (= control gate), 152 is a floating gate, 154 is a bit line, and 153 is a contact hole. In this embodiment, the area occupied by the memory cell for one bit is about 10 μm ² .

Next, a method of manufacturing the structure of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 5A, 1 × 10 ¹² phosphorus is implanted into a P-type silicon substrate 105 by ion implantation.
After introducing at a dose of about 10 ¹³ cm ^-2 , heat treatment is performed to form an N well 112. Thereafter, a silicon oxide film 115 of about 400 ° is formed by thermal oxidation.

Next, as shown in FIG. 5B, a photoresist 117 having an opening inside the N-well 112 is formed by photolithography.
7 is used as a mask, and boron is introduced into the N well 112 at a dose of about 1 × 10 ¹³ to 10 ¹⁴ cm ⁻² .

Next, as shown in FIG. 5C, heat treatment is performed to form a P well 113 in the N well 112.

Next, as shown in FIG. 6A, a silicon oxide film 106 having a thickness of about 10 nm is formed on the surface of the P well 113 by thermal oxidation, and a conductive polycrystal having a thickness of about 150 nm is formed thereon. A silicon film is formed. Thereafter, the conductive polycrystalline silicon film is patterned by photolithography, and the conductive polycrystalline silicon film is divided into memory cells. Next, an insulating film made of an oxide film and a nitride film having a thickness of about 25 nm is formed on the entire surface, and a conductive polycrystalline silicon film having a thickness of about 250 nm is formed thereon. Then, the insulating film and the upper and lower conductive polycrystalline silicon films are patterned by photolithography and reactive ion etching to form a floating gate 10.
9. The insulating film 107 and the control gate 100 are formed in a self-aligned manner.

Next, as shown in FIG. 6B, a photoresist 118 having an opening at a portion where a source is to be formed and a part of the control gate 100 is formed by photolithography, and the photoresist 118 and the control gate 100 are masked. BF ₂ ions are introduced into the P well 113 at a dose of about 1 × 10 ¹³ to 2 × 10 ¹⁴ cm ⁻² by the ion implantation method described above.

Next, as shown in FIG. 6C, after the photoresist 118 is removed, arsenic ions are implanted in an amount of 1 × 10 ¹⁵ to 1 × 10 ¹⁵ by ion implantation over the entire surface of the element region of the P well 113.
It is introduced at a dose of about 0 ¹⁶ cm ^-2 .

Next, as shown in FIG. 6D, a heat treatment is performed at 950 ° C. for about 30 minutes in a nitrogen atmosphere to thermally diffuse the arsenic and boron introduced into the P well 113, respectively.
A drain 102 ', a source 104', and a high-concentration P-type impurity diffusion layer 114 are formed.

By the process of FIG. 6, the source 104 '
Is a P-type impurity diffusion layer 1 having a higher concentration than the P well 113.
14 can be formed.

The element isolation region shown in FIG. 4 is formed by the LOCOS method or the like before performing the step of FIG. The high-concentration P-type impurity diffusion layer 301 and the high-concentration N-type impurity diffusion layer 302 may be formed at the same time as forming the same conductivity type impurity diffusion layer in the step of FIG. May be formed in the step.

Next, a method of rewriting a memory cell according to this embodiment will be described with reference to FIGS.

FIG. 7 shows the applied voltage when writing to the memory cell 10 in the circuit of FIG.

When writing to the memory cell 10, the voltage of the word line 100 is set to V _w1 as shown in FIG.
_w1 = -8V is applied. Further, the voltage of the bit line 102 is set to V _prg1, and for example, V _prg1 = 6 V is applied. Further, the voltage of the P-well 113 serving as the substrate is set to V _sub , for example, V _sub = 0V. Further, the voltage of the source line 104 is set to V
_as and the source line 104 is left open. The voltage relationship at this time is V _prg1 > V _sub ≒ 0V> V _w1 . At this time, since a negative voltage is applied to the control gate 100,
Memory cells 10 and 11 are off, and no channel is formed. If the above voltage conditions are applied to the equation (1) and the coupling ratio R _p = 0.6, the potential difference between the floating gate 109 and the drain 102 ′ in FIG. 1 is about 10.5V. Then, due to this potential difference, F
−N tunnel current flows and the floating gate 109
Electrons are extracted from the drain to the drain 102 '. At this time,
The memory cell 10 to which data is to be written is at an erase level in advance, and the threshold is lowered by extracting electrons from the floating gate 109. By properly controlling the writing time and the like so that the threshold value does not become excessively low, the threshold value is set to 2 V of the writing level.
Can be

As shown in FIG. 7, at the time of writing to the memory cell 10, the voltage of the word line 101 is set to V _w2 ,
For example, V _w2 = 0 V (V _w2 > V _w1 ) is applied. The voltage of the bit line 103 is set to V _prg2 , for example, V _prg2 = 0V
Is applied. At this time, the potential difference between the control gate and the drain of the memory cell 11 is 8 V, which induces a voltage of about 7 V at the floating gate of the memory cell 11. No current flows, and thus the threshold value of the memory cell 11 does not change. That is, writing to the memory cell 11 is not performed. In addition, the potential difference between the control gate and the drain of the memory cell 12 becomes 6 V, so that about 5.0 V is applied between the floating gate and the drain of the memory cell 12.
Although a potential difference of 5 V occurs, an FN tunnel current does not flow at this potential difference, and the threshold value of the memory cell 12 does not change. That is, writing to the memory cell 12 is not performed.

Next, the erasing operation will be described.

FIG. 8 shows a first example of a combination of applied voltages when erasing the memory cell 10 in the circuit of FIG.

In the first example of the erasing method, the word line 10
0 voltage and V _ERS1, is applied, for example, V _{er s1} = 18V. Also, the bit lines 102 and 103 and the source line 104
_Is set to V _se , for example, V _se = 0 V (V _ers1 ≫V _se )
Is applied. At this time, the control gate 10 of the memory cell 10
0, a high voltage of 18 V is applied to the memory cell 10
Is turned on, and a channel is formed. Since the potential difference between the control gate 100 of the memory cell 10 and the channel is 18 V, the coupling ratio R _p =
Assuming 0.6, a voltage of about 11 V is induced in the floating gate 109 of the memory cell 10. Then, an FN tunnel current flows due to a potential difference between the floating gate 109 and the channel due to this voltage, and electrons are injected into the floating gate 109 from the channel region. As a result, the threshold value of the memory cell 10 is, for example, 6
８8V, and the memory cell 10 becomes the erase level. At this time, the memory cells 12 and 13 are connected to the word line 101.
Since the applied voltage is 0 V, the threshold value does not change, and therefore these memory cells 12 and 13 are not erased. However, since the same voltage as that of the memory cell 10 is applied to the memory cell 11, the memory cell 11 is erased. That is, in the first erasing method example, as in the case of the conventional EEPROM, all the memory cells on the same word line as the selected memory cell are erased.

FIG. 9 shows a second example of combinations of applied voltages when erasing the memory cell 10 of FIG.

In the second example of the erasing method, the word line 10
For example, V _ers1 = 8 V is applied to the bit lines 102, 1
03 and the source line 104, for example, V _se = −10 V (V
_ers1 >0V> _Vse ). At this time, memory cell 1
Since 8 V is applied to the 0 control gate 100, the memory cell 10 is turned on and a channel is formed. In this example, the potential _Vsub of the P well 113 as the substrate is set to the same value as _Vse . In this case,
Since the potential difference between the control gate 100 of the memory cell 10 and the channel is 18 V, an FN tunnel current flows and electrons are injected from the channel region into the floating gate 109 as in the case of the above-described first erase method. Is done.
Then, the threshold value increases, and the memory cell 10 becomes the erase level. Further, the applied voltage of the word line 101 is V
_{By setting ers2} to, for example, V _ers2 = 0 V, a potential difference of 8 V is generated between the control gate and the drain / source / substrate of each of the memory cells 12 and 13, whereby the respective floating gate and drain / Source/
Although a potential difference of about 6 V is induced between the substrate and the substrate, the FN tunnel current does not flow at this potential difference, so that the memory cells 12 and 13 are not erased. In addition, the first
In the second example of the erasing method, all the memory cells (for example, the memory cell 11) on the same word line as the selected memory cell are erased, as in the case of the example of the erasing method described above.

The memory cell rewriting method using the two erasing method examples described above uses a tunnel phenomenon for both writing and erasing, and does not require an isolation transistor. Therefore, the area of the cell array can be significantly reduced as compared with the first conventional example shown in FIGS. 12 and 13, and a large-scale integration of the cell array can be achieved. Further, since CHE injection is not used for writing, the voltage applied to the drain of the memory cell at the time of reading can be higher than that of the second conventional example shown in FIGS. Then, what was 1V can be changed to 2V or more.) As a result, the ON current of the memory cell at the time of reading can be increased, and the reading speed at the time of reading can be increased. Furthermore, since the FN tunnel current is used for both writing and erasing, it can be used with a reduced single power supply voltage.

Furthermore, in the present embodiment, erasing a memory cell is an operation of increasing the threshold voltage of the memory cell, and thus has the advantage of not causing the problem of excessive erasing during erasing. That is, in the second conventional example shown in FIGS. 15 and 16, when the entire cell array is collectively erased, excessive erasing (phenomenon in which the threshold voltage becomes too low) due to variations in characteristics that occur during the manufacture of memory cells. Was a problem. In order to prevent this, it is necessary to time-divide the erasing operation and perform the verify operation in the middle of the erasing operation. As a result, in the conventional example, the erasing time was long (for example, about 90% at 1 Mbit integration).
0 ms was required. ). On the other hand, in the above-described embodiment of the present invention, the operation can be performed within 20 ms even in the case of the batch erase.

Further, in the above-described embodiment of the present invention, FIG.
As shown in FIG. 4 and FIG.
2, the P-well 113 is formed in the P-well 113 electrically separated from the P-type silicon substrate 105, and the potentials of the P-well 113 and the N-well 112 can be independently set. Therefore, the potential of the P well 113, which is the substrate potential at the time of rewriting the memory cell, can be set relatively freely. For example, as in the above-described second erasing method, the P well 113 has a potential higher than the ground potential. By applying a low voltage, the high voltage (V _ers1 ) applied to the control gate can be relatively reduced. As a result, there is an advantage that the transistor breakdown voltage in the peripheral circuit for controlling the high voltage (V _ers1 ) can be designed to be low. In particular, since the width of the element isolation section (field section) to which the high voltage (V _ers1 ) is applied can be reduced, a more highly integrated EEPROM can be realized.

FIG. 10 shows a third example of a combination of applied voltages when erasing the memory cell 10 of FIG.

In the third example of the erasing method, the word line 10
For example, V _ers1 = 12 V is applied to 0, the voltage of the source line 104 is set to V _se1 , for example, V _se1 = 5 V is applied, and the voltage of the bit line 102 is set to V _se2 , for example, V _se2 = 0.
V is applied. That is, V _ers1 > V _se1 > V _se2 ≧ 0V. At this time, 12V is applied to the control gate of the memory cell 10,
Since 5 V is applied to the source and 0 V is applied to the drain, hot electrons are generated in the vicinity of the source, and CHE injection by the hot electrons occurs.
Becomes higher. On the other hand, when, for example, V _ers2 = 0V (V _ers1 > V _ers2 ) is applied to the word line 101, in the memory cell 12, the control gate becomes 0 V, the drain becomes 0 V, and the source becomes 5 V, and the memory cell 12 remains off. Thus, the threshold does not change. At this time, the voltage of the bit line 103 is set to V _se3 , for example, V _se3 = 5.
When V (V _se3 ≒ V _se1 > V _se2 ) is applied, the control gate of the memory cell 11 is 12 V, the drain is 5 V, the source is 5 V, and the control gate voltage is 12 V, so that the memory cell 11 is turned on. A channel is formed, but since there is no potential difference between the drain and the source, no channel current flows, and thus no CHE injection occurs. Also,
Because the potential difference is small, no FN tunnel current is generated,
Therefore, the threshold value of the memory cell 11 does not change.
Further, 0 V is applied to the control gate, 5 V is applied to the drain, and 5 V is applied to the source of the memory cell 13. Since the control gate voltage is 0 V, the memory cell 13 is in the off state, and the potential difference Therefore, the threshold value of the memory cell 13 does not change.

In the third erasing method, the FN tunnel current at the drain is used for writing, and the CHE injection from the source is used for erasing, so that the second conventional example shown in FIGS. It has the following advantages.

One is that, in the conventional example, selective erasing could be performed only in byte units (or word units or sector units) at the time of erasing, whereas in the third erasing method example, as described above, Can be erased.
Moreover, in the conventional example, in order to perform erasing in byte units (or word units or sector units), it is necessary to prepare a transistor for byte (or word or sector) selection separately from the cell array, or , It is necessary to separate the source line into byte units (or word units or sector units). In this third erasing method, however, erasing in bit units is not required. It can be performed. Therefore,
Unnecessary memory cells are not erased, and the area occupied by the device can be reduced.

When a memory cell is read, a constant voltage is applied to the drain of the selected memory cell and the source is grounded, as in the second conventional example shown in FIGS. However, in the third erasing method example, since CHE injection is performed from the source direction, the risk of erroneous erasure (erroneous writing in the conventional example) due to the drain voltage is reduced. There is an advantage that it can be set higher than in the conventional example and the reading speed can be increased. In addition, since the drain voltage at the time of reading and the source voltage at the time of erasing are independent of each other, there is an advantage that it is easy to lower the voltage at the time of CHE injection.

Further, as shown in FIGS. 1 and 4, the memory cell of this embodiment has an N-type impurity diffusion layer 1 constituting a source.
04 'is surrounded by a P-type impurity diffusion layer 114 having an impurity concentration higher than that of the P well 113.
For this reason, the generation efficiency of hot electrons near the source is significantly improved as compared with the case where the P-type impurity diffusion layer 114 is not provided. FIG. 11 shows a P-type impurity diffusion layer 11.
4 (curve 41) and the P-type impurity diffusion layer 114
And the case where no is provided (curve 42) shows the erasing characteristics when erasing is performed according to the third example of erasing method. As can be seen from this graph, the provision of the P-type impurity diffusion layer 114 improves the erasing speed by almost one digit.

As the erasing method of the memory cell according to the present invention, a method combining the above-described first erasing method example and the third erasing method example or a combination of the second erasing method example and the third erasing method example is used. You can also. For example, in the latter case, the third erasing method is used when it is necessary to perform erasing in bit units, and the second erasing method is used when erasing in sector units or larger units (blocks or all memory cells in the EEPROM). An example method is used. That is, in an application in which a plurality of bytes (several hundred bytes to several megabytes) are to be erased simultaneously, the third example of the erasing method requires a certain amount of time (for example, approximately 1.3 bytes for 128 kbytes) to save power consumption required for erasing. Second), but by using the second example of the erasing method together, it can be performed in about 20 ms.

Although the embodiments of the present invention have been described above, the above-described embodiments do not limit the present invention. For example, in the rewriting method in the above-described embodiment, specific voltage values are shown, but these voltage values are different depending on the structure of the memory cell, particularly, the capacitance value and the coupling ratio value of the oxide film and the interlayer insulating film. Accordingly, it should be appropriately changed within a range that satisfies the relationship described in the claims.

When the third erasing method is not used, the P-type impurity diffusion layer 114 shown in FIGS. 1 and 4 may not be provided.

[0089]

According to the present invention, for example, a memory cell such as an EEPROM is formed in a first well of the same conductivity type as a semiconductor substrate formed in a form floating in a second well of the opposite conductivity type to the semiconductor substrate.
And the electrical connection to the first and second wells is made independently of each other. Therefore, the substrate potential when rewriting the memory cell, that is, the potential of the first well is compared. Can be set arbitrarily.

Further, according to the rewriting method of the present invention, rewriting and reading can be performed with a single power supply voltage, and low power supply voltage can be easily reduced. Further, since no isolation transistor or the like is required, the cell area can be reduced, and the degree of integration can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic longitudinal sectional view of an EEPROM memory cell according to an embodiment of the present invention, and is a schematic longitudinal sectional view of a portion along a line AB in FIG.

FIG. 2 is a circuit diagram showing an electrical connection of the memory cell of FIG. 1;

FIG. 3 is a schematic plan view of an EEPROM memory cell corresponding to the portion of FIG. 2;

FIG. 4 is a schematic vertical sectional view showing a configuration of a peripheral portion of a cell array of an EEPROM according to an embodiment of the present invention.

FIG. 5 is a schematic vertical sectional view showing a method for manufacturing an EEPROM memory cell according to one embodiment of the present invention.

FIG. 6 is a schematic longitudinal sectional view showing a method for manufacturing an EEPROM memory cell according to one embodiment of the present invention.

FIG. 7 is a diagram showing applied voltages when writing is performed on the memory cell of FIG. 2;

8 is a diagram showing applied voltages according to a first example of an erasing method of the memory cell of FIG. 2;

FIG. 9 is a diagram illustrating applied voltages according to a second example of the erasing method of the memory cell in FIG. 2;

FIG. 10 is a diagram illustrating applied voltages according to a third example of the erasing method of the memory cell in FIG. 2;

FIG. 11 is a graph showing erasing characteristics in a third erasing method example depending on the presence or absence of a high-concentration P-type impurity diffusion layer surrounding the source of the memory cell of FIG. 1;

FIG. 12 is a circuit diagram showing an electrical connection of a conventional EEPROM memory cell.

FIG. 13 is a vertical cross-sectional view taken along a line AB in FIG. 12;

FIG. 14 is an equivalent circuit diagram of the memory cell of FIG. 13;

FIG. 15 is a circuit diagram showing an electrical connection of another conventional EEPROM memory cell.

FIG. 16 is a longitudinal sectional view taken along a line AB in FIG. 15;

[Explanation of symbols]

 10, 11, 12, 13 Memory cell 100, 101 Word line (control gate) 102, 103 Bit line 102 'Drain 104 Source line 104' Source 105 P-type silicon substrate 106 Gate oxide film 107 Insulating film 109 Floating gate 110 Channel region 112 N well 113 P well 114 High concentration P type impurity diffusion layer 150 N type diffusion layer 151 Control gate 152 Floating gate 154 Bit line

Continuation of the front page (56) References JP-A-4-229655 (JP, A) JP-A-60-200574 (JP, A) JP-A-4-256361 (JP, A) JP-A-1-320700 (JP, A) JP-A-60-72275 (JP, A) JP-A-5-183171 (JP, A) JP-A-6-244386 (JP, A) JP-A-6-151785 (JP, A) 5-343700 (JP, A) JP-A-4-211178 (JP, A) JP-A-3-99474 (JP, A) JP-A-2-143464 (JP, A) JP-A-1-130570 (JP, A) A) JP-A-61-264764 (JP, A) IEEE JOURNAL OF S OLID-STATE CIRCUIT S, Vol. 27, No. 11, p. 1547-1554 Nikkei Microdevices January 1993, December 24, 1992, No. 91, p. 59-68 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (8)

(57) [Claims] An electrically rewritable non-volatile semiconductor memory device including a plurality of memory cells arranged in a matrix, wherein each memory cell includes a source and a drain, and the source and the drain. A nonvolatile semiconductor memory device having a channel region formed between the drains, a charge holding layer provided on the channel region, and a control gate provided on the charge holding layer; A memory cell is formed in a first well of a first conductivity type, the first well is formed in a second well of a second conductivity type, and the second well is a semiconductor substrate of the first conductivity type. And the electrical connection between the first well and the second well is made independently to the semiconductor substrate, and in each of the memory cells, the electrical charge is stored in the charge holding layer. A word line for applying a voltage to a control gate of the memory cell, and a bit for applying a voltage to a drain of the memory cell, in order to realize a write level and an erase level according to a change in a threshold voltage due to a difference in the amount of charge applied A write voltage in a memory cell selected from the plurality of memory cells, a first voltage lower than a ground potential by the word line, and a first voltage lower than a ground potential by the bit line. A high second voltage; and at least one first unselected memory cell having a control gate electrically connected to a control gate of the memory cell, wherein the first voltage is applied by the bit line. A third voltage lower than the second voltage that does not cause a tunnel phenomenon due to a potential difference between the third voltage and an electrical contact with a drain of the memory cell; In the at least one second unselected memory cell having a drain connected to the memory cell, the word line is higher than the first voltage such that a potential difference between the memory cell and the second voltage does not cause a tunnel phenomenon. Control by the fourth voltage
The nonvolatile semiconductor memory device characterized by having means. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said impurity diffusion layer of the second conductivity type is surrounded by said high-concentration impurity diffusion layer. 3. The nonvolatile semiconductor memory device according to claim 1, wherein an impurity concentration of said first well is higher than an impurity concentration of said semiconductor substrate. 4. A source line for applying a voltage to a source of the memory cell, wherein the erase level in a memory cell selected from the plurality of memory cells is set to a fifth voltage by the word line; And a sixth voltage lower than the fifth voltage by the line and the bit line, the potential difference between the fifth voltage and the sixth voltage is used to cause tunneling from the channel region of the memory cell. 4. The nonvolatile semiconductor memory device according to claim 1, further comprising: means for injecting a negative charge into the charge holding layer of the memory cell to control the charge. 5. The nonvolatile semiconductor memory device according to claim 4, wherein said sixth voltage is lower than a ground potential . 6. An electrically rewritable non-volatile semiconductor memory device having a plurality of memory cells arranged in a matrix, wherein each memory cell includes a source and a drain, and the source and the drain. In a rewriting method for a nonvolatile semiconductor memory device having a channel region formed between drains, a charge holding layer provided on the channel region, and a control gate provided on the charge holding layer, In the nonvolatile semiconductor memory device, each of the memory cells is formed in a first well of a first conductivity type, and the first well is formed in a second well of a second conductivity type. 2
Are formed in a semiconductor substrate of a first conductivity type, and electrical connection between the first well and the second well is performed independently of the semiconductor substrate. A memory having a write level and an erase level corresponding to a change in a threshold voltage due to a difference in the amount of charge stored in the charge holding layer; and performing a write operation on a selected one of the plurality of memory cells. The control gate of the cell has a first voltage lower than the ground potential.
And a second voltage higher than the ground potential is applied to the drain of the memory cell.
A negative charge is extracted from the charge holding layer of the memory cell by a tunnel phenomenon due to a potential difference between the second voltage and the second voltage, the memory cell is set to the write level, and is electrically connected to a control gate of the selected memory cell. The drain of at least one first unselected memory cell having a control gate is provided with a third voltage lower than the second voltage so as not to cause a tunnel phenomenon due to a potential difference between the first voltage and the first voltage. And a control gate of at least one second non-selected memory cell having a drain electrically connected to the drain of the selected memory cell is connected to the second voltage. And applying a fourth voltage higher than the first voltage to such an extent that a tunneling phenomenon is not caused by a potential difference therebetween. Rewriting storage device. 7. When erasing a selected memory cell among the plurality of memory cells, applying a fifth voltage to a control gate of the memory cell and applying the fifth voltage to a source and a drain of the memory cell. 6th lower than the voltage of
And applying a potential difference between the fifth and sixth voltages to inject a negative charge from the channel region into the charge holding layer of the memory cell by a tunnel phenomenon to bring the memory cell to the erase level. 7. The rewriting method for a nonvolatile semiconductor memory device according to claim 6, wherein: 8. The method according to claim 7, wherein the sixth voltage is lower than a ground potential.