JP3215258B2 - PLL integrated circuit and adjustment method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type PLL integrated circuit using a MOS capacitor as a capacitance of a loop filter, and an adjusting method. PLL applications are very extensive. CPU clock synchronization, P
CM communications, FM demodulators, frequency synthesizers and the like are typical examples. In recent years, especially with the development of integrated circuits, PLL
Circuits have become economical and easy to implement with integrated circuits, and have become widely used in various consumer devices such as stereos, televisions, and transceivers.
In such various applications, a PLL integrated circuit with higher stability, higher accuracy, and higher reliability has been required.

In particular, regarding clock synchronization of a CPU, C
As the PU chip area increases and the clock frequency increases, clock skew generated between chips or within a chip becomes a problem. As a method of reducing the clock skew, a clock adjustment method using a PLL is currently receiving particular attention as a very effective method.

[0003]

2. Description of the Related Art First, a PLL will be briefly described.
The PLL is a circuit that synchronizes the frequency and phase of two signals. FIG. 10 shows a general configuration diagram of a PLL. In the figure, 1 is a phase comparator, 2 is a charge pump, 3 is a loop filter, and 4 is a voltage controlled oscillator.

[0006] The PLL is an external input signal (reference signal).
The phase: θi) and the phase of the output signal (phase: θo) of the internal voltage controlled oscillator 4 (VCO) are synchronized. The phase comparator 1 compares the phases of two input signals, and calculates a phase difference θe = θ.
A pulse with a width proportional to i-θo is output. charge·
The pump 2 converts a pulse voltage output of the phase comparator 1 into a current.

[0005] The loop filter 3 removes unnecessary harmonic components and noise, and determines the response characteristics and the synchronization characteristics of the PLL based on the amplitude and phase characteristics. In the case of the loop filter as shown in FIG. 13, the input voltage Vc of the VCO can be expressed by Vc = (Ip ÷ C) × t. Here, Ip is the pump current of the charge pump, C is the capacitance value of the loop filter, and t is the time.

The voltage controlled oscillator 4 includes a loop filter 3
Is an oscillator whose oscillation frequency is determined by the output voltage. As shown in FIG. 11, the voltage-oscillation frequency characteristic usually shows a proportional relationship. The above-described phase comparator 1, charge pump 2, loop filter 3, voltage-controlled oscillator 4
However, as shown in FIG. 10, a single loop PLL loop is formed. This loop is a feedback loop for the phase.

Consider a process in which two signals are synchronized. FIG.
Reference numeral 2 denotes a time change of the input control voltage Vc of the VCO. At first, since the oscillation frequency of the VCO is low and the difference from the reference frequency is large, the output of the phase comparator 1 is also large, and the input voltage of the VCO rises rapidly.

Thereafter, the frequency difference gradually decreases, and when the frequency and the phase of the two input signals of the phase comparator 1 are synchronized, the input voltage of the voltage controlled oscillator 4 becomes constant. In FIG. 12, TL indicates a lock time (time until the phases are synchronized), and VCL indicates an input voltage of the voltage controlled oscillator 4 when the PLL is locked.

The lock time, the lock range, the noise band, and the like are important factors representing the performance of the PLL. These are the pump current I _p of the charge pump, the resistance R of the loop filter, the capacitance C of the loop filter, VC
It is determined by the gain of O (the slope of the voltage-frequency characteristic) and the like.

When controlling the lock time of the PLL,
For example, when it is desired to shorten the lock time, the smaller the capacitance value of the loop filter is, the better. However, in a region where phases are synchronized, a certain value of the capacitance is required to improve the loop characteristics. Therefore, if the capacitance value is small at first and becomes a constant capacitance value in which the loop characteristics are good in the region where the phases are synchronized, the lock time is short,
In addition, the loop characteristics are improved.

Although it is difficult to improve the lock time and the PLL characteristics at the same time at the same time in synchronization with a normal design, several methods have been devised. For example,
PLL with two resistors in the loop filter
Is to select a smaller resistance value before synchronization, and to select a larger resistance value after synchronization (Japanese Patent Laid-Open No. Hei 4-1).
FIG. 1 of Japanese Patent Application Laid-Open No. 57923/1993, in which the capacity in a loop filter can be selected (Japanese Patent Laid-Open No. 4-10033 / 1991)
No. 1 (FIG. 2), two loop filters are prepared and switched before and after synchronization (JP-A-63-970).
No. 16, Japanese Patent Application Laid-Open No. 56-110344, FIG.
Nos. 2 and 3).

[0012]

In the prior art in which the PLL circuit is not devised in any way, the characteristics of the loop filter are constant without change. There is a disadvantage that the characteristics cannot be improved after PLL synchronization.

Further, in the conventional techniques for changing the characteristics of the loop filter before and after the PLL is synchronized, an extra circuit is required in each case. Therefore, there is a disadvantage that the circuit area becomes large. Further, in the case of the conventional technology in which the loop filter is switched before and after PLL synchronization,
At the time of switching, the input voltage of the voltage controlled oscillator is disturbed and PL
There is also a drawback that the characteristics of L deteriorate.

The present invention is based on the above considerations, and is a MOS type PLL capable of shortening a lock time and improving loop stability after synchronization without adding an extra circuit. It is intended to provide an integrated circuit.

[0015]

FIG. 1 shows the structure of a MOS capacitor when an N-type MOS capacitor is formed on a P-type substrate. In the figure, 7 is a P-type silicon substrate, 8 is a gate oxide film, 9 is a metal gate electrode, 10 is a high concentration N-type impurity region, and 11 is a channel layer region.

FIG. 2 shows the relationship between the gate voltage Vg and the capacitance of the MOS capacitor shown in FIG. While the gate voltage is low, the depletion layer capacitance and the gate oxide film capacitance are connected in series.
The capacity shows a small value. When the gate voltage increases and the gate voltage exceeds the threshold value Vth of the MOS capacitor, an inversion layer is formed, and the capacitance approaches the oxide film capacitance.
After that, it takes a constant value (the area (a) in FIG. 2).

Normally, in a frequency range in which the PLL can synchronize, the loop characteristics of the PLL do not change so that
The capacitance of the loop filter, a range of FIG. 2 which is a constant in the range of the input control voltage V _C of the VCO to achieve the frequency range of interest of (a) is used. That is, PL
The input control voltage VCL (see FIG. 12) of the VCO locked by L must be in the area (a) in FIG.

As described above, in order to shorten the time required for the PLL to lock from the initial state, the smaller the capacitance value of the loop filter, the better, but in order to improve the loop characteristics in the locked state, Requires a certain capacitance value. As can be seen from FIGS. 12 and 2, if the threshold value Vth is made slightly smaller or equal to the voltage VCL when the PLL is locked, the above requirement can be satisfied.

FIG. 3 shows two MOS transistors having different threshold values Vth.
FIG. 4 is a diagram illustrating voltage-capacity characteristics of a capacitor. VCL is P
LL is the voltage at the time of locking. In this case, (b) has a shorter lock time than (a). When the MOS capacitor is created with the same process parameters (type of gate metal electrode, thickness of gate oxide film, impurity concentration of channel layer, etc.) as other circuit elements on the MOS type PLL integrated circuit, FIG. The characteristic shown in (a) is obtained. FIG. 3B shows the characteristics of the MOS capacitor according to the present invention.

FIG. 4 shows the time change of V _C in each case. FIG. 4A corresponds to the characteristic of FIG.
(b) corresponds to the characteristic of (b) of FIG. The lock time TLa in FIG. 4A is longer than the lock time TLb in FIG.

[0021]

According to the present invention, the lock time and the loop characteristic can be simultaneously and optimally controlled without adding an extra circuit, and the lock time is short and the loop characteristic at the time of locking is good. A PLL integrated circuit can be obtained.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The threshold voltage of a MOS capacitor as shown in FIG. 1 is given by the following equation (see Reference 1). _{Vth = 2ψ F + φ MS +} (2ε S / N A) 1/2 / C OX + Q int / C OX ... (1) where, [psi _F is the Fermi level of the substrate, phi _MS is the gate electrode and the silicon substrate The work function difference, ε _S is the dielectric constant of silicon, N _A is the substrate concentration, C _OX is the capacity of the gate oxide film per unit area, and Q _int is the fixed charge at the MOS interface. Therefore, the threshold value of the MOS capacitor is changed by the following means.

[0023]Change the metal electrode type of the MOS capacitor
Change the work function difference φ _MS . The work function difference due to the difference of the gate metal electrode is shown below.
(Ref. 2). However, Mg is used as a reference. Mg0Al0.8Ni1.2Cu1.4Au1.7Ag1.8

Thus, Mg → Al → Ni → Cu →
The work function difference increases in the order of Au → Ag, and the voltage-capacity characteristic shifts from the characteristic of FIG. 3A to the characteristic of FIG. For example, when comparing Al and Cu, Cu
Has a threshold value 0.6 V larger than that of Al. In the range where the capacity is guaranteed to be a fixed area when locked,
The lock time decreases as the work function difference increases.

The thickness of the oxide film of the MOS capacitor is changed.
Let From equation (1), it can be seen that the threshold value also changes depending on the oxide film capacitance value. In order to change the capacitance of the oxide film, the thickness of the oxide film may be changed. Since there is an inverse relationship between the capacitance value and the film thickness, the threshold value can be increased by increasing the film thickness.

The impurity concentration of the channel layer is changed. Equation (1) shows that the threshold value changes by changing the substrate concentration N _A. The substrate concentration N _A that actually determines the threshold value is the impurity concentration in the channel layer. for that reason,
The impurity concentration may be changed by ion implantation. To increase the threshold, N _A may be reduced. FIG. 5 shows an example of the dependency of the threshold value of the MOS capacitor on the gate oxide film and the substrate concentration (Reference Document 3).

A substrate bias is applied. In the case of NMOS, the threshold value changes as follows with respect to the substrate bias (Reference Document 4). _{Vth (V BS) = Vth (} 0) + K N ^{_{[(2ψ F + V BS) 1/2}} - (2ψ F) 1/2 ] (2) where, Vth (0) is the time of V _BS = 0 Threshold
It is given by equation (1). K _N is the substrate bias effect coefficient.

Normally, in the case of NMOS, a negative substrate bias is applied. FIG. 6 shows an example of a change in threshold value due to a substrate bias (Reference Document 5). The threshold value increases as the substrate bias increases. By increasing the substrate bias, the capacitance-voltage characteristics of FIG.
The lock time can be shortened by changing to the capacitance-voltage characteristic of (b).

It is also possible to make only the substrate bias of the MOS capacitor part variable. For this purpose, the MOS capacitor portion may be formed in a double well structure. A board for generating a PLL loop filter;
The substrate that generates the other circuit portions of L may be separated.

With the double gate structure, the threshold voltage
To change. FIG. 7 shows a MOS capacitor having a double gate structure.
In the figure, 7 is a P-type silicon substrate, 8 is a gate oxide film, 9-0 is a floating gate, 9-1 and 9-2.
Denotes a gate, and 10 denotes a high-concentration N-type impurity region.

In the structure as shown in FIG. 7, the substantial voltage applied to the channel layer is as follows. V _eff = (C ₁ V ₁ + C ₂ V ₂ ) / C _T (3) Therefore, the apparent threshold voltage is changed by adjusting the voltage applied to the gates 9-1 and 9-2. I can do it.

FIGS. 8 and 9 show simulation results of the conventional PLL and simulation results of the PLL integrated circuit of the present invention. This is because the MOS capacitor (N on the P-type substrate)
MOS) to change the threshold voltage Vth
Are the results when the value is changed. The horizontal axis represents time, and the vertical axis represents the control voltage of the VCO.

FIG. 8 shows the case of the prior art, in which the substrate bias is 0 V, the threshold Vth at this time is 0.94 V, the lock voltage VCL is 2.15 V, and the lock time is 3.5 microseconds. The ratio of the threshold value Vth to the lock voltage VCL is 0.94 ÷ 2.15 ≒ 0.44. In the prior art, the MOS capacitor portion of the PLL integrated circuit is
It was created with the same process parameters as the other circuit parts of the PLL integrated circuit.

FIG. 9 shows the case where the present invention is applied, wherein the substrate bias is -3.0 V, the threshold at this time is 1.65 V, the lock voltage VCL is 2.15 V, and the lock time is 2.1 microseconds. It is. The ratio of the threshold value Vth to the lock voltage VCL is 1.65 ÷ 2.15 ≒ 0.77. By using the present invention, the lock time can be shortened by 40%.

The names of the references 1, 2, 3, 4, and 5 are shown below. 1. Design of CMOS VLSI Tetsuya Iizuka P80 2. P by Physics of Semiconductor Devices SMSze
396 3. Design of CMOS VLSI Tetsuya Iizuka P80 4. Design of CMOS LSI LSI Tetsuya Iizuka P13 5. CMOS LSI Design Tetsuya Iizuka P13

[0036]

As is apparent from the above description, according to the present invention, it is possible to simultaneously control and optimize the lock time and the loop characteristics without adding an extra circuit unlike the prior art. Therefore, a degree of freedom is provided by the design of the PLL, and a higher-performance PLL integrated circuit can be realized with a more flexible design, the lock time can be increased, and the loop characteristics at the time of locking can be improved. It is possible to do. In the above description, the present invention is applied to the case where the P-type Si
Although the case where a substrate is used has been described as an example, the present invention is naturally applicable to the case of an N-type Si substrate.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a MOS capacitor (in the case of a P-type substrate).

FIG. 2 is a diagram showing a gate voltage-capacity characteristic of a MOS capacitor.

FIG. 3 is a diagram showing capacitance-voltage characteristics of MOS capacitors having different threshold voltages.

4 is a diagram showing the time variation of V _C.

FIG. 5 is a diagram showing dependence of a threshold value of a MOS capacitor on a gate oxide film thickness and a substrate concentration.

FIG. 6 is a diagram showing the substrate bias dependence of the threshold voltage.

FIG. 7 is a diagram showing a MOS capacitor having a double gate structure.

FIG. 8 is a diagram showing a simulation result of a conventional PLL integrated circuit.

FIG. 9 is a diagram showing a simulation result of the PLL integrated circuit of the present invention.

FIG. 10 is a diagram showing a configuration of a PLL.

FIG. 11 is a diagram showing a control voltage V _C -frequency characteristic of a VCO.

FIG. 12 is a diagram showing a time change of an input control voltage V _C of a VCO.

FIG. 13 is a diagram illustrating a configuration example of a loop filter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Charge pump 3 Loop filter 4 Voltage controlled oscillator 5 Resistance 6 Capacitance 7 P-type silicon substrate 8 Gate oxide film 9 Gate electrode 10 High concentration N-type impurity region 11 Channel layer region

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L ⁷ /06-7/14

Claims (8)

(57) [Claims] 1. A MOS PLL integrated circuit using a MOS capacitor as a capacitance of a loop filter of a phase locked loop circuit, wherein a threshold voltage of the MOS capacitor is an input of a voltage controlled oscillator when the PLL is locked. 75% to 100% of voltage
% PLL integrated circuit. 2. The threshold voltage of a MOS capacitor can be changed by changing the type of a metal electrode of the MOS capacitor.
7 of the input voltage of the voltage controlled oscillator when the PLL is locked
2. The PLL integrated circuit according to claim 1, wherein said PLL integrated circuit is present in a range of 5% to 100%. 3. The threshold voltage of the MOS capacitor is in the range of 75% to 100% of the input voltage of the voltage-controlled oscillator when the PLL is locked by changing the thickness of the gate oxide film of the MOS capacitor. 2. The PLL integrated circuit according to claim 1, wherein: 4. Changing the impurity concentration of the channel layer of the MOS capacitor so that the threshold voltage of the MOS capacitor is in the range of 75% to 100% of the input voltage of the voltage controlled oscillator when the PLL is locked. 2. The PLL integrated circuit according to claim 1, wherein: 5. A PLL integrated circuit of a MOS type using a MOS capacitor as a capacitance of a loop filter of a phase locked loop circuit, wherein a substrate bias of a portion of the MOS capacitor can be varied. circuit. 6. By changing the substrate bias,
The threshold voltage of the MOS capacitor is set to 75% to 100% of the input voltage of the voltage controlled oscillator when the PLL is locked.
% In the range of%.
Adjustment method of L integrated circuit. 7. A PLL integrated circuit of a MOS type using a MOS capacitor as a capacitance of a loop filter of a phase locked loop circuit, wherein the MOS capacitor has a double gate structure. 8. The voltage applied to the gate of the MOS capacitor is adjusted so that the threshold voltage of the MOS capacitor is in the range of 75% to 100% of the input voltage of the voltage controlled oscillator when the PLL is locked. 8. The method for adjusting a PLL integrated circuit according to claim 7, wherein: