JP3219307B2 - Semiconductor device structure and manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having ultra-fine, high-speed, and high reliability.

[0002]

2. Description of the Related Art A MOS (metal oxide semiconductor) type integrated circuit currently in practical use is a planar type MOS semiconductor in which an electric conduction path is formed in the same direction (horizontal direction) with respect to the direction of the surface of a semiconductor substrate. The device is used. In order to improve the degree of integration of an integrated circuit, it is necessary to reduce the area occupied by each element. A planar MOS field-effect transistor (hereinafter referred to as MOSFE) which is one of the planar MOS semiconductor devices.
In order to reduce the occupied area in (T), it is necessary to shorten the channel length or the channel width. However, doing so causes many problems such as a short channel effect, deterioration due to hot carriers, and a reduction in current driving capability. Therefore, it is difficult to effectively reduce the occupied area by reducing the channel length and channel width.

On the other hand, it has been found that device characteristics such as operating speed can be improved by completely depleting a semiconductor thin film portion in a MOSFET formed on an SOI (semiconductor thin film on insulator) substrate or the like. Research on chemical devices has been conducted recently. Also, a two-gate MOSFET having two gate electrodes sandwiching a channel region
Accordingly, research for improving the controllability of the drain current has been advanced.

Various methods have been tried to realize a device having a small occupied area, a fully depleted device, and a two-gate device as described above. As one of the above methods, there is a method of forming an electric conduction path by projecting in a direction perpendicular to the surface of a silicon substrate.

As described above, the MOSFE formed by projecting the electric conduction path in the direction perpendicular to the surface of the silicon substrate.
As T, there is a vertical MOSFET. This vertical MOSFE
In T, by forming the channel in a direction perpendicular to the surface of the silicon substrate, the occupied area can be reduced without shortening the channel length or reducing the channel width. In the above vertical MOSFET,
A gate electrode can be easily formed around a vertically formed channel region. Therefore, by making the vertical substrate portion where the channel region is formed into a sufficiently thin columnar shape, the columnar substrate portion can be completely depleted. Further, the above vertical MOSFET
In the above, two opposite portions of the substrate portion formed in a columnar shape
By forming a gate electrode along one side wall, 2
This makes it possible to easily realize a vertical MOSFET with completely depleted gates. As described above, by forming the electric conduction path so as to protrude in the vertical direction, a fine and high-speed semiconductor device can be formed.

Conventionally, as a method of manufacturing a vertical MOSFET, there is a method as shown in FIGS. Hereinafter, a conventional method for manufacturing a vertical MOSFET will be described with reference to FIGS.

First, as shown in FIG. 12A, boron ions are implanted into the surface of a silicon
The type impurity layer 2 is formed. After that, an etching mask (not shown) is formed on the p-type impurity layer 2 by photolithography. Then, the p-type impurity layer 2 was partially removed by RIE (Reactive Ion Etching) using the formed etching mask, and as shown in FIG. A silicon pillar 4 having a thickness of 5 μm is formed.

Next, as shown in FIG. 12C, a gate oxide film 5 having a thickness of 20 nm is formed by thermal oxidation.
As shown in (d), a polycrystalline silicon layer 6 is deposited to a thickness of 0.6 μm. Then, etching back is performed using a sidewall (sidewall) forming technique, as shown in FIG.
The gate electrodes 7, 7 are left except for the polycrystalline silicon layer 6 having a thickness of 0.3 μm in the horizontal direction.

Next, as shown in FIG. 13 (f), arsenic ions are implanted using the gate electrode 7 as a mask to a thickness of 0.3 μm.
The drain region 8 and the source region 3 are formed at a depth of. Thus, a vertical MOSFET is formed. In the vertical MOSFET having the above-described structure, channels are formed on both side surfaces of the silicon pillar 4 opposed to the gate electrodes 7, 7 with the gate oxide film 5 interposed therebetween. The vertical direction. still,
The drain region 8 and the source region 3 may be interchanged.

FIGS. 14 to 18 show an example of a lateral MOSFET in which an electric conduction path is formed by projecting in a direction perpendicular to the surface of a silicon substrate. Hereinafter, a method of manufacturing a conventional lateral MOSFET in which an electric conduction path is formed by projecting in a direction perpendicular to the silicon substrate surface will be described with reference to FIGS.

First, as shown in FIG. 14A, a silicon substrate 11 is thermally oxidized to form a silicon oxide film 12, and a silicon nitride film 13 is further laminated. Next, FIG.
As shown in (1), a resist pattern 14 is formed in the element formation region by photolithography. Then, using the resist pattern 14 as a mask, the silicon nitride film 1
3, the silicon oxide film 12 and the silicon substrate 11
FIG. 14 shows a state in which etching is continuously performed at a depth of about 00 nm.
A silicon pillar 15 as shown in FIG. After that, as shown in FIG.
4 is removed, and a silicon oxide film 16 is formed on the exposed surface of the silicon pillar 15 by thermal oxidation.

Next, as shown in FIG. 15E, a silicon nitride film 17 is laminated on the entire surface. Then, the entire surface of the silicon nitride film 17 is etched back, whereby the silicon nitride film 17 shown in FIG.
As shown in FIG. 5, sidewalls 18 of a silicon nitride film are formed on the side surfaces of the silicon pillar 15. Thereafter, the silicon substrate 1 not covered with the side walls 18 is subjected to high-temperature thermal oxidation.
1 is oxidized. Then, by further oxidizing, as shown in FIG. 15 (g), the silicon oxide film 1 is also formed on both sides of the silicon substrate 11 under the silicon pillars 15 from both sides.
9 grows to form a floating structure in which the silicon pillar 15 is floated.

Next, as shown in FIG. 16 (h), the silicon nitride film 13, the side wall 18, and the silicon oxide films 12, 1 are formed.
6 is removed. Then, as shown in FIG. 16I, the silicon pillar 15 is subjected to thermal oxidation to form a silicon oxide film 20 for a gate insulating film. Next, after laminating the low-resistance polycrystalline silicon film 21 for the gate electrode, the resist is patterned by photolithography, and the low-resistance polycrystalline silicon film 21 is patterned using the patterned resist as a mask.
Is etched to form a gate electrode as shown in FIG. Further, using the gate electrode 21 as a mask, impurity ion implantation 22 for forming a diffusion layer in the source / drain portion is performed.

After that, as shown in FIG. 17 (k), a silicon oxide film 23 is laminated on the entire surface and etched back to smooth the surface irregularities. Then, a contact hole 24 for taking out each electrode is formed. Next, a metal film is laminated, and a metal wiring layer 25 as shown in FIG. In this manner, as shown in the overall image in FIG. 18, a lateral MOSFET is formed in which the silicon pillar 15 as an electric conduction path is formed so as to project perpendicularly to the surface of the silicon substrate 11. Note that FIG.
Describes only one side of the source / drain electrodes, but it goes without saying that both electrodes are actually formed.

[0015]

However, the above-mentioned conventional MOSFET having an electric conduction path which projects perpendicularly to the surface of the silicon substrate has the following problems. First, in the method of manufacturing the vertical MOSFET, since the formation of the silicon pillar 4 depends on an etching mask formed by microfabrication by photolithography, the thickness of the silicon pillar 4 to be formed is limited by the fine processing technology. Therefore, the thickness cannot be reduced to about 0.5 μm or less. Therefore, in the vertical MOSFET formed as described above, when a voltage is applied to the opposing gate electrodes 7, 7, the p-type silicon portion is formed between the depletion layers formed on both sides of the silicon pillar 4. And the silicon pillar 4 cannot be completely depleted.

Therefore, a completely depleted MOSFET in which the silicon pillar 4 is completely depleted cannot be manufactured by the above-described vertical MOSFET manufacturing method. In other words, there is a problem that an ultra-fine and high-speed semiconductor device cannot be manufactured by the method of forming the semiconductor pillar by the fine processing.

In the above-described method of manufacturing a lateral MOSFET, the formation of the silicon pillar 15 is based on photolithography, and therefore has the same problem as that of the above-described vertical MOSFET. In addition, the above-mentioned structure-specific problems arise.

That is, as shown in FIGS. 16 (j) and 18, the gate electrode 21 in the case of the above-mentioned lateral MOSFET extends vertically along the side surface of the silicon pillar 15 projecting from the surface of the silicon substrate 11. And a portion extending horizontally along the surface of the silicon oxide film 19 following the portion. Therefore, when the gate electrode 21 having such a shape is formed by general photolithography, the above-described vertical portion of the low-resistance polycrystalline silicon film or the resist pattern formed on the silicon pillar 15 and the horizontal portion are formed. There is a danger that a constriction or the like may occur at a crossing point with the portion and the wire may be disconnected when the gate electrode 21 is formed by etching. That is,
There is a problem that the element characteristics are adversely affected.

An object of the present invention is to provide a structure and a manufacturing method of a semiconductor device which is ultra-fine, has high speed, and has high reliability without being affected by the limit of fine processing.

[0020]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a thin film pattern on a semiconductor substrate of a predetermined conductivity type; Removing the thin film pattern after forming a side wall around the entire periphery to leave only the frame-shaped side wall on the semiconductor substrate; and performing etching using the side wall as a mask to form a frame-shaped half-side on the semiconductor substrate. The method is characterized by comprising a step of forming a conductor pillar and a step of forming an electrode surrounding the semiconductor pillar after removing the side wall.

Further, according to a second aspect of the present invention, in the method of manufacturing a semiconductor device, a thin film pattern is formed on a semiconductor substrate of a predetermined conductivity type, and a first sidewall is formed on the thin film pattern by a sidewall formation technique. Removing a pattern to leave only the first side wall on the semiconductor substrate; performing etching using the first side wall as a mask to form a semiconductor pillar on the semiconductor substrate; Forming a second side wall on the side surface of the semiconductor pillar by a technique; and performing thermal oxidation using the first and second side walls covering the semiconductor pillar as a protective film to form an oxide film on the surface of the semiconductor substrate. Forming and insulating the semiconductor pillar from the semiconductor substrate; and forming an electrode surrounding the semiconductor pillar after removing the first and second sidewalls. It is characterized by comprising.

[0022] In the method of the third invention, a predetermined conduction type which is formed in an island shape on the insulating layer a thin film pattern formed on the semiconductor thin film, the thin film pattern by the side wall forming technique Removing the thin film pattern after forming a side wall on the entire circumference to leave only a frame-shaped side wall on the semiconductor thin film; and performing etching until the insulating layer is reached using the side wall as a mask. Frame on insulating layer
The method is characterized by comprising a step of forming a semiconductor pillar having a shape, and a step of forming an electrode surrounding the periphery of the semiconductor pillar after removing the side wall.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to third aspects, the electrode surrounds a part of the periphery of the semiconductor pillar. It is characterized by being formed by.

Further, the structure of the semiconductor device of the fifth invention is as follows.
A semiconductor pillar having a predetermined conductivity type and a plate-shaped semiconductor pillar protruding through an insulating film formed on the surface of the semiconductor substrate; and an upper edge of the semiconductor pillar having a predetermined width and a predetermined depth. The semiconductor device is characterized in that it has a narrow portion formed by cutting a groove, and an electrode that passes through an insulating film on the surface of the semiconductor substrate and surrounds the narrow portion along the side wall of the narrow portion in the semiconductor pillar.

Further, a method of manufacturing a semiconductor device of the sixth aspect of the present invention, a step of forming a sidewall on the semiconductor pillar and forming a semi-conductor columns in a predetermined conductivity type semiconductor substrate, the side wall forming technique, Performing a thermal oxidation process using the side walls covering the semiconductor pillars as a protective film to form an oxide film on the surface of the semiconductor substrate to insulate the semiconductor pillars from the semiconductor substrate; and removing the sidewalls and removing the electrodes on the semiconductor pillars. A step of forming a resist pattern having an opening at the formation location, etching the semiconductor pillar using the resist pattern as a mask to make the height of the electrode formation location lower than at other locations, and the step of forming the oxidation formed on the surface of the semiconductor substrate. Forming a vacant portion by etching down the periphery and the lower part of the film at the electrode forming location by isotropic etching conditions; Laminated body film is patterned after covering the electrode formation portion of the semiconductor pillar with fill the empty deletion unit is characterized by comprising a step of forming an electrode surrounding the electrode formation portion.

[0026]

According to the fifth aspect of the present invention, the semiconductor pillar as an electric conduction path is formed on the semiconductor substrate so as to protrude via the insulating film formed on the surface of the semiconductor substrate. Then, along the side wall of the narrow portion formed by cutting a groove having a predetermined width and a predetermined depth at the upper edge of the semiconductor pillar, an insulating film formed around the narrow portion on the surface of the semiconductor substrate is formed. An electrode is formed so as to pass through and surround. As described above, by forming the narrow portion of the semiconductor pillar thin and fine and surrounding it with the electrode, when a bias voltage is applied, the depletion layer spreads over the entire narrow portion and a high-speed complete depletion operation is performed. .

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. <First Example> This example relates to a method for forming a semiconductor pillar protruding from the surface of a semiconductor substrate without depending on fine processing by photolithography. Hereinafter, in this example, a MOSFET will be described as an example of a semiconductor device. First Embodiment FIG. 1 shows a vertical MOSFET according to this embodiment.
It is a cross-sectional view in the manufacturing process of. Hereinafter, a method of manufacturing the vertical MOSFET will be described with reference to FIG.

First, as shown in FIG. 1A, a normal photolithography and R
A pattern 32 of SiO ₂ (silicon oxide) is formed by the IE method. Next, as shown in FIG. 1 (b), a Si ₃ N ₄ (silicon nitride) film 33 is formed to a thickness of 100 nm. Thereafter, as shown in FIG. 1 (c), the entire surface is etched by RIE to form sidewalls 33a of Si ₃ N _{4 on} both side surfaces of the SiO ₂ pattern 32. Side wall 33a formed in this case
In the horizontal direction (hereinafter, simply referred to as the thickness of the side wall 33a)
Is 50 nm, but the thickness of the side wall 33 a can be controlled by the thickness of the SiO ₂ pattern 32 or the thickness of the Si ₃ N ₄ film 33.

Next, as shown in FIG. 1D, only the SiO ₂ pattern 32 is selectively removed by immersion in a hydrofluoric acid solution. After that, as shown in FIG. 1E, the p-type silicon substrate 31 is etched to a depth of 300 nm by RIE using the side wall 33a as an etching mask to form a silicon column 31a. Thus, in this embodiment,
Side wall 33 serving as an etching mask by film forming technology and sidewall forming technology without using photolithography
Since a is formed, the thickness of the silicon pillar 31a is not affected by the limitation of the fine processing.

Next, as shown in FIG. 2F, after arsenic ions are implanted into the p-type silicon substrate 31 to form the source region 34, the side walls 33a made of Si ₃ N ₄ are removed by a phosphoric acid solution. . Further, as shown in FIG.
A gate oxide film 35 is formed with a thickness of. Next, FIG.
As shown in FIG.
Flatten to a thickness of μm. After that, as shown in FIG. 2 (i), the gate electrode 36a is formed by etching back, leaving a tungsten layer at a height of 0.1 μm.

Further, as shown in FIG. 2 (j), arsenic ions are implanted into the tip of the silicon pillar 31a to form a drain region 37 having a depth of 0.2 μm. Thus, a vertical MOSFET whose channel length (depending on the depth of the drain region 37) is adjusted to 0.1 μm is formed.
The drain region 37 and the source region 34 may be interchanged.

Here, as shown in FIG. 2I, the shape controllability in forming the gate electrode 36a by etching back the flattened tungsten layer 36 is good.
The height of the gate electrode 36a is constant at a controlled height. Therefore, the depth of the drain region 37 when the arsenic ions are implanted next to form the drain region 37 can be accurately controlled by the height of the gate electrode 36a. Thus, the channel lengths of the channels formed on both side surfaces of the silicon pillar 31a are easily and accurately controlled.

The thickness of the silicon pillar 31a in the horizontal direction is limited to the limit of fine processing by forming the thickness of the side wall 33a of Si ₃ N ₄ shown in FIG. It can be set thin regardless of the setting. Here, the thickness of the side wall 33a can be controlled by the thickness of the SiO ₂ pattern 32 and the thickness of the Si ₃ N ₄ film 33 as described above. Therefore, the thickness of the silicon pillar 31a of the vertical MOSFET formed by the manufacturing method of the vertical MOSFET of the present embodiment can be set to 0.5 μm or less.

FIG. 3 is a bird's-eye view of the intermediate part corresponding to FIG. 2 (f). As can be easily understood from FIG. 3, the silicon pillar 31a formed according to the present embodiment may have a frame shape as shown in FIG. It may be two flat plates. In each case,
Channels will be formed on opposite sides of the flat portion of the silicon pillar 31a. If the thickness of the silicon pillar 31a is sufficiently small, both depletion layers formed inward from the both sides will be formed at the center. Overlap, silicon pillar 3
1a has only two depletion layers overlapping two channels. Thus, a fully-depleted vertical MOSFET is manufactured.

As described above, according to the present embodiment, Si
The silicon pillar 3 is formed by using the side wall 33a whose thickness is controlled by the thickness of the O ₂ pattern 32 and the thickness of the Si ₃ N ₄ film 33.
1a. Therefore, the thickness of the silicon pillar 31a can be set to be thin regardless of the limit of the fine processing, and a fully depleted vertical MOSFET can be formed. In other words, by forming the above-mentioned electric conduction path vertically, a fine structure is realized, and by forming a thin silicon pillar without depending on fine processing, a superfine structure and complete depletion are realized, A fine and high-speed semiconductor device can be manufactured.

[Second Embodiment] FIG. 4 is a cross-sectional view of a vertical MOSFET according to this embodiment in a manufacturing process. Hereinafter, according to FIG. 4, a vertical MOSF different from that of the first embodiment will be described.
A method for manufacturing ET will be described. First, according to the manufacturing method of the vertical MOSFET in the first embodiment, FIG.
The silicon pillar 3 having the Si ₃ N ₄ side wall 33a as shown in FIG.
1a is formed on a p-type silicon substrate 31. The height of the silicon pillar 31a formed in this case is desirably 500 nm.

Next, as shown in FIG. 4 (f), after forming a Si ₃ N ₄ film 42 with a thickness of 50 nm, the whole surface is etched back by the RIE method, and as shown in FIG. A side wall 42a of Si ₃ N ₄ is formed. Next, as shown in FIG. 4H, an oxide film 43 is formed by performing thermal oxidation, and the silicon pillar 31a is insulated from the p-type silicon substrate 31 by the oxide film 43. After that, as shown in FIG. 4 (i), the side walls 42a and 33a are removed with a phosphoric acid solution to leave the silicon pillars 31a.

Next, as shown in FIG. 4 (j), after forming a gate oxide film 44 on the surface of the silicon pillar 31a,
Arsenic ions are implanted to form a source region 45 below the silicon pillar 31a. Subsequently, as shown in FIG. 4K, a gate electrode 46 and a drain region 47 are formed in the same manner as in the first embodiment (see FIGS. 2H to 2J). In this way, the vertical MO whose channel length is adjusted
An SFET is formed. It goes without saying that the drain region 47 and the source region 45 may be interchanged.

As described above, according to the present embodiment, similarly to the first embodiment, the channel length can be controlled with high accuracy, and the thickness of the silicon pillar 31a is set to be thin regardless of the limit of fine processing. Therefore, a fully depleted MOS semiconductor device can be manufactured. In addition, the fully-depleted vertical MOSFET formed according to the present embodiment has the same structure as the SOI structure as shown in FIG.
Therefore, since each element is separated, the parasitic capacitance between the elements can be reduced, and the speed can be further increased.

[Third Embodiment] FIG. 5 is a cross-sectional view in the process of forming a lateral MOSFET according to this embodiment. Hereinafter, a method for manufacturing a lateral MOSFET different from the first and second embodiments will be described with reference to FIG. First, according to the manufacturing method in the second embodiment, as shown in FIG. 4I, a silicon pillar 31a is formed on a p-type silicon substrate 31 from the p-type silicon substrate 31 by an oxide film 43. .

Next, as shown in FIG. 5J, a gate oxide film 51 is formed on the surface of the silicon pillar 31a. And
As shown in FIG. 5 (k), after the surface is covered with a tungsten layer, patterning is performed to leave the tungsten layer only at the central portion in the longitudinal direction of the silicon pillar 31a, so that the gate electrode 5
Form 2 Next, arsenic ions are implanted into the silicon pillar 31a using the gate electrode 52 formed as a mask. Thus, the gate electrode 5 on the silicon pillar 31a is formed.
The source region and the drain region are formed at the same time in a portion not covered by the second region.

FIG. 6 shows a horizontal type M formed according to this embodiment.
FIG. 6A is a bird's-eye view of the OSFET. FIG. 6A shows a case where the silicon pillar 31a is in a frame shape, and FIG.
The case where a is a flat plate facing each other is shown. In any case, for example, the gate electrode 52 in the silicon pillar 31a is used.
If the source region 53 is located on the near side in the figure, the drain region 54 is located on the silicon pillar 31a behind the gate electrode 52 in the figure. Therefore, FIG. 5 (k), which is a cross-sectional view including the gate electrode 52 in FIG.
The source region 53 and the drain region 54 do not appear.

Thus, a lateral MOSFET is formed. In this case, the drain region 54 and the source region 53 may be interchanged. In this case, in the obtained lateral MOSFET, a channel is formed in the width direction (horizontal direction) of the gate electrode 33 on both side surfaces of the silicon pillar 31a. Therefore, the channel length can be adjusted by the width of the gate electrode 52.

As described above, according to the present embodiment, the channel length can be controlled with high accuracy, as in the case of the second embodiment.
A thin silicon pillar can be formed irrespective of the limit of microfabrication, and a SOI structure can be formed to manufacture a faster fully depleted vertical MOSFET. In addition, in the manufacturing method of the lateral MOSFET according to the present embodiment, the source region 5 is formed by one ion implantation using the gate electrode 52 as a mask.
3 and the drain region 54 can be formed simultaneously.

In the case of the second and third embodiments, the SOI structure is consequently obtained. Therefore, a fully depleted MOSF using an SOI substrate from the beginning
ET may be formed. That is, according to the method of manufacturing a vertical MOSFET according to the first embodiment, a silicon thin film formed in an island shape on an insulator in an SOI substrate is etched into a columnar shape by etching using a side wall formed by a film forming technique and a sidewall forming technique as a mask. And an intermediate part as shown in FIG. 4 (i) is created. Thereafter, the second embodiment or the third embodiment may be performed according to the procedure shown in FIG. 4 (j) or FIG. 5 (j).

In the first and second embodiments, it is not necessary to surround the entire periphery of the silicon pillar 31a with the gate electrode when forming the gate electrode. That is, FIG.
In the case of the frame-shaped silicon pillar 31a as shown in FIG. 3A, the gate electrode may be formed so as to sandwich only both side surfaces of the two opposing flat plate portions. In the case of flat silicon pillars 31a opposed to each other as shown in FIG. 3B, the gate electrodes may be formed only on the side surfaces of the respective silicon pillars 31a.

<Second Example> In this example, when a gate electrode surrounding a silicon pillar formed so as to protrude from the surface of a semiconductor substrate is formed by general photolithography, a lateral semiconductor such that a constriction does not occur in a resist pattern or the like. It relates to the structure and characteristics of the device. Hereinafter, the present embodiment will be described by taking a horizontal MOSFET as an example.

Fourth Embodiment FIGS. 7 to 11 are cross-sectional views of a lateral MOSFET according to this embodiment in a manufacturing process. Hereinafter, a method for manufacturing a lateral MOSFET will be described with reference to FIGS.

First, as shown in FIG. 7A, a silicon substrate 61 is thermally oxidized to form a silicon oxide film 62, and a silicon nitride film 63 is further laminated. Next, as shown in FIG. 7B, a resist pattern 64 is formed in the element formation region by photolithography. Then, using the resist pattern 64 as a mask, the silicon nitride film 63, the silicon oxide film 62 and the silicon substrate 61 are several hundred nm thick.
The silicon pillar 65 as shown in FIG. After that, Figure 7
As shown in (d), the resist pattern 64 is removed, and a silicon oxide film 66 is formed on the exposed surface of the silicon pillar 65 by thermal oxidation.

Next, as shown in FIG. 8E, a silicon nitride film 67 is laminated on the entire surface. Then, the silicon nitride film 67
By etching back the entire surface, the side wall 6 of the silicon nitride film is formed on the side surface of the silicon pillar 65 as shown in FIG.
8 is formed. Thereafter, the silicon substrate 61 not covered with the side walls 68 is oxidized by performing high-temperature thermal oxidation. Then, by further oxidizing, as shown in FIG. 8 (g), a silicon oxide film 69 grows from both sides below the silicon pillar 65 in the silicon substrate 61 to form a floating structure in which the silicon pillar 65 is floated. Is done.

Next, as shown in FIG. 9H, the silicon nitride film 63, the side walls 68, and the silicon oxide films 62, 6 are formed.
6 is removed. Then, patterning is performed by providing an opening with a resist mask in a region of the silicon pillar 65 where a channel is to be formed, and the silicon pillar 65 is etched using the resist as a mask. Thus, FIG. 9 (i)
As shown in the figure, the height of the channel formation region 76 in the silicon pillar 65 is reduced to about 100 nm.

Further, the periphery of the channel forming region 76 and the lower layer of the silicon oxide film 69 are dug down under the same mask under isotropic etching conditions (conditions in which the etching rates in the depth direction and the horizontal direction are equal). Etching in the direction is performed. Thus, the silicon oxide film 69 below the bottom surface of the silicon pillar 65 is removed to form a void 77 as shown in FIG.

Next, the silicon pillar 65 including the channel forming region 76 is subjected to thermal oxidation to form a silicon oxide film 70 for a gate insulating film. Then, a low-resistance polycrystalline silicon film 71 for a gate electrode is stacked to fill the void 77 and to form a channel forming region 7 in the silicon pillar 65.
After covering the top 6, the resist is patterned by photolithography, and using this as a mask, the low-resistance polycrystalline silicon film 71 is etched to form a gate electrode as shown in FIG. Further, the gate electrode 71
Is used as a mask to perform impurity ion implantation 72 for forming a diffusion layer in the source / drain portion.

After that, a silicon oxide film 73 is laminated on the entire surface and etched back to smooth the surface irregularities. Then, as shown in FIG. 10 (l), a contact hole 74 for taking out each electrode is formed. Next, a metal film is laminated, and a metal wiring layer 75 as shown in FIG. In this manner, as shown in the overall image of FIG. 11, a lateral MOSFET is formed in which the silicon pillar 65 as an electric conduction path is formed so as to project in the direction perpendicular to the surface of the silicon substrate 61. Note that FIG.
In the above, only one side of the source / drain electrode is described, but actually both electrodes are formed.

The lateral MOSFE thus formed is
In T, as shown in FIG. 11, a silicon pillar 65 as an electric conduction path protrudes from the surface of the silicon substrate 61, and the height of only the channel formation region 76 in the silicon pillar 65 is reduced. Then, the channel forming region 76
A void portion 77 is provided in the lower silicon oxide film 69, and has a structure in which a gate electrode 71 surrounds the periphery of a thin and fine channel formation region 76. Therefore, when a gate bias is applied to the channel formation region 76, the depletion layer can easily spread over the entire channel,
Thus, a transistor having a completely depleted operation can be obtained.

At this time, if the height of the whole silicon pillar 65 is reduced, the resistance of the source / drain portion is increased, which hinders the high-speed operation which is an advantage of the complete depletion device. Therefore, in the present embodiment, the source / drain portion is formed to have a large area and only the channel formation region 76 is formed to be narrow.

The lateral MOSFET according to the present embodiment is
Has a structure in which the height of the channel formation region 76 in the silicon pillar 65 is low as described above. Therefore,
In this method of manufacturing a lateral MOSFET, when the gate electrode 71 is formed by general photolithography, the low-resistance polycrystalline silicon film 71 formed on the silicon pillar 65 and the vertical portion of the resist pattern are short. Constriction is unlikely to occur, and there is little risk of disconnection or the like when forming the gate electrode 71 by etching. That is, according to the present embodiment, a lateral MOSFET that does not adversely affect the element characteristics can be easily manufactured.

The above-described fully depleted transistor is suitable for low-voltage operation because the current driving force can be increased and the current characteristic rises steeply. In addition, since the operation speed can be maintained at a high speed without lowering the threshold voltage, the threshold voltage can be maintained at a high value, and an allowable range of the variation of the threshold voltage can be set, so that the reliability of the transistor element can be improved.

In the fourth embodiment, the silicon pillar 6
In forming the resist pattern 5, a resist pattern 64, which is a mask for etching the silicon substrate 61, is formed by photolithography. However, the present invention is not limited to this, and the first example (first example)
Similarly to the third to third embodiments), a sidewall may be formed on a thin film pattern formed on a silicon substrate by a sidewall formation technique, and the thin film pattern may be formed by etching using the sidewall as a mask.

In each of the above embodiments, a method for manufacturing an ultra-fine and high-speed semiconductor device has been described using a MOSFET as an example. However, the present invention can be applied to the manufacture of other semiconductor devices without any problem.

[0061]

As apparent from above, according to the present invention, a method of manufacturing a semiconductor device of the first invention, the side wall in a frame shape by the side wall forming technique the entire periphery of the thin film pattern formed on a predetermined conductivity type of the semiconductor substrate After forming the above, the thin film pattern is removed, and etching is performed using the side wall as a mask.
Since a frame-shaped semiconductor pillar is formed, and after removing the side wall, an electrode is formed so as to surround the semiconductor pillar, an etching mask for forming the semiconductor pillar can be formed regardless of fine processing by photolithography. . Therefore, the thickness of the semiconductor pillar can be reduced regardless of the limit of the fine processing. As a result, when electric conduction paths are formed on both side surfaces of the semiconductor pillar, the semiconductor pillar is completely depleted,
An ultrafine and high-speed semiconductor device can be manufactured.

Further, in the method of manufacturing a semiconductor device according to the second invention, the first side wall is formed by a side wall forming technique on a thin film pattern formed on a semiconductor substrate of a predetermined conductivity type, and then the thin film pattern is removed. The semiconductor pillar is formed by etching using the first sidewall as a mask, a second sidewall is formed on a side face of the semiconductor pillar, and the semiconductor pillar is oxidized by performing thermal oxidation using the both sidewalls as protective films. Since the film is insulated from the semiconductor substrate and the side walls are removed, the electrodes are formed so as to surround the semiconductor pillars, so that the semiconductor elements formed by the semiconductor pillars surrounded by the electrodes can be separated. Therefore, it is possible to manufacture an ultra-fine and higher-speed semiconductor device having the same structure as the SOI structure.

The method of manufacturing a semiconductor device according to the third aspect of the present invention is a method of manufacturing a semiconductor device, comprising forming a frame around the entire periphery of a thin film pattern formed on a semiconductor film of a predetermined conductivity type formed in an island shape on an insulating layer by a sidewall forming technique. After forming the side wall in a shape, the thin film pattern is removed, and etching is performed using the side wall as a mask to form a frame-shaped semiconductor pillar on the insulating layer. After the sidewall is removed, the periphery of the semiconductor pillar is surrounded. Since the electrodes are formed by using the same method, an ultra-fine and high-speed semiconductor device having the same structure as the SOI structure can be manufactured more easily.

The structure of the semiconductor device of the fifth invention is as follows.
A plate-shaped semiconductor pillar protruding from a semiconductor substrate via an insulating film, a narrow portion formed by engraving a groove of a predetermined width and a predetermined depth on an upper edge of the semiconductor pillar, Since the electrode surrounding the periphery is provided, the narrow portion in the semiconductor pillar has a fine and fine shape. Therefore, when a bias voltage is applied from the electrode surrounding the narrow portion to the narrow portion, a depletion layer spreads over the entire narrow portion, and a high-speed and high-reliability semiconductor device exhibiting a complete depletion operation can be provided.

[0065] In the method of the sixth aspect of the present invention, to form the sidewall by a side wall forming technique the semiconductor Columns made form a predetermined conductivity type semiconductor substrate, thermal oxidation of the side walls as a protective film To form an oxide film on the surface of the semiconductor substrate, insulate the semiconductor pillar from the semiconductor substrate, etch the electrode formation location on the semiconductor pillar lower than other locations, and oxidize the surface of the semiconductor substrate. The periphery and the lower part of the film on the electrode forming portion are etched to form a void, and the electrode forming portion on the semiconductor pillar is surrounded by an electrode semiconductor film and patterned to form an electrode. An ultra-fine electric conduction path can be formed without being affected by processing limitations. Further, since the height of the electrode forming portion in the semiconductor pillar formed according to the present invention is low, when the electrode surrounding the electrode forming portion is formed by the usual photolithography technique, the resist pattern is unlikely to be constricted. Therefore, according to the present invention, a semiconductor device having high speed and high reliability can be easily formed.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a vertical MOSFET manufacturing process according to an embodiment of a semiconductor device manufacturing method of the present invention.

FIG. 2 is an explanatory view of the manufacturing process following FIG. 1;

FIG. 3 is a bird's-eye view of an intermediate part corresponding to FIG. 2 (f).

FIG. 4 is an explanatory diagram of another vertical MOSFET manufacturing process.

FIG. 5 is an explanatory diagram of a horizontal MOSFET manufacturing process.

FIG. 6 is a bird's-eye view of the lateral MOSFET corresponding to FIG. 5 (k).

FIG. 7 is an explanatory diagram of a lateral MOSFET manufacturing process different from FIG. 5;

FIG. 8 is an explanatory view of the manufacturing process following FIG. 7;

FIG. 9 is an explanatory view of the manufacturing process following FIG. 8;

FIG. 10 is an explanatory diagram of the manufacturing process following FIG. 9;

FIG. 11 is an explanatory view of the manufacturing process following FIG. 10;

FIG. 12 is an explanatory diagram of a manufacturing process according to a conventional method for manufacturing a vertical MOSFET.

FIG. 13 is an explanatory diagram of the manufacturing process following FIG. 12;

FIG. 14 is an explanatory diagram of a manufacturing process according to a method of manufacturing a lateral MOSFET in another conventional example.

FIG. 15 is an explanatory diagram of the manufacturing process following FIG. 14;

FIG. 16 is an explanatory view of the manufacturing process continued from FIG. 15;

FIG. 17 is an explanatory diagram of the manufacturing process following FIG. 16;

FIG. 18 is an explanatory view of the manufacturing process following FIG. 17;

[Explanation of symbols]

31: p-type silicon substrate, 31a: silicon pillar, 33a, 42a: side wall, 34, 4
5, 53 ... source region, 35, 44, 51 ... gate oxide film, 36 a, 46, 52 ... gate electrode, 37, 47,
54 ... drain region, 43 ... oxide film, 61 ... silicon substrate, 62, 66, 69, 73 ... silicon oxide film, 6
3, 67: silicon nitride film, 65: silicon pillar, 68: side wall, 71: low resistance polycrystalline silicon film, 76: channel formation region,
77 ... Empty space.

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/78 618D (56) References JP-A-2-263473 (JP, A) JP-A-64-35957 (JP, A) JP-A-2-119188 (JP, A) JP-A-2-17675 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 29/786 H01L 21/334 -21/336 H01L 21/302

Claims (6)

(57) [Claims] 1. A thin film pattern is formed on a semiconductor substrate of a predetermined conductivity type, side walls are formed on the entire periphery of the thin film pattern by a sidewall forming technique, and then the thin film pattern is removed to form a frame on the semiconductor substrate. Leaving only the side wall of the above; forming the frame-shaped semiconductor pillar on the semiconductor substrate by etching using the side wall as a mask; removing the side wall and surrounding the periphery of the semiconductor pillar with an electrode. Forming a semiconductor device. 2. A thin film pattern is formed on a semiconductor substrate of a predetermined conductivity type, a first side wall is formed on the thin film pattern by a sidewall forming technique, and then the thin film pattern is removed to form a thin film pattern on the semiconductor substrate. A step of leaving only one side wall; a step of performing etching using the first side wall as a mask to form a semiconductor pillar on the semiconductor substrate; and a second sidewall on a side surface of the semiconductor pillar by a sidewall formation technique. Forming a silicon oxide film on the surface of the semiconductor substrate by performing thermal oxidation using the first side wall and the second side wall covering the semiconductor pillar as a protective film to insulate the semiconductor pillar from the semiconductor substrate. A step of forming an electrode surrounding the semiconductor pillar after removing the first side wall and the second side wall. Method. 3. A thin film pattern is formed on a semiconductor film of a predetermined conductivity type formed in an island shape on an insulating layer, and a sidewall is formed on the entire periphery of the thin film pattern by a sidewall forming technique, and then the thin film pattern is formed. Removing and leaving only a frame-shaped side wall on the semiconductor thin film; etching using the side wall as a mask until reaching the insulating layer to form a frame-shaped semiconductor pillar on the insulating layer; A method of manufacturing a semiconductor device, comprising a step of forming an electrode surrounding the semiconductor pillar after removing the side wall. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the electrode is formed so as to surround a part of a periphery of the semiconductor pillar. A method for manufacturing a semiconductor device. 5. A semiconductor pillar having a predetermined width formed on a semiconductor substrate of a predetermined conductivity type and protruding through an insulating film formed on the surface of the semiconductor substrate, and an upper edge of the semiconductor pillar having a predetermined width. A narrow portion formed by engraving a groove having a predetermined depth, and an electrode that passes through the insulating film on the surface of the semiconductor substrate and surrounds the periphery of the narrow portion along the side wall of the narrow portion in the semiconductor pillar. A structure of a semiconductor device, characterized in that: 6. A predetermined conductivity type of the semiconductor substrate and forming a semi-conductor post, forming a side wall on the semiconductor pillar by sidewall forming techniques, thermal oxidation sidewalls covering the semiconductor pillar as a protective film Performing an oxide film on the surface of the semiconductor substrate, insulating the semiconductor pillar from the semiconductor substrate, and forming a resist pattern in which an electrode formation location in the semiconductor pillar is opened after removing the sidewall. Etching the semiconductor pillars using the resist pattern as a mask to lower the height of the electrode formation location than other locations; and forming the periphery and the lower part of the electrode formation location in the oxide film formed on the semiconductor substrate surface. A step of forming a vacant space by etching under an isotropic etching condition, and laminating a semiconductor film for an electrode to fill the vacant space. Both the method of manufacturing a semiconductor device characterized by comprising a step of forming an electrode surrounding the electrode forming portion by patterning after covering the electrode formation portion of the semiconductor pillar.