JP3349479B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique particularly effective when used in a dynamic RAM (random access memory) having a built-in voltage conversion circuit.

[0002]

2. Description of the Related Art As the integration and capacity of dynamic RAMs and the like have become higher and smaller, circuit elements have been miniaturized. As one means for compensating for a decrease in breakdown voltage, the value of an internal power supply voltage in a chip is set to, for example, +3. A method of reducing the voltage to about 3 V has been adopted. In this case, it is effective to standardize the external power supply voltage supplied from the outside to, for example, +5.0 V and unify the external power supply voltage into a single unit. A voltage conversion circuit for forming the internal power supply voltage is provided.

On the other hand, a dynamic RAM as described above
For example, a MOSFET (metal oxide semiconductor type field effect transistor; in this specification, a MOSFET is generally referred to as an insulated gate type field effect transistor) in which a failure easily occurs due to a gate oxide film defect or the like. In order to perform early detection, a so-called burn-in (aging) test for performing an acceleration test in a state where the power supply voltage or the ambient temperature is abnormally high, for example, is performed. At this time, the value of the internal power supply voltage is increased until just before a normal circuit element is destroyed, thereby increasing the error detection rate and test efficiency of the burn-in test. A dynamic RAM incorporating a voltage conversion circuit is disclosed in, for example, JP-A-59-110.
225, etc.

[0004]

In a dynamic RAM or the like having a built-in voltage conversion circuit as described above, the value of the internal power supply voltage is substantially constant even when the value of the external power supply voltage fluctuates as described above. It is said. Therefore, even if the external power supply voltage is increased to perform the burn-in test, the internal power supply voltage does not change, and a desired acceleration test cannot be performed. In order to cope with this, the present inventors have developed a voltage conversion circuit having an output characteristic as shown in FIG. 3 prior to the present invention.

That is, in a normal area NM where a normal operation of a dynamic RAM or the like is performed, the output signal of the voltage conversion circuit VC, that is, the value of the internal power supply voltage VCL is irrespective of the value of the external power supply voltage VCL (for example, +3.3 V). When the external power supply voltage VCL is further increased to reach the so-called burn-in region BT,
Internal power supply voltage VCL is increased in proportion to external power supply voltage VCL. As a result, the internal power supply voltage VCL is raised to the predetermined high voltage VCL only by increasing the external power supply voltage VCL to a predetermined value, as in the case of a conventional dynamic RAM or the like.
B, a desired burn-in test can be performed.

However, these dynamic type R
The inventors of the present application have further clarified that the following problems remain in AM and the like. That is, in the voltage conversion circuit having the output characteristics shown in FIG. 3, for example, a plurality of MOSFETs in a series form and a diode form are used.
Based on the combined threshold voltage of T, level difference VS between external power supply voltage VCL and internal power supply voltage VCL in burn-in region BT is set. As is well known, the threshold voltage of a MOSFET fluctuates relatively largely with the manufacturing process and the ambient temperature.

Therefore, even if the external power supply voltage VCL is set to a predetermined design value, the value of the internal power supply voltage VCL exhibits a relatively large fluctuation EO as shown by a dotted line in FIG.
This lowers the error detection rate of the burn-in test, that is, the screening accuracy, lowers the reliability of the dynamic RAM, reduces the test efficiency of the dynamic RAM, etc., and lowers the yield due to so-called overkill. Becomes

An object of the present invention is to provide a fuse circuit which can be programmed by cutting fuse means.
It is an object of the present invention to provide a semiconductor integrated circuit device provided with a fuse circuit capable of setting a pseudo program state without cutting a fuse unit. Another object of the present invention is to suppress output voltage fluctuation in a burn-in area of a voltage conversion circuit that is built in a dynamic RAM or the like and has a burn-in area. Another object of the present invention is
It is an object of the present invention to improve the screening accuracy of a burn-in test for a dynamic RAM having a voltage conversion circuit and the like and to enhance the reliability of the dynamic RAM. A further object of the present invention is to improve the test efficiency and yield of a dynamic RAM or the like and reduce the cost. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a fuse circuit is provided for storing predetermined information in the fuse means according to the initial state and the program state, and the fuse circuit simulates the fuse means in the program state when the fuse means is in the initial state. The semiconductor integrated circuit device is configured so as to have a means for making it possible to trim the internal voltage and the like without physically cutting the fuse means, and to determine in advance the fuse means to be cut.
By checking, the trimming accuracy can be increased.

In a predetermined combination, a voltage conversion circuit built in a dynamic RAM or the like and having a so-called burn-in area whose output voltage, that is, the value of the internal power supply voltage is increased in proportion to the external power supply voltage during an acceleration test operation is cut off. A plurality of fuse means are provided which can selectively switch the value of the internal power supply voltage in the burn-in area by performing the operation. Further, in a predetermined test mode, the value of the internal power supply voltage can be monitored via a predetermined external terminal.

[0011]

FIG. 10 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied. FIG. 9 also shows the dynamic RA of FIG.
FIG. 1, FIG. 6, FIG. 7, and FIG. 8 show a block diagram of one embodiment of the voltage conversion circuit VC incorporated in M. In FIG. 1, reference voltage generation circuits VLG, VLG included in the voltage conversion circuit VC of FIG. Circuit diagrams of an embodiment of the reference potential generation circuit VRG, the fuse circuit FC, and the internal power supply voltage generation circuit IVG are shown respectively.

FIG. 2 shows an example of a partial equivalent circuit diagram of the reference potential generating circuit VLG of FIG. 1, and FIG. 3 shows an output characteristic diagram of the embodiment. With reference to these figures, an outline of the configuration, operation and characteristics of the dynamic RAM and the voltage conversion circuit of this embodiment, and the characteristics thereof will be described.

The circuit elements shown in FIGS. 1, 2 and 6 to 8 and the circuit elements forming each block shown in FIGS. 9 to 11 are not particularly limited by a known semiconductor integrated circuit manufacturing technique. It is formed over one semiconductor substrate such as single crystal silicon. In the following circuit diagram, a MOSFET (metal oxide semiconductor field effect transistor; an MOSFET is referred to as an insulated gate field effect transistor) in which an arrow is attached to a channel (pack gate) portion thereof. Is a P-channel type and an N-channel MOSFE without arrows
It is shown separately from T.

Although the dynamic RAM of this embodiment is not particularly limited, it has a relatively large storage capacity, circuit elements centering on memory cells are extremely miniaturized, and their breakdown voltage is low. For this reason, the internal circuit of the dynamic RAM including the memory array is not particularly limited, but may include +3.
The internal voltage VCL of 3 V is used as the operation power supply. And
The dynamic RAM is not particularly limited, but +
A voltage conversion circuit VC for forming the internal power supply voltage VCL based on the external power supply voltage VCC of 5.0 V is built in.
As a result, it is possible to reduce the power consumption of the dynamic RAM and to unify the external power supply voltage while preventing breakdown voltage breakdown of the circuit element.

In FIG. 10, a dynamic RAM
Although not particularly limited, a so-called shared sense method is adopted, and a pair of memory arrays MARYL and MARYR arranged with a sense amplifier SA interposed therebetween has a basic configuration. The memory arrays MARYL and MARYR include a plurality of word lines arranged in parallel in the vertical direction in FIG.
It includes a plurality of complementary bit lines arranged in parallel in the horizontal direction and a large number of dynamic memory cells arranged in a lattice at intersections of these word lines and complementary bit lines.

The word lines forming the memory arrays MARYL and MARYR are not particularly limited, but are coupled to the corresponding row address decoders RADL and RADR, respectively, and are selectively selected. The row address decoders RADL and RADR are not particularly limited.
I excluding the most significant bit from row address buffer RAB
Bit internal address signal a x0, a xi-1 (where complementary, expressed as e.g. non inverted internal Atoresu signal ax0 and inverted internal address signals ax0B complementary internal address signals together ax0. Further, the inverting signal, Like the inverted internal address signal ax0B, B is added to the end of the signal name. The same applies hereinafter) and the timing signals φxl and φxr are supplied from the timing generation circuit TG.

The row address buffer RAB includes:
X address signal A via address input terminals A0-Ai
X0 to AXi are supplied in a time-division manner, and a refresh address signal ar is supplied from a refresh address counter RFC.
0 to ari are supplied. Further, timing signals φar and φrf are supplied from the timing generation circuit TG to the row address buffer RAB, and a timing signal φrc is supplied to the refresh address counter RFC.

The row address decoder RADL is selectively activated when the timing signal φxl is set to a high level. In this operating state, the row address decoder RADL the complementary internal address signals a X0～
a xi-1 is decoded, and the corresponding word line of the memory array MARYL is alternatively set to a high level selected state. Similarly, the row address decoder RADR is a selectively operated state by a timing signal φxr is a high level, the complementary internal address signals a x0~ a xi-
1, the corresponding word line of the memory array MARYR is alternatively set to a high level selected state.

The row address buffer RAB is an address input terminal A when the dynamic RAM is set to a normal operation mode and the timing signal φrf is set to a low level.
X address signals AX0 to AXi supplied in a time-sharing manner through 0 to Ai are taken in according to a timing signal φar. When the dynamic RAM is set to the refresh mode and the timing signal φrf is set to the high level, the refresh address signals ar0 to ari supplied from the refresh address counter RFC are fetched. Then, based on these row address signals, to form a complementary internal address signals a x0~ a xi. Of these, the complementary internal address signals a xi of the most significant bit is supplied to the timing generation circuit TG, other complementary internal address signals a x0~ a xi-1, as described above, the row address decoder RADL and RADR Supplied in common.

The refresh address counter RFC is
When the dynamic RAM is set to the refresh mode, the dynamic RAM performs a stepping operation in accordance with the timing signal φrc to form the refresh address signals ar0 to ari, and supplies the refresh address signals ar0 to ari to the row address buffer RAB.

On the other hand, the complementary bit lines forming the memory array MARY are connected to the corresponding shared M of the sense amplifier SA.
Via the OSFET, it is coupled to the corresponding unit amplifier circuit of the sense amplifier SA. Complementary input / output nodes of these unit amplifier circuits further correspond to a pair of switch MOSFs.
Via ET, they are respectively coupled to complementary common data lines CD. In the shared MOSFET of the sense amplifier SA,
The timing signal φsl or φsr is commonly supplied, and the internal power supply voltage VCL and the ground potential are selectively supplied to the unit amplifier circuit via a pair of drive MOSFETs selectively turned on according to the timing signal φpa. You.

Switch MOS of each pair of sense amplifiers SA
The FETs are supplied with corresponding column selection signals from the column address decoder CAD. The column address decoder CAD includes a column address buffer CAB.
To i + 1-bit complementary internal address signals a y0 to a y
i is supplied, and a timing signal φy is supplied from the timing generation circuit TG. The column address buffer CAB is supplied with Y address signals AY0 to AYi in a time-division manner via address input terminals A0 to Ai, and a timing signal φac from a timing generation circuit TG.

Shared MOSFET of sense amplifier SA
Are selectively and simultaneously turned on by setting the corresponding timing signal φsl or φsr to a high level. Thereby, the memory array MARYL or MAR
A complementary bit line of YR is selectively connected to a complementary input / output node of a corresponding unit amplifier circuit of sense amplifier SA.

The unit amplifier circuit of the sense amplifier SA operates when the timing signal φpa is set to the high level and the drive MOSFET
Are supplied with the internal power supply voltage VCL and the ground potential, thereby selectively operating. In this operation state, the unit amplifier circuit of the sense amplifier SA amplifies a small read signal output from a plurality of memory cells coupled to a selected word line of the memory array ARYL or ARYR via a corresponding complementary bit line. , A high-level or low-level binary read signal.

As described above, each unit circuit of the sense amplifier SA further includes a plurality of pairs of N-channel type switches MO.
Includes SFET. One of these switches MOSFET, respectively coupled to the complementary output nodes of the corresponding unit amplifier of the sense amplifier SA, the other of, are commonly coupled to the non-inverting or inverting the signal lines of complementary common data lines C D. In addition, a common address gate of each pair of switch MOSFETs has a column address decoder CAD described later.
Supplies a corresponding column selection signal.
These column selection signals are normally all at low level, and when the dynamic RAM is selected,
It is alternatively set to a high level in accordance with the address signals AY0 to AYi.

Switch MOS of each pair of sense amplifiers SA
FET is selectively turned on by the corresponding column select signal are alternatively high level, the complementary output nodes and complementary common data lines C D of the corresponding unit amplifier
Connect selectively.

The column address decoder CAD is selectively activated by the timing signal φy being set to the high level. In this operation state, the column address decoder CAD supplies the complementary internal address signals a y0 to a y
yi is decoded, and the corresponding column selection signal is alternatively set to a high level.

The column address buffer CAB captures and holds the address signals AY0 to AYi supplied in a time division manner through the address input terminals A0 to Ai according to the timing signal φac. Further, based on these Y address signals, complementary internal address signals a y0 to a yi are formed and supplied to the column address decoder CAD.

The complementary common data line CD is
A. The main amplifier MA, is supplied complementary write signal W D from the data input buffer DIB, the output signal or the complementary read signal R D is supplied to the data output buffer DOB. Data input buffer DI
The input terminal of B is coupled to the data input terminal Din, and the output terminal of the data output buffer DOB is coupled to the data output terminal Dout. Main amplifier MA is supplied with timing signals φw and φr from timing generation circuit TG, and data output buffer DOB is supplied with timing signal φoe.

The main amplifier MA is a dynamic type RA
M is selected in the write mode and the timing signal φ
When w is at a high level, the data input buffer DI
Forming a predetermined write signal based on the complementary write signal WD supplied from B, and through the complementary common data lines C D, writing to selected memory cells of the memory array MARYL or MARYR. Also, dynamic RAM
Is selected in the read mode and the timing signal φr
Is set to a high level, the read signal output from the selected memory cell of the memory array MARYL or MARYR via the complementary common data line CD is further amplified, and the data output buffer D is output as the complementary read signal RD.
Transmit to OB.

When the dynamic RAM is selected in the write mode, the data input buffer DIB is
A complementary write signal WD is formed based on the write data supplied via the data input terminal Din, and is supplied to the main amplifier MA. Data output buffer DOB, when the timing signal φoe dynamic RAM is set to the selected state in the read mode is set to the high level, forming a predetermined output signal based on the complementary read signal R D supplied from the main amplifier MA Then, the data is output to the outside via the data output terminal Dout.

Incidentally, the dynamic type R of this embodiment
In AM, although not particularly limited, the internal power supply voltage supply point V
N-channel MOSFET receiving internal control signal tvo at its gate between CL and data output terminal Dout
Q79 is provided. Although the internal control signal tvo is not particularly limited, the column address strobe signal CAS
A so-called WCBR cycle in which B and the write enable signal WEB are set to a low level prior to the row address strobe signal RASB is executed, and at the same time, predetermined bits of the address signals A0 to Ai are set to a high level.
When the dynamic RAM is set to a predetermined test mode, it is selectively set to a high level.

The high level is formed by boosting the internal power supply voltage VCL, and is set to a high voltage higher than the internal power supply voltage VCL by at least the threshold voltage of the MOSFET Q79. Internal control signal tvo
Is at a high level, MOSFET Q79 is turned on, and internal power supply voltage VCL is output via an external terminal, that is, data output terminal Dout. as a result,
Internal power supply voltage VC without adding special external terminals
The trimming and evaluation of L can be performed efficiently, and the number of test steps for the dynamic RAM can be reduced.

The timing generation circuit TG includes, but is not limited to, a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB, which are externally supplied as start-up control signals.
Based on the complementary internal address signals a xi and address signals A0~Ai most significant bits supplied from the row address buffer RAB, to form the various timing signals and the internal control signal, and supplies to each circuit of the dynamic RAM .

Although not particularly limited, the voltage conversion circuit VC is supplied with an external power supply voltage VCC via a power supply voltage terminal VCC, and is supplied with a timing signal φvc from a timing generation circuit TG. Here, the external power supply voltage VCC is
Although not particularly limited, it is set to +5.0 V, and the timing signal φvc is selectively set to the high level while the dynamic RAM is in the selected state. External power supply voltage VCC
Is, although not particularly limited, a high internal power supply voltage VCC.
For example, a row address buffer RAB, a column address buffer CAB, and a data input buffer D
It is supplied to input / output circuits such as the IB and the data output buffer DOB.

The voltage conversion circuit VC is not particularly limited, but as shown in the block diagram of FIG. 9, a reference potential generation circuit VRG, a fuse circuit FC, and a reference potential generation circuit VL.
G and an internal power supply voltage generation circuit IVG. These circuits are supplied with the external power supply voltage VCC. Also,
Although not particularly limited, test control signals PFS0 to PFS5 are supplied to the fuse circuit FC via six test pads, and output signals thereof, that is, internal signals FN0 to FN7 are provided.
FB0 to FB7 are supplied to a reference potential generation circuit VLG.

The reference potential generation circuit VLG is further supplied with reference potentials VRN (first reference potential) and VRB (second reference potential) from the reference potential generation circuit VRG, and its output signal, that is, the reference potential VL is It is supplied to the internal power supply voltage generation circuit IVG. The timing signal φvc is further supplied to the internal power supply voltage generation circuit IVG, and the output signal, that is, the internal power supply voltage VCL is supplied to each circuit of the dynamic RAM.

Here, the reference potential generation circuit VRG of the voltage conversion circuit VC is not particularly limited, but as shown in FIG. 6, a bias circuit BC and two reference potential generation circuits VR are provided.
GN and VRGB. Among them, the bias circuit B
C is not particularly limited, but is constituted by three P-channel MOSFETs Q17 to Q19 and one N-channel MOSFET Q67 provided in series in the same manner as the external power supply voltage VCC and the ground potential of the circuit. MOSFET
Q17, Q18, and Q67 are in the form of diodes by having their gates and drains commonly coupled,
MOSFET Q19 is always turned on when its gate is coupled to the ground potential of the circuit. This allows
As gate voltages of MOSFETs Q17, Q18 and Q67, predetermined bias voltages VB1 to VB3 set by source / drain voltages of these MOSFETs, that is, threshold voltages, are obtained.

On the other hand, reference potential generating circuit VRGN is not particularly limited, but includes three P-channel MOs provided in series between external power supply voltage VCC and the ground potential of the circuit.
SFETs Q20 to Q22 and one N-channel MOSF
ETQ66 and another P-channel MOSFET Q23 provided in parallel with the MOSFETs Q22 and Q68. Here, MSFET Q23
Is a high threshold voltage type MOSFET, and its threshold voltage is about twice the threshold voltage V _THP of a normal P-channel MOSFET such as MOSFET Q22, that is, 2 times.
V _THP .

The bias voltage VB1 is supplied to the gate of the MOSFET Q20 from the bias circuit BC.
The gates of the OSFETs Q21 and Q68 are supplied with bias voltages VB2 and VB3, respectively. Also, MO
The SFETs Q22 and Q23 have their gates and drains commonly connected to form a diode, and
The drain potential of the FETs Q22 and Q68 that are commonly coupled is used as an output signal of the reference potential generation circuit VRGN, that is, the reference potential VRN, as a reference voltage generation circuit VLG
Supplied to

In the reference potential generation circuit VRGN, MO
The current available through SFETs Q20 and Q21 is M
Due to the current limiting action of OSFET Q68, MOSFET Q
22 and Q23. For this reason, MOS
The source / drain voltage of the FET Q22 is almost equal to its threshold voltage V _THP , and the source / drain voltage of the MOSFET Q23 is also almost equal to its threshold voltage 2V _THP . As a result, the drain voltage of MOSFET Q23, that is, the reference potential VRN becomes substantially + V _THP . In this embodiment, a P-channel MOS including a MOSFET Q23
Although the threshold voltage V _{THP of the} FET is not particularly limited,
It is about 0.9 V, and the reference potential VRN is about +0.9 V. However, in practice, since the threshold voltage V _THP fluctuates due to the manufacturing process or the like, the reference potential VRN, including the fluctuation ΔV _THP, is + V _THP ± ΔV _THP . That is, it is approximately +0.9 V ± ΔV _THP .

Similarly, reference potential generating circuit VRGB is not particularly limited, but includes three P-channel M-channel transistors provided in series between external power supply voltage VCC and the ground potential of the circuit.
OSFETs Q11 to Q13 and one N-channel MOS
FET Q66 and MOSFETs Q11-Q1
2 and two P-channel MOSFs provided in parallel with
ETQ13 and Q14 are included.

Here, the MOSFETs Q14 and Q15 are high threshold voltage type MOSFETs, and their threshold voltages are the same as those of the MOSFET Q23.
Normal P-channel MOSFET such as TQ11-Q13
_Is approximately twice the threshold voltage V _THP , ie, 2 V _THP . The bias voltage VB1 is supplied to the gate of the MOSFET Q11, and the bias voltage VB3 is supplied to the gate of the MOSFET Q66. The MOSFETs Q12 and Q13 and the MOSFETs Q14 and Q15 are in the form of diodes by having their gates and drains commonly connected. The drain potential of MOSFET Q11, that is, MO
As the source potential of the SFET Q12, the output signal of the reference voltage generation circuit VRGB, that is, the reference potential is supplied to the reference voltage generation circuit VLG as VRB.

In the reference voltage generating circuit VRGB, the MO
The current obtained through SFET Q66 is MOSFET
The MOSFETs Q12 and Q12
13 and MOSFETs Q14 and Q15. Therefore, the source and drain of MOSFE12 and Q13, the threshold voltage V _{TH P} substantially each
Thus, the source / drain voltages of the MOSFETs Q14 and Q15 are each approximately equal to the threshold voltage 2V _THP .

As a result, the drain voltage of MOSFET Q11, that is, reference potential VRB is substantially equal to VCC-V _THP.
Becomes In this embodiment, a P-channel MOSFE
As described above, the threshold value V _THP of T is set to about 0.9 V, and the reference potential VRN is set to about VCC-1.8 V. However, in practice, since the threshold voltage V _THP fluctuates due to a manufacturing process or the like, the reference potential VRB includes the fluctuation ΔV _THP and VCC-2 (V _THP ± ΔV _THP ), that is, about VCC− 1.8V ± 2ΔV _THP .

Next, the fuse circuit FC is not particularly limited, but as shown in FIG.
To PFS5, and six unit fuse circuits UFC0 to UFC5 and two decoder circuits DEC1
And DEC2.

Unit fuse circuit UF of fuse circuit FC
Although not limited, C0 to UFC5 are fuse means F1 selectively cut by, for example, a laser beam or the like, as shown by the unit fuse circuit UFC0.
including. One of these fuse means F1 is coupled to the external power supply voltage VCC via a P-channel MOSFET Q31 (pseudo cutting means), although not particularly limited.
The other end is coupled to the ground potential of the circuit via N-channel MOSFETs Q77 and Q78, and further coupled to the input terminal of inverter circuit N1.

The gate of MOSFET Q31 is coupled to the corresponding test pad PFS0 to PFS5, which is coupled to the ground potential of the circuit via a corresponding resistor R20. The external power supply voltage VCC is supplied to the gate of the MOSFET Q77.
The output signal of the corresponding inverter circuit N1 is supplied to each of the eight gates. Thereby, MOSFET Q77
Acts as a load MOSFET and MOSFET Q78
Operates as a feedback MOSFET transmitting the output signal of the inverter circuit N1 to its input terminal. Test pad P
Although not particularly limited, FS0 to PFS5 are normally opened and selectively coupled to the external power supply voltage VCC during a predetermined test operation.

After the output signal of the inverter circuit N1 is inverted by the inverter circuit N2, it becomes inverted output signals F0B to F5B of each unit fuse circuit. After these inverted output signals are further inverted by the inverter circuit N3, the non-inverted output signals F0 to F5 of each unit fuse circuit are output.
It is said. Complementary output signals F 0 to F 2 of the unit fuse circuits UFC0~UFC2 is supplied to the decoder DEC1,
Complementary output signal F of unit fuse circuits UFC3 to UFC5
. 3 to F 5 is supplied to the decoder circuit DEC2.

When the dynamic RAM is brought into a normal operation state and the test pads PFS0 to PFS5 are opened, the MOSFs of the unit fuse circuits UFC0 to UFC5 are opened.
The ETQ31 is turned on when the ground potential of the circuit is supplied via the corresponding resistor R20. At this time,
If the corresponding fuse means F1 is not blown, the input of the inverter circuit N1 is at a high level, so that the inverted output signal F0B of the unit fuse circuits UFC0 to UFC5.
To F5B become high level, and the non-inverted output signals F0 to F5
5 becomes low level. At this time, when the corresponding fuse means F1 is cut, the input of the inverter circuit N1 is at a low level, so that the inverted output signals F0B to G5B of the unit fuse circuits UFC0 to UFC5 are at a low level, and the non-inverted output signal is F0 to F5 become high level.

On the other hand, the dynamic RAM is brought into a predetermined test operation state, and the corresponding test pads PFS0 to PFS5
Is coupled to the external power supply voltage VCC, the MOSFET Q31 of the unit fuse circuits UFC0 to UFC5 is turned off. Therefore, the input of the inverter circuit N1 is forced to the low level regardless of the fuse means F1. For this reason, the unit fuse circuits UFC0 to UFC
5, the inverting output signals F0B to F5B are forced to be at a low level regardless of the corresponding fuse means F1, and the non-inverted output signals F0 to F5 are at a high level. That is, in the fuse circuit FC of this embodiment, the test pads PFS0 to PFSP
By coupling FS5 to the external power supply voltage VCC, it is possible to simulate the cutoff state of the fuse means F1 of the corresponding unit fuse circuits UFC0 to UFC5.

The decoder DEC1 of the fuse circuit FC is
Although not particularly limited, the eight NOR gate circuits NO1 to NO
O8. The first to third of these NOR gate circuits
Are connected to the unit fuse circuits UFC0 to UFC2.
, And non-inverted output signals F0 to F2 are supplied in a predetermined combination. The output signals of the NOR gate circuits NO1 to NO8 are connected to the fuse circuit FC.
, The internal region reference potential generation circuit VL of the reference potential generation circuit VLG as the internal output signal FN0 to FN7.
GN.

Thus, the internal signals FN0 to FN7 are
Fuse means F of unit fuse circuits UFC0 to UFC2
When 1 is set to the cut state or the pseudo cut state in a predetermined combination, it is alternatively set to the high level. That is, for example, when all of the fuse means F1 of the unit fuse circuits UFC0 to UFC2 are not in the cut state or the pseudo cut state,
The internal signal FN0 is alternatively set to a high level, and when all of these fuse means are in a cut state or a pseudo cut state, the internal signal FN7 is alternatively set to a high level.

Similarly, the decoder DE of the fuse circuit FC
C2 includes eight NOR gate circuits NO9 to NO16. The first to third input terminals of these NOR gate circuits are connected to inverted output signals F3B to F5B and non-inverted output signals F3 to F5 of unit fuse circuits UFC3 to UFC5, respectively.
5 are supplied in a predetermined combination. NOR gate circuit N
The output signals O9 to N16 are supplied as internal signals FB0 to FB7 to the burn-in area reference potential generation circuit VLGB of the reference potential generation circuit VLG. Thereby, the internal signals FB0 to FB7 are output from the unit fuse circuits UFC3 to UFC
When the five fuse means F1 are cut or pseudo cut in a corresponding combination, they are alternatively set to the high level.

The reference potential generating circuit VLG is not particularly limited, but as shown in FIG. 1, a normal region reference potential generating circuit VLGN (first reference potential generating circuit) and a burn-in region reference potential generating circuit VLGB (second reference potential generating circuit) and a reference potential switching circuit VLS.

Among them, the normal region reference potential generating circuit V
Although LGN is not particularly limited, a pair of differential MOSFETs
Operational amplifier circuit OA based on TQ55 and Q56
Including 1. The drains of these MOSFETs are coupled to an external power supply voltage VCC via a pair of P-channel MOSFETs Q7 and Q8, and their commonly coupled sources are coupled to the circuit ground via an N-channel MOSFET Q57.

The MOSFETs Q7 and Q8 are of a current mirror type, so that the differential MOSFETs Q55 and Q5
6, acting as an active load for the MOSFET
The Q57 acts as a constant current source when a predetermined constant voltage VS1 is supplied to its gate. MOSFET Q5
The gates of 5 and Q56 are respectively connected to the operational amplifier circuit OA1.
And the non-inverting input terminal + (second input terminal) of the MOSFETs Q7 and Q7.
55 are connected to the operational amplifier OA1.
Output terminal.

The reference potential VRN is supplied from the reference potential generation circuit VRG to the inverting input terminal of the operational amplifier circuit OA1, that is, the gate of the MOSFET Q55, and the output signal thereof, that is, the drain potential of the MOSFET Q7 and Q55 that are commonly coupled is P Channel type control MOSFET
It is supplied to the gate of TQ9. Control MOSFET Q9 has a source coupled to external power supply voltage VCC, and a drain coupled to output terminal VLN of reference potential generating circuit VLGN via P-channel MOSFET Q10 receiving at its gate an internal control signal TVLK. Output terminal V
Resistors R10 to R18 constituting a feedback circuit are provided in series between LN and the ground potential of the circuit.

The nodes commonly connected to these resistors are commonly connected to the non-inverting input terminal + of the operational amplifier OA1 via the feedback MOSFETs Q58 to Q65. The gates of the feedback MOSFETs Q58 to Q65 are supplied with the corresponding internal signal FN from the fuse circuit FC.
0 to FN7 are supplied. The potential of the output terminal VLN is used as the output signal of the normal region reference potential generation circuit VLGN, that is, the reference potential VLN (first reference potential), and as the output signal of the reference potential generation circuit VLG, that is, the reference potential VL. The voltage is supplied to the voltage generation circuit IVG. A smoothing capacitor C having a relatively large capacitance is provided between the output terminal VLN and the ground potential of the circuit.
2 are provided.

As described above, the internal signals FN0 to FN7
Are unit fuse circuits UFC0 to UFC of the fuse circuit FC.
When the fuse means F1 of FC2 is set to a cut state or a pseudo cut state in a predetermined combination, the fuse means F1 is alternatively set to a high level. At this time, the normal region reference potential generation circuit V
In the LGN, corresponding feedback MOSFETs Q58 to Q65
Are alternatively turned on. Therefore, the reference potential VLN
As shown in the equivalent circuit diagram of FIG. 2A, a feedback resistor RA consisting of a resistor on the output terminal VLN side with respect to the feedback MOSFET turned on and a feedback resistor RB consisting of a resistor on the ground potential side of the circuit, as shown in the equivalent circuit diagram of FIG. , And is fed back to the non-inverting input terminal + of the operational amplifier circuit OA1 as the internal potential VX.

As is well known, the output signal of the operational amplifier circuit OA1 is the non-inverted input signal +, that is, the internal potential VX.
Is higher than the inverted input signal −, that is, the reference voltage VRN, and is set to the low level in the opposite state. When the output signal of the operational amplifier circuit OA1 rises, the control MOS
The conductance of the FET Q9 is reduced, thereby lowering the reference potential VLN, that is, the internal potential VX.
On the other hand, when the output signal of the operational amplifier circuit OA1 is lowered,
The conductance of the control MOSFET Q9 is increased,
Thereby, reference potential VLN, that is, internal potential VX is increased. As a result, the operational amplifier circuit OA1 acts to make the non-inverted input signal +, ie, the internal potential VX, coincide with the inverted input signal −, ie, the reference potential VRN.

When the non-inverted input signal + of the operational amplifier circuit OA1 (ie, the internal potential VX) and its inverted input signal-, ie, the reference potential VRN, match, the internal potential VX becomes: VX = VRN = VLN × RB / (RA + RB) . Therefore, normal region reference potential generating circuit VL
The reference cage position VLN formed by G is VLN = VRN × (RA + RB) / RB = VRN × α. Needless to say, α is α = (RA + RB) / RB, and corresponds to the feedback rate to the operational amplifier circuit OA1.

In this embodiment, the feedback ratio α is not particularly limited, but is designed so that its center value is about 3.67. As described above, the reference potential VRN is approximately +0.9
V, the reference potential generating circuit VLGN for the normal region
, Ie, the center value of the reference position VLN is about +3.3.
V.

Here, the value of the reference potential VRN includes the variation ΔV _THP of the threshold voltage of the MOFET due to the manufacturing process, as described above, and the value of the reference potential VLN fluctuates accordingly. . In this case, the fuse circuit F
The fuse means F1 of the unit fuse circuits UFC0 to UFC2 of C is selectively cut off in a predetermined combination, and the corresponding feedback MOSFETs Q58 to Q65 are selectively turned on, thereby trimming the value of the reference potential VLN. , A desired value, that is, + 3.3V.

In the trimming process,
As described above, the fuse means F1 of the unit fuse circuits FC0 to FC2 of the fuse circuit FC can be in a pseudo cut state by supplying the external power supply voltage VCC to the corresponding test pads PFS0 to PFS2. As a result, a combination of fuse means F1 to be cut can be found without physically cutting fuse means F1, and trimming of reference potential VLN can be performed efficiently and accurately.

By the way, the normal region reference potential generating circuit V
LGN has an internal control signal TVLK at its gate between the control MOSFET Q9 and the output terminal VLN.
An OSFET Q10 is provided. This internal control signal TV
LK is not particularly limited, but is usually set to a low level.
When a test operation for evaluating an operation margin of a dynamic RAM is performed, an external power supply voltage VCC is selectively provided.
And a high level like When the dynamic RAM is set to the normal operation mode and the internal control signal TVLK is set to the low level, the reference potential generation circuit V for the normal region is used.
In the LGN, the MOSFET Q10 is turned on, and the control operation of the reference potential VLN as described above is performed. However, when a test operation for evaluating the operation margin of the dynamic RAM is performed and the internal control signal TVLK is set to the high level, the MOSFET Q10 is turned off, and the normal region reference potential generation circuit VLGN is substantially turned off. Stop operation.

The burn-in reference potential generation circuit VLGB of the reference potential generation circuit VLG is not particularly limited, but an operational amplifier circuit OA2 having P-channel type differential MOSFETs Q5 and Q6 as a basic configuration and an operational amplifier circuit O
N-channel type control MOSF receiving the output signal of A2
ETQ49 is included. The drain of control MOSFET Q49 is coupled to external power supply voltage VCC via series resistors R1 to R9 forming a feedback circuit together with N-channel MOSFETs Q41 to Q48.

The gates of the feedback MOSFETs Q41 to Q48 have corresponding internal signals FB from the fuse circuit FC.
0 to FB7 are supplied, and their commonly coupled sources are coupled to the non-inverting input terminal + of the operational amplifier circuit OA2, that is, the gate of the MOSFET Q6. The reference potential VRB is supplied from the reference potential generation circuit VRG to the inverting input terminal of the operational amplifier circuit OA2—that is, the gate of the MOSFET Q5. The drain potential of control MOSFET Q49 is an output signal of burn-in region reference potential generation circuit VLGB, that is, reference potential VRB.

As described above, the internal signals FB0 to FB7
Are unit fuse circuits UFC3 to UFC of the fuse circuit FC.
When the fuse means F1 of FC5 is set to a cut state or a pseudo cut state in a corresponding combination, the fuse means F1 is alternatively set to a high level. At this time, in the burn-in region reference potential generation circuit VLGB, the corresponding feedback MOSFETs Q41 to Q41 are connected.
Q48 is alternatively turned on. Therefore, the reference potential VLB is, as shown in the equivalent circuit diagram of FIG.
External power supply voltage VCC from MOSFET turned on
The voltage is divided by a feedback resistor RC composed of a resistor on the output side and a feedback resistor RD composed of a resistor on the output terminal VLB side, and is fed back as an internal potential VY to the non-inverting input terminal + of the operational amplifier circuit OA2.

As is well known, the output signal of the operational amplifier circuit OA2 is raised when its non-inverted input signal +, that is, the internal signal VY, is made higher than the inverted input signal-, ie, the reference potential VRB, and is made lower in the opposite state. When the output signal of the operational amplifier circuit OA2 is raised, the control MOSF
The conductance of the ETQ 49 is increased, thereby lowering the reference potential VLB, that is, the internal potential VY.
On the other hand, when the output signal of the operational amplifier circuit OA2 is lowered, the conductance of the control MOSFET Q43 is reduced, whereby the reference potential VLB, that is, the internal potential VLB is reduced.
Y is raised. As a result, the operational amplifier circuit OA2 acts to make the non-inverted output signal +, ie, the internal potential VY, coincide with the inverted input signal −, ie, the reference potential VRB.

When the non-inverted input signal + of the operational amplifier circuit OA2, ie, the internal potential VY, and its inverted input signal-, ie, the reference potential VRB, match, the internal potential VY is: VY = VRB = VLB + (VCC-VLB) × RD / (RC + RD). However, as described above, since the reference potential VRB is VRB = VCC-2V _THP , rearranging the above equation, VLB [1-RD / (RC + RD)] = VCC- [1-
RD / (RC + RD)]-2V _THP , so that VLB = VCC-2V _THP / [1-RD / (RC + RD)] = VCC-2V _THP × (RC + RD) / RC = VCC-2V _THP × β . Needless to say, β is β = (RC + RD) /
RC, which corresponds to the feedback ratio for the operational amplifier circuit OA2.

In this embodiment, the feedback rate β is not particularly limited, but is designed so that its center value is about 1.5. As described above, since the threshold voltage V _THP of the P-channel MOSFET is about 0.9 V, the output signal of the burn-in region reference potential generation circuit VLGB, that is, the center value of the reference potential VLN is VCC-2.7 V. , Are increased in proportion to the value of the external power supply voltage VCC.

Here, the value of the reference potential VRB includes the variation ΔV _THP of the threshold voltage of the MOSFET due to the manufacturing process, as described above, and VRB = VCC−2 (V _THP ± ΔV _THP ). Is done. Therefore, the value of the reference potential VLB fluctuates with this fluctuation ΔV _THP . In this case, the unit fuse circuits UFC3 to UFC5 of the fuse circuit FC
Of the fuse means F1 is selectively cut or pseudo-cut in a predetermined combination, and the corresponding feedback MOSFET
By selectively turning on Q41 to Q48, the value of the reference potential VLB is trimmed, and a predetermined value VCC is selected.
-2.7V can be set.

The reference potential switching circuit VLS of the reference potential generating circuit VLG includes, but is not limited to, a pair of N-channel MOSFETs Q50 and Q51 in a differential form. The drains of these differential MOSFETs are connected to a pair of P-channel MOSFETs Q1
And Q2 to the external power supply voltage VCC, and between its common coupled source and the ground potential of the circuit, N
A constant current source including a channel MOSFET Q52 is provided. The output signal of the burn-in region reference potential generating circuit VLGB, that is, the reference potential VLB is supplied to the gate of the MOSFET Q50.
The output signal of the normal region reference potential generation circuit VLGN, that is, the reference potential VLN, that is, the reference potential VL, is supplied to the gates of the gates.

The external power supply voltage VCC and the MOSFET Q5
A P-channel type control MOSFET Q3 is provided between one gate, that is, the output terminal VL. The gate of the control MOSFET Q3 is connected to the MOSFET Q5.
A drain potential of 0 is supplied. Thereby, MOSF
The differential circuit having the basic configuration of ETQ50 and Q51 acts as a comparison circuit for comparing the levels of the reference potentials VLB and VLN, and the control MOSFET Q3 is paraphrased on the condition that the output signal of the comparison circuit is at a low level. Then, on the condition that the level of reference potential VLB is higher than reference potential VLN, control MOS for reference potential VL
Acts selectively as an FET.

That is, the reference potential VLB is changed to the reference potential VL.
When the voltage is lower than N, the output signal of the comparison circuit including the MOSFETs Q50 and Q51 becomes a high level like the external power supply voltage VCC. Therefore, the MOSFET Q3 is turned off and does not act as a control MOSFET. On the other hand, when the reference potential VLB becomes higher than the reference potential VLN,
The output signal of the comparison circuit has a low level according to the reference potential VLB. Therefore, the MOSFET Q3 is turned on, and acts as a control MOSFET for the reference potential VL. As described above, the value of reference potential level VLB is increased in proportion to external power supply voltage VCC.

As a result, when the value of external power supply voltage VCC is equal to or lower than a predetermined value, that is, when external power supply voltage VCC is set to the first region, reference potential VL of normal region reference potential generation circuit VLGN Output signal, that is, reference potential VL
N, when external power supply voltage VCC is equal to or higher than a predetermined value, that is, when external power supply voltage VCC is in the second region, it changes according to the output signal of burn-in region reference potential generation circuit VLGB, that is, reference potential VLB. Will be done. As described above, the output signal of the reference potential generation circuit VLG, that is, the reference potential VL is output from the internal power supply voltage generation circuit IV.
G.

Internal power supply voltage generating circuit IVG includes, but is not limited to, two internal power supply voltage generating circuits IVG1 and IVG2, as shown in FIG. Although not particularly limited, smoothing capacitors C3 and C4 and a resistor R19 are provided between the commonly coupled output terminals of these internal power supply voltage generating circuits and the ground potential of the circuit.

The internal power supply voltage generating circuit IVG1 is not particularly limited, but may be an N-channel type differential MOSFET Q6.
9 and an operational amplifier circuit OA3 having Q70 as a basic configuration. The drains of the differential MOSFETs Q69 and Q70 are connected to P-channel MOSFETs Q as active loads.
24 and Q25 to an external power supply voltage VCC, and the common coupled source is an N-channel MOS
It is coupled to the ground potential of the circuit via FET Q71. M
The gate of the OSFET Q71 has a timing generation circuit T
G supplies a timing signal φvc. As described above, the timing signal φvc is selectively set to the high level while the dynamic RAM is in the selected state. As a result, the operational amplifier circuit OA3 becomes a dynamic RA
M is set to the selected state, and the timing signal φvc is set to the high level, thereby selectively setting the operation state.

The reference potential V is applied to the inverting input terminal of the operational amplifier circuit OA3, that is, the gate of the MOSFET Q69.
L is supplied. The output signal of the operational amplifier circuit OA3 is supplied to the gate of a P-channel type control MOSFET Q27 provided between the external power supply voltage VCC and its non-inverting input terminal +, that is, the gate of the MOSFET Q70. Here, control MOSFET Q27 is designed to wait for a relatively large conductance. Control MOS
The drain of the FET Q27 has an N-channel MOSFET Q72 receiving the timing signal φvc at its gate.
, And to the output terminal of the internal power supply voltage generating circuit IVG, that is, to the internal power supply voltage supply point VCL. Further, the external power supply voltage VC
Between C and the gate of the control MOSFET Q27, a P-channel MOSFET Q26 receiving the timing signal φvc at its gate is provided.

From these facts, the internal power supply voltage generation circuit IVG1 is selectively set to the dynamic RAM, and is selectively activated by the timing signal φvc being set to the high level. It acts to match the level of VCL with the reference potential VL. At this time, the current supply capability of internal power supply voltage generation circuit IVG1 is relatively increased by increasing the conductance of control MOSFET Q27. The dynamic RAM is set to the non-selected state, and the timing signal φ
When vc is set to low level, the operation of internal power supply voltage generation circuit IVG1 is stopped.

On the other hand, internal power supply voltage generation circuit IVG2
Although not particularly limited, an N-channel type differential MOSFE
Operational amplifier circuit OA based on TQ73 and Q74
4 inclusive. These differential MOSFETs Q73 and Q74
Is a P-channel MO that is an active load
External power supply voltage VCC through SFETs Q28 and Q29
, The common coupled source of which is coupled to the circuit ground via an N-channel MOSFET Q74. The external power supply voltage VCC is supplied to the gate of the MOSFET Q75, whereby the operational amplifier circuit OA4 is always operated.

The inverting input terminal of the operational amplifier circuit OA4, that is, the gate of the MOSFET Q73 is connected to the reference potential V.
L is supplied. The output signal of the operational amplifier OA4 is supplied to the gate of a P-channel type control MOSFET Q30 provided between the external power supply voltage VCC and its non-inverting input terminal +, that is, the gate of the MOSFET Q74. Here, control MOSFET Q30 is designed to have a relatively small conductance. Control MOS
The drain of FET Q30 is coupled to the ground potential of the circuit via an N-channel MOSFET Q76 receiving the external power supply voltage VCC at its gate, and to the internal power supply voltage supply point VCL.

From these, the internal power supply voltage generation circuit IVG2 is always in operation regardless of the selected state of the dynamic RAM, and its output signal, that is, the level of the internal power supply voltage VCL is made equal to the reference potential VL. Works. At this time, the internal power supply voltage generation circuit lVG2
Is relatively reduced by reducing the conductance of the control MOSFET Q30. As a result, the current supply capability of the entire internal power supply voltage generation circuit IVG is increased when the dynamic RAM is in the selected state, and is reduced to a necessary minimum when the dynamic RAM is in the non-selected state.

By the way, the reference potential VL supplied from the reference potential generating circuit VLG is stabilized to the reference potential VLN, that is, +3.3 V when the external power supply voltage VCC is lower than the predetermined value, as described above. When the power supply voltage VCC is equal to or higher than a predetermined value, the power supply voltage is increased in proportion to the external power supply voltage VCC.

However, as shown in the output characteristic diagram of FIG. 3, the center value of internal power supply voltage VCL is determined when external power supply voltage VCC is lower than a predetermined value, in other words, when external power supply voltage VCC is in normal region NM. (The first region), the voltage is fixed to VCLN, that is, +3.3 V, and when the external power supply voltage VCC is equal to or higher than a predetermined value, in other words, the external power supply voltage VCC is in the burn-in region BT (the second region). At some point, VCL = VCC-VS = VCC-2V _THP × β = VCC-2.7, which is increased in proportion to the external power supply voltage VCC.

Further, the dynamic RA of this embodiment
In M, the reference potential VL in the burn-in area, that is, V
As described above, the LB is trimmed by selectively setting the fuse means F1 of the unit fuse circuits UFC3 to UFC5 of the fuse circuit FC to a cut state or a pseudo cut state. Therefore, the value of internal power supply voltage VCL in burn-in region BT is close to the above-mentioned center value despite that threshold voltage V _THP of P-channel MOSFET determining reference potential VRB varies according to the manufacturing process or the like. , As shown by the solid line in FIG.

Thus, the value of internal power supply voltage VCL during the burn-in test can be set to a value sufficiently close to desired voltage VCLB. As a result, the error detection rate of the burn-in test, that is, the screening accuracy is improved, the reliability of the dynamic RAM is improved, and the damage of normal circuit elements due to so-called overkill is reduced, and the yield of the dynamic RAM is improved. .

As shown in the present embodiment, by applying the present invention to a semiconductor integrated circuit device such as a dynamic RAM having a built-in voltage conversion circuit, the following effects can be obtained. That is,

(1) A voltage conversion circuit having a so-called burn-in area built in a dynamic RAM or the like and whose output voltage, that is, an internal power supply voltage is increased in proportion to an external power supply voltage during a burn-in test, is cut in a predetermined combination. By providing fuse means capable of selectively switching the value of the internal power supply voltage, the value of the internal power supply voltage in the burn-in area can be trimmed, and the effect of suppressing fluctuations due to manufacturing variations or the like can be obtained.

(2) According to the above item (1), an effect is obtained that the error detection rate of the burn-in test can be increased and the screening accuracy can be increased.

(3) According to the above item (1), there is obtained an effect that damage to normal circuit elements due to so-called overkill can be reduced and the yield of a dynamic RAM or the like can be increased.

(4) In the above items (1) to (3),
By providing another fuse means that can selectively switch the value of the internal power supply voltage during normal operation by being cut in a predetermined combination, the value of the internal power supply voltage in a so-called normal region is trimmed, and manufacturing variations and the like are provided. The effect that the fluctuation | variation by this can be suppressed is acquired.

(5) According to the above item (4), the effect that the operation of the dynamic RAM in the normal operation mode can be stabilized can be obtained.

(6) In the above items (1) to (5),
By providing a pseudo cutting means such as a MOSFET which is selectively turned off in accordance with a predetermined test control signal in series with the fuse means, the trimming fuse means can be set to a pseudo cutting and cutting state. An effect is obtained in that the combination of fuse means to be determined is determined and checked in advance, and the trimming accuracy can be improved.

(7) According to the above item (6), an effect that the internal power supply voltage and the like can be trimmed without physically cutting the fuse means can be obtained.

(8) In the above items (1) to (7),
When a test operation or the like for evaluating the operation margin of a dynamic RAM or the like is performed, the value of the internal power supply voltage in the normal region can be increased in proportion to the external power supply voltage, so that the operation margin during the operation margin evaluation can be improved. The effect is obtained that the value of the internal power supply voltage can be set according to the external power supply voltage.

(9) In the above items (1) to (8),
A dynamic RAM or a MOSFET which is selectively turned on when a predetermined test mode is set is provided between the internal power supply voltage supply and a predetermined external terminal. The effect that the value of the internal power supply voltage can be monitored via the.

(10) According to the above items (6) to (9), the effect of increasing the efficiency of the test operation of the dynamic RAM or the like and reducing the number of test steps can be obtained.

(11) According to the above items (1) to (10), an effect is obtained that the cost of the dynamic RAM can be promoted while improving the reliability thereof.

The invention made by the inventor has been specifically described based on the embodiments. However, the invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example,
In FIG. 1, the number of MOSFETs and resistors constituting the feedback circuit of each reference potential generating circuit, that is, the internal power supply voltage VC
The number of L trimming steps can be set arbitrarily.

Means for trimming the reference potentials VLN, VLB and VL can be considered by various methods, and these reference potentials and reference potentials VRN and VR can be used.
Specific values such as B are arbitrary. In FIG. 3, the voltage conversion circuit VC can have output characteristics as shown in, for example, FIG. 4 or FIG. That is, in the case of FIG. 4, the internal power supply voltage VCL gradually increases in the normal region NM in proportion to the external power supply voltage VCC.

In the case of FIG. 5, the internal power supply voltage VCL
Is increased in proportion to external power supply voltage VCC at the same ratio as in burn-in region BT also in normal region NM.
In any case, the value of the internal power supply voltage VCL in the burn-in region BT is trimmed by, for example, selectively cutting the fuse means, and fluctuations due to manufacturing variations or the like are suppressed. In FIG. 7, the number of fuse means provided in the fuse circuit FC is arbitrary, and various embodiments may be considered for a method of identifying the cutting state and a decoding method.

When the number of trimming steps of the reference potential is very large and the number of the fuse means is large, the fuse circuit FC can take a modified example as shown in FIG. That is, in FIG. 11, the fuse circuit FC includes a fuse circuit FCN corresponding to the normal region and including n unit fuse circuits, and a fuse circuit FC corresponding to the burn-in region and including n unit fuse circuits.
B, and these fuse circuits FCN and FN
N-bit counter circuit CT provided corresponding to CB
RN and CTRB.

A reset signal RST and a count-up pulse CU are commonly supplied to these counter circuits.
Enable signals TEN and TEB are supplied, respectively. These counter circuits selectively perform a step-up operation by the count-up pulse CU when the corresponding enable signal TEN or TEB is set to a high level, and output signals thereof, that is, internal signals CN0 to CNn-1 or CB0. To CBn-1 are valid. As a result, it is possible to realize a pseudo cut state of the fuse means of the fuse circuit FCN or FCB in various combinations without providing a large number of test pads corresponding to each unit fuse circuit.

In FIG. 8, internal power supply voltage generating circuit IV
G does not need to include a plurality of internal power supply voltage generating circuits having different current supply capacities, and selectively supplies them according to a predetermined timing signal. There is no need to bring it into operation. In FIG. 9, the external power supply voltage VCC is particularly the voltage conversion circuit VC.
Need not be supplied to circuits other than the external power supply voltage V
Specific values of CC and the internal power supply voltage VCL are also arbitrary. In addition, the dynamic RAM can include, for example, a plurality of similar voltage conversion circuits having different output voltages.

In FIG. 10, a dynamic RAM
May have a plurality of memory mats, or may adopt a so-called multi-bit configuration for simultaneously inputting / outputting a plurality of bits of storage data. In addition, the dynamic RAM does not require a shared sense system and an address multiplex system. The external terminal for monitoring the internal power supply voltage VCL may be the data input terminal Din or the address input terminals A0 to Ai.
May be any of

Further, reference potential generating circuit VLG and reference potential generating circuit VR shown in FIG. 1 and FIGS.
G, the fuse circuit FC, and the specific circuit configuration of the internal voltage generation circuit IVG, the block configuration of the voltage conversion circuit VC and the dynamic RAM shown in FIGS. 9 and 10, and control signals, address signals, and power supply voltages. Combination and the like can take various embodiments.

In the above description, the case where the invention made by the present inventor is mainly applied to a dynamic RAM, which is the field of application, has been described. However, the present invention is not limited to this. The present invention can also be applied to various semiconductor memory devices and logic integrated circuit devices such as gate array integrated circuits. Further, the invention in which the fuse means is set to a pseudo-cut state is provided with various types of semiconductor memory devices including a fuse means for selectively switching a defective element to a redundant circuit and a fuse means for trimming another circuit constant. The present invention can also be applied to a logic integrated circuit device and the like. The present invention can be widely applied to at least a semiconductor integrated circuit device having a built-in voltage conversion circuit or having a fuse means.

[0110]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, a predetermined combination is cut into a voltage conversion circuit having a so-called burn-in region which is built in a dynamic RAM or the like and whose output voltage, that is, an internal power supply voltage is changed in proportion to an external power supply voltage during an accelerated test operation. Thus, fuse means capable of selectively switching the value of the internal power supply voltage in the burn-in region is provided.

Further, a pseudo disconnecting means capable of pseudo-cutting these fuse means is provided, and the value of the internal power supply voltage can be monitored via a predetermined external terminal. This makes it possible to efficiently trim the value of the internal power supply voltage in the burn-in area, suppress fluctuations due to manufacturing variations and the like, and increase the screening accuracy of the burn-in test. In addition, damage to normal circuit elements due to so-called overkill is reduced, and dynamic RA
The yield of M and the like can be increased. As a result, cost reduction can be promoted while improving the reliability of the dynamic RAM and the like.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a reference potential generation circuit included in a voltage conversion circuit of a dynamic RAM to which the present invention is applied.

FIG. 2 is a partial equivalent circuit diagram showing one example of a reference potential generation circuit of FIG. 1;

FIG. 3 is an output characteristic diagram showing a first embodiment of the voltage conversion circuit including the reference potential generation circuit of FIG. 1;

FIG. 4 is an output characteristic diagram showing a second embodiment of the voltage conversion circuit including the reference potential generation circuit of FIG. 1;

FIG. 5 is an output characteristic diagram showing a third embodiment of the voltage conversion circuit including the reference potential generation circuit of FIG. 1;

FIG. 6 is a circuit diagram showing an embodiment of a reference potential generation circuit included in a voltage conversion circuit of a dynamic RAM to which the present invention is applied.

FIG. 7 is a circuit diagram showing one embodiment of a fuse circuit included in a voltage conversion circuit of a dynamic RAM to which the present invention is applied.

FIG. 8 is a circuit diagram showing one embodiment of an internal voltage generation circuit included in a voltage conversion circuit of a dynamic RAM to which the present invention is applied.

FIG. 9 is a block diagram showing one embodiment of a voltage conversion circuit of a dynamic RAM to which the present invention is applied.

FIG. 10 shows a dynamic RAM to which the present invention is applied.
FIG. 3 is a block diagram showing one embodiment of the present invention.

FIG. 11 is a dynamic RAM to which the present invention is applied;
FIG. 10 is a block diagram showing another embodiment of the fuse circuit included in the voltage conversion circuit of FIG.

[Explanation of symbols]

VLG: Reference potential generation circuit, VLGN: Reference potential generation circuit for normal area, VLGB: Reference potential generation circuit for burn-in area, VLS: Reference potential switching circuit, Q1 to Q3: P channel MOSFET, Q4
1 to Q79: N-channel MOSFET, C1 to C
4 ... Capacitor, R1 to R20 ... Resistance. OA1
OA4: operational amplifier circuit, RA to RD: feedback resistor. VRG: Reference potential generation circuit, BC: Bias circuit, VRGN: Normal region reference potential generation circuit,
VRGB: Reference potential generation circuit for burn-in area. FC
... Fuse circuit, UFC0 to UFC5 ... Unit fuse circuit, DEC1 to DEC2 ... Decoder, F1
... fuse means, N1 to N3 ... inverter circuits, NO1 to NO16 ... NOR gate circuits. IVG,
IVG1 to IVG2 ... internal power supply voltage generation circuits. VC
... voltage conversion circuit. DRAM: Dynamic R
AM, MARYL, MARYR ... memory array, S
A: sense amplifier, RADL, RADR: row address decog, RAB: row address buffer, RFC: refresh address counter, CA
D: column address decoder, CAB: column address buffer, MA: main amplifier, DIB
.. A data input buffer, DOB... A data output buffer, and TG a timing generation circuit. FCN, FCB
... Fuse circuit, CTRN, CTRB ... Counter circuit.

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Manabu Tsunozaki 2326 Imai, Ome-shi, Tokyo Nichi Works, Ltd.Device Development Center (72) Inventor Kazuyoshi Oshima 2326 Imai, Ome-shi, Tokyo Nichi Works Inside the Device Development Center (56) References JP-A-3-22300 (JP, A) JP-A-3-15797 (JP, A) JP-A-3-181100 (JP, A) JP-A-59-124098 (JP) , A) JP-A-59-121854 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 29/00 671 G11C 11/401

Claims (5)

(57) [Claims] 1. A fuse circuit for storing predetermined information in a fuse means according to an initial state and a program state, and a voltage conversion circuit for receiving an operating voltage and converting it to an internal voltage.
Comprising, the fuse circuit, the fuse means have a means for the program state the fuse unit in a pseudo manner when in the initial state, set between the voltage conversion circuit, the resistor element and a switching element
The above internal voltage is determined by the resistance ratio set by the combination.
And a negative feedback amplifier circuit formed by the fuse circuit.
The internal voltage is adjusted by switch control of a switch element .
The semiconductor integrated circuit device, characterized in that that. 2. The fuse unit according to claim 1, wherein the first node and the second node are turned on in the initial state, and the first node and the second node are turned off in the program state. The means for pseudo-programming is a transistor in which a source-drain path is connected to the first node, and a control signal is input to a gate of the transistor to make the transistor non-conductive. A semiconductor integrated circuit device which is set to the program state without cutting the fuse means. 3. The semiconductor device according to claim 2 , wherein the control signal indicates that the semiconductor integrated circuit device performs a test operation.
Operate the transistor selectively
A semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1 , wherein said semiconductor integrated circuit device is a dynamic random access memory.
Semiconductor integrated circuit characterized by being access memory
Road equipment. 5. The device according to claim 1, wherein the means for pseudo-programming is provided by an external device.
Characterized by being connected to a test pad installed in
Semiconductor integrated circuit device.