JP3352626B2 - High frequency semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-frequency semiconductor device, and more particularly to a high-frequency semiconductor device having a uniplanar line and a method of manufacturing the same.

[0002]

2. Description of the Related Art In the coming 21st century, the infrastructure for information communication such as optical fiber communication networks will be enhanced,
It is expected that an advanced information society will come. In such a society, demand for mobile communication terminals typified by mobile phones is expected to further increase, and higher-speed, higher-capacity communication services such as outdoor data communication and moving image communication will be required. The current frequency band is depleted of frequency resources, and such services cannot be realized. Therefore, it is necessary to increase the frequency band to be used and shift to a millimeter-wave band whose use is currently limited.

Since the wavelength of an electromagnetic wave is shortened by such a high frequency, a line length shorter than that of a conventional high frequency device is required. Conversely, if a circuit is configured with the conventional line length, the transmission loss increases, and the characteristics of the circuit deteriorate. Therefore, the use of a higher frequency inevitably involves downsizing of a circuit, and it is necessary to form a monolithic IC in which active elements and passive elements are integrated on one substrate.

[0004] Gallium arsenide (GaAs) used for the substrate of this monolithic IC has a resistivity (ρ = 10 ⁷ Ωcm) that is approximately 2000 times higher than that of silicon (Si). A transmission line with less loss is possible. This feature, combined with the excellent high-frequency characteristics of GaAs-based devices, leads to the realization of a monolithic microwave integrated circuit (MMIC).

[0005] High-frequency transmission lines used in MMICs are roughly classified into biplanar lines and uniplanar lines. Hereinafter, a biplanar type line and a uniplanar line will be described with reference to the drawings. FIG. 14 (a)
FIG. 14 shows a cross-sectional structure of a conventional biplanar line represented by a microstrip line, and FIG. 14B shows a cross-sectional structure of a uniplanar line represented by a coplanar line. As shown in FIG. 14A, the microstrip line includes a signal line 102A formed on a main surface of a GaAs substrate 101 and a ground plane 103A formed on a surface opposite to the main surface. Have been. The signal line 102A and the ground plane 103A are grounded via via holes 104 selectively provided in the substrate 101. On the other hand, as shown in FIG. 14B, the coplanar line is formed on the main surface of the substrate 101, and the signal line 1
02B, a pair of ground lines 103B spaced at a predetermined interval from both sides of the signal line 102B.

In order to form a so-called 50Ω line having an impedance required for circuit design of 50Ω from the microstrip line shown in FIG. 14A, it is necessary to polish the substrate 101 to a thickness of about 200 μm to 150 μm. . Like the microstrip line, the biplanar type line has a via hole 10 separately from the formation of the active element.
An additional step of forming the substrate 4 and thinning the substrate is required, which leads to a decrease in yield and an increase in cost.

On the other hand, the coplanar line shown in FIG. 14B does not require a via hole since the signal line 102B and the ground line pair 103B are formed on the same surface, and furthermore, the impedance is reduced by the signal line 102B and the ground line pair 103B. Therefore, the substrate 101 need not be polished. As a result, the MMIC can be reduced in cost without requiring an additional step for circuit formation.

[0008]

However, when the conventional coplanar line is compared with a microstrip line having the same signal line width, the electromagnetic wave propagates as shown in FIGS. 14A and 14B. In general, transmission loss increases due to the small area. To achieve low loss equivalent to a microstrip line, it is necessary to increase the width of the signal line 102B, resulting in an increase in circuit area. This leads to a reduction in the number of chips per slice (= wafer), which has the problem of offsetting the superiority in manufacturing cost of the coplanar line.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems and to reduce transmission loss in a uniplanar line.

[0010]

To achieve the above object, a high-frequency semiconductor device according to the present invention comprises a high dielectric layer and a uniplanar line formed on the high dielectric layer.

According to the high frequency semiconductor device of the present invention, since the uniplanar line is formed on the high dielectric layer,
Since the electric lines of force between the signal line and the ground line are concentrated below the uniplanar line, the capacity between the lines increases,
As a result, the value of the dielectric loss tangent, which is inversely proportional to the dielectric constant, decreases.

In the high frequency semiconductor device of the present invention, it is preferable that the high dielectric layer is formed on a high resistance substrate. By doing so, a high-frequency semiconductor device can be reliably obtained.

In the high frequency semiconductor device according to the present invention, the high resistance substrate is preferably made of gallium arsenide or glass.

It is preferable that the high-frequency semiconductor device of the present invention further includes an insulating film provided between the high dielectric layer and the uniplanar line. In this case, the conductivity between the signal line and the ground line is reduced by the insulating film provided between the high dielectric layer and the uniplanar line, so that the value of the dielectric loss tangent that is directly proportional to the conductivity is reduced.

In the high-frequency semiconductor device according to the present invention, the uniplanar line is composed of a plurality of conductor films each provided at a distance from each other, and is provided between at least a plurality of conductor films and is made of a high dielectric material. Preferably, it further comprises a layer. In this case, since the high dielectric substance is interposed not only below the uniplanar line but also between the side portions between the lines, the electric lines of force between the lines are further concentrated, so that the signal line of the uniplanar line and the ground The capacitance between the lines is further increased.

In the high-frequency semiconductor device according to the present invention, the uniplanar line is composed of a plurality of conductor films each provided at an interval from each other, and the high dielectric layer is formed between the plurality of conductor films along the uniplanar line. It is preferable to have a groove for dividing the high dielectric layer. By doing so, the region between the plurality of conductor films in the high dielectric layer becomes discontinuous, so that the conductivity between the signal line and the ground line decreases.

In the high-frequency semiconductor device according to the present invention, it is preferable that a groove of the high dielectric layer is filled with a high-resistance dielectric. By doing so, the dielectric constant of the groove becomes higher than that of air, so that the capacitance between the signal lines and the ground line can be increased while the conductivity between the lines is reduced.

In the high-frequency semiconductor device of the present invention, the high-resistance dielectric is preferably silicon nitride.

In the high frequency semiconductor device of the present invention, the high dielectric layer is made of Ba _x Sr _{1 -x} TiO ₃ (where x is 0 ≦ x)
≦ 1. _{), Pb x La y Zr 1} -xy TiO 3 ( where, x, y is set to 0 ≦ x + y ≦ 1. ) Or Ta ₂ O ₅
It preferably comprises

In the high-frequency semiconductor device according to the present invention, the uniplanar line is a coplanar line comprising a signal line and a pair of ground lines spaced at predetermined intervals from both sides of the signal line.
Alternatively, a slot line formed of a pair of conductor films spaced at a predetermined interval is preferable.

In the method of manufacturing a high-frequency semiconductor device according to the present invention, a first step of forming a high-dielectric layer on a high-resistance substrate and a second step of forming a metal thin film on the high-dielectric layer are provided.
A third step of performing a heat treatment on the high-resistance substrate on which the thin film is formed so that the high-dielectric layer is recrystallized; and a fourth step of patterning the conductive film to be a uniplanar line. Steps.

According to the method of manufacturing a high-frequency semiconductor device of the present invention, the heat treatment for recrystallizing the high dielectric is performed while the thin film made of a metal having an excellent affinity for the high dielectric covers the high dielectric layer. Since the high dielectric layer is covered with the metal thin film, recrystallization of the high dielectric can be performed efficiently, and as a result, a desired dielectric constant for the high dielectric can be realized. Further, since the high dielectric layer is covered with the metal thin film having an excellent affinity, peeling of the high dielectric layer from the high resistance substrate after the heat treatment hardly occurs.

[0023]

(First Embodiment) A first embodiment of the present invention.
An embodiment will be described with reference to the drawings.

FIG. 1 shows a cross-sectional structure of a high-frequency semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, strontium titanate (SrTiO ₃ ) having a thickness of 1 μm is formed on a main surface of a substrate 11 made of semi-insulating GaAs.
, A 50 nm thick platinum (Pt) and a 1 μm thick gold (Au) are laminated, and a predetermined interval is provided between the signal line 13a and both sides of the signal line 13a. Coplanar line 1 composed of ground line pair 13b
3 are formed. Although only the coplanar line 13 is shown in FIG. 1, it is assumed that an active element such as a high-frequency transistor or a passive element such as a capacitor is formed on the substrate 11.

(First Manufacturing Method of First Embodiment) A first manufacturing method of the high-frequency semiconductor device configured as described above will be described below with reference to the drawings.

FIGS. 2A to 2D show cross-sectional structures in the order of steps of a first method for manufacturing a high-frequency semiconductor device according to the present embodiment. First, as shown in FIG. 2A, the substrate 11 made of semi-insulating GaAs is heated so that the substrate temperature becomes 300 ° C., and the substrate 11 is formed on the main surface of the substrate 11 by, for example, RF sputtering. After depositing SrTiO ₃ , a heat treatment at a temperature of 450 ° C. is performed in an oxygen atmosphere to form a high dielectric layer 12 made of SrTiO ₃ .
By this heat treatment, SrTiO ₃ is recrystallized in the high dielectric layer 12 so that the crystal orientation becomes uniform, so that a high dielectric constant can be realized.

Next, as shown in FIG. 2B, a resist pattern 15 having an opening serving as a line pattern is formed on the high dielectric film 12 by using a photolithography method. As shown in FIG. 2C, a wiring metal film 13A is deposited so as to form a Pt / Au laminate. Thereafter, as shown in FIG.
Is lifted off to form a coplanar line 13 composed of the wiring metal film 13A, and composed of the signal line 13a and a pair of ground lines 13b spaced apart from both sides of the signal line 13a by a predetermined distance.

FIG. 3A schematically shows the distribution of electric lines of force of the coplanar line 13 according to the present embodiment. In FIG. 3A, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. As shown in FIG. 3A, electric lines of force generated between the signal line 13a and the ground line pair 13b in the coplanar line 13 are high dielectric layers 12 having a high relative dielectric constant (in the case of SrTiO ₃ , the relative dielectric constant is high). Are concentrated in 200), and furthermore, according to Snell's law, the lines of electric force form a high dielectric layer 1 having a high relative dielectric constant.
Since the light is refracted from the second side toward the substrate 11 having a lower relative dielectric constant (in the case of GaAs, the relative dielectric constant is 12.7), the lines of electric force in the substrate 11 are sparse.

As described above, since the electromagnetic wave propagating through the coplanar line 13 is strongly affected by the high dielectric layer 12 located around the coplanar line 13, the inter-line capacitance in the transmission line theory increases. That is, FIG.
And the value of the inter-line capacitance 16 shown in the equivalent circuit diagram based on the transmission line theory of FIG.

More specifically, the dielectric loss derived from the transmission line theory is represented by the following equation (1): dielectric loss tangent tan δ = σ / ωε (1) (where σ is the substrate 11 , Ω represents the angular frequency, and ε represents the dielectric constant of the substrate 11).

Accordingly, the value of the dielectric loss tangent is determined by the dielectric constant ε of the denominator.
Is reduced due to the high dielectric constant of the high dielectric layer 12, so that the dielectric loss is reduced. As a result, the attenuation constant (power loss) represented by the sum of the dielectric loss and the conductor loss of the line is reduced.

(Second Manufacturing Method of First Embodiment) Hereinafter, a second manufacturing method of the high-frequency semiconductor device configured as described above will be described with reference to the drawings.

FIGS. 4A to 4E show cross-sectional structures in the order of steps of a second method of manufacturing the high-frequency semiconductor device according to the present embodiment. First, as shown in FIG. 4A, the substrate 11 made of semi-insulating GaAs is heated so that the substrate temperature becomes 300 ° C., and the substrate 11 is heated on the main surface of the substrate 11 by, for example, RF sputtering. High dielectric layer 1 made of SrTiO ₃
2 is deposited.

Next, as shown in FIG. 4B, a wiring metal film 13B is deposited on the high dielectric layer 12 so as to form a Pt / Au laminate, and then the temperature is reduced in an oxygen atmosphere. 450
The heat treatment of ° C is performed. Thereby, the high dielectric layer 12 becomes S
Since rTiO ₃ is recrystallized and the crystal orientation is aligned, a high dielectric constant can be realized.

Next, as shown in FIG. 4C, a resist pattern 17 for masking the line pattern is formed on the high dielectric film 12 by photolithography, and the resist pattern 17 is used as a mask. Metal thin film for wiring 1
By milling 3B with argon (Ar), it is composed of a wiring metal film 13B, and is composed of a signal line 13a and a pair of ground lines 13b spaced at predetermined intervals from both sides of the signal line 13a. A coplanar line 13 is formed.

When SrTiO ₃ is used for the high dielectric layer 12, since SrTiO ₃ has a relatively low affinity for GaAs of the substrate 11, if SrTiO ₃ is directly deposited on the substrate 11,
The effect of the heat treatment for recrystallization is reduced, and in the worst case, the high dielectric layer 12 is separated from the substrate 11.

[0037] However, in the second manufacturing method according to the present embodiment, to perform the heat treatment after affinity with SrTiO ₃ is deposited a relatively high Pt metal on the top surface of the high dielectric layer 12, SrTiO ₃ Can be effectively recrystallized, so that a high dielectric layer 12 having a desired high dielectric constant can be realized, and as a result, the high dielectric layer 12 hardly peels off from the substrate 11.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 5 shows a cross-sectional configuration of a high-frequency semiconductor device according to a second embodiment of the present invention. 5, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. This embodiment, co
High dielectric layer 1 made of planar line 13 and SrTiO ₃
2, silicon nitride (Si) having a thickness of 200 nm
N) is provided.

Hereinafter, a method of manufacturing the high-frequency semiconductor device configured as described above will be described with reference to the drawings.

FIGS. 6A to 6D show cross-sectional structures in the order of steps of the method of manufacturing the high-frequency semiconductor device according to the present embodiment. Here, in FIG. 6, the same components as those shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted. Only the differences from the first manufacturing method of the first embodiment will be described. 6B, an insulating film 21 made of SiN having a thickness of 200 nm is formed on the entire surface of the high dielectric layer 12 by using, for example, a CVD method, as shown in FIG.
Is deposited.

FIG. 7A schematically shows a distribution of electric lines of force of the coplanar line 13 according to the present embodiment. In FIG. 7A, the same components as those shown in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 7A, electric lines of force generated between the signal line 13a and the pair of ground lines 13b in the coplanar line 13 start from the insulating film 21 having a low relative dielectric constant (= 7) according to Snell's law. High dielectric layer 1 with high relative permittivity (= 200)
Since the light is refracted to the second side, the lines of electric force of the insulating film 21 are relatively sparse, and the lines of electric force in the high dielectric film 12 are relatively dense. The lines of electric force in the high dielectric film 12 are GaAs.
Since the light is refracted toward the substrate 11, the lines of electric force in the substrate 11 are relatively sparse.

As described above, since the electromagnetic wave propagating through the coplanar line 13 is strongly affected by the high dielectric layer 12 located around the coplanar line 13, the capacitance between lines in the transmission line theory increases. Moreover, since the insulating film 21 is provided below the coplanar line 13 as compared with the first embodiment, the signal line 13a and the ground line pair 13
b. As a result, as shown in the schematic diagram of FIG. 7B and the equivalent circuit diagram of the transmission line theory of FIG. 7C, the value of the line-to-line conductance 22 decreases.

Therefore, in the dielectric loss tangent shown in the above-mentioned relational expression (1), the conductivity σ of the molecule decreases and the dielectric constant ε of the denominator increases, so that the dielectric loss is further reduced. Therefore, the attenuation constant (power loss) represented by the sum of the dielectric loss and the conductor loss of the line is further reduced.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 8 shows a sectional configuration of a high-frequency semiconductor device according to the third embodiment of the present invention. In FIG.
The description of the same components as shown in FIG. 1 will be omitted by retaining the same reference numerals. In the present embodiment, SrT
It is characterized in that a filling layer 31 made of a high dielectric material is formed on the high dielectric layer 12 made of iO ₃ so as to cover between the lines 13 a and 13 b of the coplanar line 13 and to cover the upper surface. .

Hereinafter, a method of manufacturing the high-frequency semiconductor device configured as described above will be described with reference to the drawings.

FIGS. 9A to 9D show cross-sectional structures in the order of steps of the method for manufacturing the high-frequency semiconductor device according to the present embodiment. Here, in FIG. 9, the same components as those shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted. Only the differences from the first manufacturing method of the first embodiment will be described. 9D, as shown in FIG. 9D, the wiring metal thin film 13A shown in FIG. 9C is lifted off to form the coplanar line 13, and thereafter, the coplanar line 13 is formed using, for example, an RF sputtering method. By depositing SrTiO ₃ over the entire surface of the substrate 11 on which the line 13 is formed, each line 13 a, 1 on the high dielectric layer 12 is deposited.
3b and on the upper surfaces of the lines 13a and 13b.
A filling layer 31 made of O ₃ is formed.

FIG. 10A schematically shows a distribution of electric lines of force of the coplanar line 13 according to the present embodiment.
In FIG. 10A, the same components as those shown in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 10A, electric lines of force generated between the signal line 13a and the ground line pair 13b in the coplanar line 13 are concentrated on the high dielectric layer 12 having a high relative dielectric constant (= 200). Further, according to Snell's law, the electric flux lines are refracted from the high dielectric layer 12 having a high relative dielectric constant to the substrate 11 having a low relative dielectric constant (= 12.7).
The lines of electric force inside are sparse. Further, compared to the first embodiment, not only the lower side of the coplanar line 13 but also each line 1
Since the periphery of 3a, 13b is covered with the filling layer 31 made of a high dielectric material, electric lines of force between the lines 13a, 13b are provided below the filling layer 31 and the lines 13a, 13b. It concentrates on the high dielectric layer 12. as a result,
As shown in the schematic diagram of FIG. 10B and the equivalent circuit diagram of the transmission line theory of FIG. 10C, the value of the inter-line capacitance 32 is further increased.

Therefore, in the dielectric loss tangent shown in the above-mentioned relational expression (1), the dielectric constant ε of the denominator further increases.
The dielectric loss is further reduced. Therefore, the attenuation constant (power loss) represented by the sum of the dielectric loss and the conductor loss of the line
Is further reduced.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 11 shows a sectional configuration of a high-frequency semiconductor device according to the fourth embodiment of the present invention. In FIG. 11, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In the present embodiment, S
The line 13 between the lines 13a and 13b of the coplanar line 13 in the high dielectric layer 12 made of rTiO _3.
a, a groove 13 for dividing the high dielectric layer 12 along the 13b
a is formed.

Hereinafter, a method of manufacturing the high-frequency semiconductor device configured as described above will be described with reference to the drawings.

FIGS. 12A to 12E show cross-sectional structures in the order of steps of the method for manufacturing the high-frequency semiconductor device according to the present embodiment. Here, in FIG. 12, the same components as those shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted. Only the differences from the first manufacturing method of the first embodiment will be described. 12 (d), the wiring metal thin film 13A shown in FIG. 12 (c) is lifted off to form a coplanar line 13, and then each of the lines 13a, A resist pattern 41 having an opening having an opening width of 0.5 μm is formed in a region between the adjacent portions 13b.

Next, as shown in FIG. 12E, using the resist pattern 41 as a mask, the high dielectric layer 12 is milled using, for example, Ar to form a coplanar line in the high dielectric layer 12. 13 lines 13a, 1
A groove 12a for dividing the high dielectric layer 12 is formed between the layers 3b, and thereafter, the resist pattern 41 is removed.

FIG. 13 (a) schematically shows the distribution of electric lines of force of the coplanar line 13 according to the present embodiment.
In FIG. 13A, the same components as those shown in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 13A, electric lines of force generated between the signal line 13a and the ground line pair 13b in the coplanar line 13 are concentrated on the high dielectric layer 12 having a high relative dielectric constant (= 200). Further, according to Snell's law, the electric flux lines are refracted from the high dielectric layer 12 having a high relative dielectric constant to the substrate 11 having a low relative dielectric constant (= 12.7).
The lines of electric force inside are sparse. Further, as compared with the first embodiment, a groove 12a for dividing the high dielectric layer 12 is provided between the lines 13a and 13b in the high dielectric layer 12, so that the signal line 13a and the ground line pair are provided. 13b is reduced. As a result, as shown in the schematic diagram of FIG. 13B and the equivalent circuit diagram of the transmission line theory of FIG. 13C, the value of the line-to-line conductance 42 decreases.

Therefore, in the dielectric loss tangent shown in the above-mentioned relational expression (1), the conductivity σ of the molecule decreases and the dielectric constant ε of the denominator increases, so that the dielectric loss is further reduced. Therefore, the attenuation constant (power loss) represented by the sum of the dielectric loss and the conductor loss of the line is further reduced.

(Modification of Fourth Embodiment) Further, as a modification of the present embodiment, each groove 1 of the high dielectric layer 12 is formed.
2a is filled with a dielectric made of SiN. In this case, since the dielectric constant of the groove 12a is higher than that of air, the line-to-line capacitance 16 can be increased while the line-to-line conductance 42 is kept small, so that the dielectric loss can be further reduced.

In the first to fourth embodiments, S
Although the high dielectric layer 12 of rTiO ₃ is formed on the substrate 11 of GaAs, the substrate may be formed of the high dielectric layer 12 itself.

Although the coplanar line 13 is used as the uniplanar line, it may be a slot line composed of a pair of conductor films formed on the substrate 11 at predetermined intervals. Although SrTiO ₃ was used for the high dielectric layer 12,
Not limited to this, Ba _x Sr _1-x TiO ₃ (where x is 0
≦ x ≦ 1. _{), Pb x La y Zr 1} -xy TiO 3
(Where x and y are 0 ≦ x + y ≦ 1) or Ta ₂
It may be O ₅ .

When SrTiO ₃ is used for the high dielectric layer 12, SrTiO ₃ is placed between the substrate 11 and the high dielectric layer 12.
rO, Ir _x O _1-x , Ru _x O _1-x (where x is 0 ≦ x
≦ 1. ), An insulating layer made of Ta ₂ O ₅ , CeO ₂ or CaF ₂ is provided, since these have excellent lattice matching with SrTiO ₃ and a close linear expansion coefficient, they are made of SrTiO ₃ having excellent crystallinity. The high dielectric layer 12 can be formed.

Further, the high dielectric layer 12 according to the present embodiment
And the coplanar line 13 are made of GaAs having an active element.
Alternatively, when formed on a substrate made of InP, the transmission line of the MMIC in the millimeter wave band can be reliably realized. Also, substrate 1
If a high-dielectric layer 12 and a coplanar line 13 according to the present embodiment are formed on a glass substrate and an active element or a semiconductor chip including the active element is flip-chip mounted on the glass substrate, electrical characteristics can be obtained. A flip-chip mounted integrated circuit with excellent performance can be realized.

Further, the wavelength of the electromagnetic wave propagating through the coplanar line 13 is shortened by the high dielectric constant of the high dielectric layer 12, so that the circuit area can be correspondingly reduced. Can also be achieved.

[0064]

According to the high-frequency semiconductor device of the present invention, since the capacitance between the signal line and the ground line of the uniplanar line increases, the value of the dielectric loss tangent, which is inversely proportional to the dielectric constant, decreases, and as a result, the dielectric loss decreases. it can. Further, since the coplanar line is formed on the high dielectric layer, the wavelength of the electromagnetic wave propagating in the high dielectric becomes short, so that the circuit area can be reduced.

In the high frequency semiconductor device of the present invention, when the high dielectric layer is formed on the high resistance substrate, the high frequency semiconductor device can be formed more reliably than when the high dielectric layer is used as the substrate.

In the high-frequency semiconductor device of the present invention, if the high-resistance substrate is made of gallium arsenide or glass, when gallium arsenide is used, active elements and passive elements can be formed on the substrate.
In the case of glass, if a semiconductor chip having an active element and a passive element is flip-chip mounted, an MMI in a millimeter wave band can be obtained.
C can be easily realized.

When the high-frequency semiconductor device of the present invention further includes an insulating film provided between the high dielectric layer and the uniplanar line, the insulating film reduces the conductivity between the signal line and the ground line. Therefore, the value of the dielectric loss tangent, which is directly proportional to the conductivity, decreases, and as a result, the dielectric loss can be further reduced.

In the high-frequency semiconductor device according to the present invention, the uniplanar line is composed of a plurality of conductor films each provided at a distance from each other, and is provided at least between the plurality of conductor films, and is made of a high dielectric material. If a layer is further provided, since the high dielectric substance is interposed not only below the uniplanar line but also between the side portions of the lines, electric lines of force between the lines are further concentrated, so that the signal of the uniplanar line is The capacitance between the line and the ground line is further increased, so that the dielectric loss can be further reduced.

In the high-frequency semiconductor device according to the present invention, the uniplanar line is composed of a plurality of conductor films each provided at an interval from each other, and the high dielectric layer is formed along the uniplanar line between the plurality of conductor films. When the groove for dividing the high dielectric layer is provided, the conductivity between the signal line and the ground line in the groove for dividing the high dielectric layer is reduced, so that the dielectric loss can be further reduced.

In the high-frequency semiconductor device according to the present invention, when a high-resistance dielectric is filled in the groove of the high-dielectric layer,
Since the dielectric constant of the groove is higher than that of air, the capacitance between the signal lines and the ground line can be increased while the conductivity between the lines is kept small, so that the dielectric loss can be further reduced.

[0071] In the high-frequency semiconductor device of the present invention, the high dielectric _{layer, Ba x Sr 1-x TiO} 3, Pb x La y Zr
_{If it is made of 1-xy} TiO ₃ or Ta ₂ O ₅ , a high dielectric layer can be reliably formed.

According to the method of manufacturing the high-frequency semiconductor device of the present invention, the heat treatment is performed in a state where the thin film made of a metal having an excellent affinity for the high dielectric covers the high dielectric. Since the efficiency is improved, a desired dielectric constant can be realized for a high dielectric substance. In addition, since the heat treatment is performed in a state where the metal thin film covers the high dielectric, peeling of the high dielectric layer from the high resistance substrate after the heat treatment hardly occurs. As a result, the high-frequency semiconductor device of the present invention can be reliably realized.

[Brief description of the drawings]

FIG. 1 is a configuration sectional view showing a high-frequency semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2D are cross-sectional views in the order of steps showing a first method for manufacturing a high-frequency semiconductor device according to the first embodiment of the present invention.

FIG. 3A is a schematic diagram illustrating a distribution of lines of electric force between lines of the high-frequency semiconductor device according to the first embodiment of the present invention. FIG. 2B is a schematic diagram illustrating a capacitance between lines of the high-frequency semiconductor device according to the first embodiment of the present invention. (C) is an equivalent circuit diagram based on the transmission line theory in the high-frequency semiconductor device according to the first embodiment of the present invention.

FIGS. 4A to 4E are cross-sectional views in the order of steps showing a second method for manufacturing the high-frequency semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a configuration of a high-frequency semiconductor device according to a second embodiment of the present invention.

FIGS. 6A to 6D are cross-sectional views in the order of steps showing a method for manufacturing a high-frequency semiconductor device according to a second embodiment of the present invention.

FIG. 7A is a schematic diagram illustrating a distribution of lines of electric force between lines of a high-frequency semiconductor device according to a second embodiment of the present invention. (B) is a schematic diagram showing a capacitance between lines of the high-frequency semiconductor device according to the second embodiment of the present invention. (C) is an equivalent circuit diagram based on the transmission line theory in the high-frequency semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a sectional view showing a configuration of a high-frequency semiconductor device according to a third embodiment of the present invention.

FIGS. 9A to 9D are cross-sectional views illustrating a method of manufacturing a high-frequency semiconductor device according to a third embodiment of the present invention in the order of steps.

FIG. 10A is a schematic diagram illustrating a distribution of lines of electric force between lines of a high-frequency semiconductor device according to a third embodiment of the present invention. (B) is a schematic diagram showing a capacitance between lines of the high-frequency semiconductor device according to the third embodiment of the present invention. (C) is an equivalent circuit diagram based on the transmission line theory in the high-frequency semiconductor device according to the third embodiment of the present invention.

FIG. 11 is a sectional view showing a configuration of a high-frequency semiconductor device according to a fourth embodiment of the present invention.

FIGS. 12A to 12E are sectional views in the order of steps showing a method for manufacturing a high-frequency semiconductor device according to a fourth embodiment of the present invention.

FIG. 13A is a schematic diagram illustrating distribution of lines of electric force between lines of a high-frequency semiconductor device according to a fourth embodiment of the present invention. (B) is a schematic diagram showing the capacitance between lines of the high-frequency semiconductor device according to the fourth embodiment of the present invention. (C) is an equivalent circuit diagram based on the transmission line theory in the high-frequency semiconductor device according to the fourth embodiment of the present invention.

FIG. 14A is a configuration sectional view showing a conventional microstrip line. (B) is a sectional view showing a configuration of a conventional coplanar line.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Substrate 12 High dielectric layer 13 Coplanar line 13a Signal line 13b Ground line pair 13A Metal thin film for wiring 13B Metal thin film for wiring 15 Resist pattern 16 Line capacitance 17 Resist pattern 21 Insulating film 22 Conductance between lines 31 Filling layer 32 Between lines Capacitance 41 Resist pattern 42 Conductance between lines

Continuing from the front page (72) Inventor Shigeru Morimoto 1006 Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-8-111606 (JP, A) JP-A-7-221510 (JP) JP-A-4-91456 (JP, A) JP-A-2-104010 (JP, A) JP-A-62-250657 (JP, A) JP-A-11-510671 (JP, A) International publication 97 / 45874 (WO, A1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01P 3/08 H01L 23/12 301 H01P 3/02 H01P 11/00

Claims (8)

(57) [Claims] And the high dielectric layer 1. A formed on the high resistance substrate, <br/> Bei example and formed Yunipurena line on the high-dielectric layer, the high-dielectric layer, Ba _x Sr _1-x TiO ₃ (where x
Is 0 ≦ x ≦ 1. _{), Pb x La y Zr 1} -xy Ti
O ₃ (where x and y are 0 ≦ x + y ≦ 1) or T
high-frequency semiconductor device characterized by comprising the a ₂ O _5. 2. The high-frequency semiconductor device according to claim 1 , wherein said high-resistance substrate is made of gallium arsenide . 3. The high-frequency semiconductor device according to claim 1, further comprising an insulating film provided between said high dielectric layer and said uniplanar line. 4. The uniplanar line includes a plurality of conductive films each provided at an interval from each other, and further includes a filling layer provided at least between the plurality of conductive films and made of a high dielectric substance. The high-frequency semiconductor device according to claim 1, wherein 5. The uniplanar line includes a plurality of conductor films, each of which is provided at an interval from each other, and the high dielectric layer is provided between the plurality of conductor films along the uniplanar line. 2. The high-frequency semiconductor device according to claim 1, further comprising a groove for dividing the high dielectric layer. 6. The high-frequency semiconductor device according to claim 5 , wherein a high-resistance dielectric is filled in the groove of the high-dielectric layer. 7. The uniplanar line is a coplanar line including a signal line and a pair of ground lines spaced at predetermined intervals from both sides of the signal line, or a slot line including a pair of conductor films spaced at a predetermined interval. 2. The high-frequency semiconductor device according to claim 1, wherein: 8. The high dielectric layer is heat-treated in an oxygen atmosphere.
Is characterized by being formed by performing
The high-frequency semiconductor device according to claim 1.