JP3394696B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3394696B2 JP3394696B2 JP28406797A JP28406797A JP3394696B2 JP 3394696 B2 JP3394696 B2 JP 3394696B2 JP 28406797 A JP28406797 A JP 28406797A JP 28406797 A JP28406797 A JP 28406797A JP 3394696 B2 JP3394696 B2 JP 3394696B2
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- metal
- metal wiring
- electrode
- forming step
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体素子の集積回
路を保護し、かつ外部装置と半導体装置の電気的接続を
安定に確保し、さらにもっとも高密度な実装を可能とし
た半導体装置であり、情報通信機器、事務用電子機器、
家庭用電子機器、測定装置、組立ロボット等の産業用電
子機器、医療用電子機器、電子玩具等に用いられている
チップサイズパッケージ(以後CSPと称する)に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which protects an integrated circuit of semiconductor elements, stably secures an electrical connection between an external device and the semiconductor device, and enables the highest density mounting. Information and communication equipment, office electronic equipment,
The present invention relates to a chip size package (hereinafter referred to as CSP) used in household electronic devices, measuring devices, industrial electronic devices such as assembly robots, medical electronic devices, electronic toys, and the like.
【0002】[0002]
【従来の技術】以下、従来のCSPについて、図面を参
照しながら説明する。図4は従来のCSPを示す構成図
である。a)は平面図、b)はa)のA1−A2間の断
面図である。図4を参照しながら従来のCSPの構成に
ついて説明する。2. Description of the Related Art A conventional CSP will be described below with reference to the drawings. FIG. 4 is a block diagram showing a conventional CSP. a) is a plan view and b) is a cross-sectional view taken along line A1-A2 of a). The configuration of the conventional CSP will be described with reference to FIG.
【0003】素子外部との電気的な接続は第二の樹脂層
31上に形成されたパッケージ電極32で行われる。半
導体素子33の素子電極34と電気的に接続されている
金属配線35は第一の樹脂層36上に形成され、この金
属配線35により、半導体素子33の素子電極34とパ
ッケージ電極32が電気的に接続される。この時金属配
線35と素子電極33の間には、バリアメタルが存在し
ている。またパシベーション膜38上に形成される第一
の樹脂層36と第二の樹脂層31とにより、このCSP
が搭載されるプリント基板とCSPのSiとの熱膨張係
数の差によって生じる応力を緩和している。Electrical connection to the outside of the device is made by a package electrode 32 formed on the second resin layer 31. The metal wiring 35 electrically connected to the element electrode 34 of the semiconductor element 33 is formed on the first resin layer 36, and the metal wiring 35 electrically connects the element electrode 34 of the semiconductor element 33 and the package electrode 32. Connected to. At this time, a barrier metal exists between the metal wiring 35 and the device electrode 33. The CSP is formed by the first resin layer 36 and the second resin layer 31 formed on the passivation film 38.
The stress caused by the difference in the coefficient of thermal expansion between the printed circuit board on which is mounted and the Si of the CSP is relaxed.
【0004】[0004]
【発明が解決しようとする課題】従来のCSPにおいて
は第一の樹脂層上に金属配線を形成する際に、半導体素
子のAl電極上にTi/Pdをはじめとしたバリアメタ
ルを形成する必要がある。このバリアメタルの形成に
は、蒸着技術と電気的に貴な金属のエッチング技術を必
要とし、非常に難易度の高い技術と高いコストを課すこ
ととなっている。In the conventional CSP, when forming a metal wiring on the first resin layer, it is necessary to form a barrier metal such as Ti / Pd on the Al electrode of the semiconductor element. is there. The formation of this barrier metal requires vapor deposition technology and etching technology for electrically noble metals, which imposes extremely difficult technology and high cost.
【0005】本発明はこのような従来のCSPのバリア
メタルの形成に難易度の高い技術と高いコストが必要と
されるという課題を考慮し、バリアメタルの形成を行う
ことなくCSPの配線層の形成を行うことによって、従
来に比べて容易に、しかも低いコストで製造される半導
体装置及びその製造方法を提供することを目的とするも
のである。The present invention takes into consideration the problem that a technique of high difficulty and a high cost are required to form the barrier metal of such a conventional CSP, and the wiring layer of the CSP is formed without forming the barrier metal. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can be manufactured more easily and at a lower cost than the conventional method by forming the semiconductor device.
【0006】[0006]
【課題を解決するための手段】前述した課題を解決する
ために、請求項1の本発明は、表面にAlからなる素子
電極を有する半導体素子と、前記素子電極の位置に開口
部を有する第一の樹脂層と、前記第一の樹脂層上に形成
されたCuからなる金属配線と、前記素子電極上に直接
形成され、前記素子電極と前記金属配線とを接続する無
電解メッキにより形成されたNiからなる金属層と、前
記金属配線上と前記第一の樹脂層上に形成され、前記金
属配線上の一部分に開口部を有する第二の樹脂層と、前
記第二の樹脂層の開ロ部に配置され、前記金属配線と接
続する金属電極とを備えたことを特徴とする半導体装置
である。To solve the problems mentioned above SUMMARY OF THE INVENTION The present invention of claim 1 includes a semiconductor device having an element electrode made of Al on the surface, the having an opening at the position of the element electrode and one resin layer, wherein a metal wiring made of the first formed in the resin layer on Cu, formed directly on the device electrodes, no that connects the metal wiring and the element electrode
A metal layer made of Ni formed by electrolytic plating; a second resin layer formed on the metal wiring and the first resin layer and having an opening at a part of the metal wiring; disposed open portion of the resin layer is a semiconductor device characterized by comprising a metal electrode connected to the metal wiring.
【0007】また、請求項2の本発明は、半導体素子の
素子電極上に無電解メッキ法により金属層を形成する金
属層形成工程と、前記金属層形成工程の後に前記素子電
極の位置に開口部を設けるように前記半導体素子上に第
一の樹脂層を形成する第一樹脂層形成工程と、前記第一
樹脂層形成工程の後に前記第一の樹脂層上に前記金属層
と接続する金属配線を形成する金属配線形成工程と、前
記金属配線形成工程の後に前記金属配線の一部に開口部
を設けるように前記第一の樹脂層と前記金属配線層上に
第二の樹脂層を形成する第二樹脂層形成工程と、前記第
二樹脂層形成工程の後に前記第二の樹脂層の開口部に金
属電極を形成する金属電極形成工程とを備えることを特
徴とする半導体装置の製造方法である。Further, according to the present invention of claim 2, a metal layer forming step of forming a metal layer on an element electrode of a semiconductor element by an electroless plating method, and an opening at a position of the element electrode after the metal layer forming step. a first resin layer forming step of forming a first resin layer on the semiconductor element to provide a part, the first
And the metal wire forming step of forming a metal wiring connected to the metal layer on the first resin layer after the resin layer forming step, before
A second resin layer forming step of forming a second resin layer serial and the first resin layer so as to provide an opening in part of the metal wiring after the metal wiring formation process on the metal wiring layer, wherein First
A semiconductor equipment manufacturing method characterized in that it comprises a metal electrode forming step of forming a metal electrode in the opening of the second resin layer after the second resin layer forming step.
【0008】[0008]
【発明の実施の形態】以下に、本発明の実施の形態を図
面を参照して説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【0009】図1は本発明の第1の実施の形態における
CSPの平面図(a)、図aのA1−A2部の断面図
(b)、及び底面図(c)である。FIG. 1 is a plan view (a) of a CSP according to a first embodiment of the present invention, a cross-sectional view (b) and a bottom view (c) of an A1-A2 portion of FIG.
【0010】素子外部との電気的な接続は第二の樹脂層
1上に形成されたパッケージ電極2で行われる。必要が
あれば、この電極2に半田ボール3等の接続材料を形成
する。半導体素子4の素子電極5と電気的に接続されて
いる金属配線6は第一の樹脂層7上に形成され、この金
属配線6により、半導体素子4の素子電極5とパッケー
ジ電極2が電気的に接続される。この時、金属配線6は
素子電極5上に無電界メッキによって形成されたNi突
起8を介して形成され、素子電極5のAlと電気的接続
が行われる。Electrical connection to the outside of the device is made by the package electrode 2 formed on the second resin layer 1. If necessary, a connecting material such as a solder ball 3 is formed on this electrode 2. The metal wiring 6 electrically connected to the element electrode 5 of the semiconductor element 4 is formed on the first resin layer 7, and the metal wiring 6 electrically connects the element electrode 5 of the semiconductor element 4 and the package electrode 2 to each other. Connected to. At this time, the metal wiring 6 is formed on the element electrode 5 via the Ni protrusion 8 formed by electroless plating, and is electrically connected to Al of the element electrode 5.
【0011】すなわち、上述した第1の実施の形態にお
けるCSPは、工法的にも工程数が多くさらにコストも
かさむバリアメタルを用いていないので、従来に比べて
容易に、しかも低いコストで製造できる。That is, since the CSP in the above-described first embodiment does not use a barrier metal which has a large number of steps in terms of construction method and is costly, it can be manufactured more easily and at a lower cost than conventional ones. .
【0012】次に、図2を用いて、本発明の第2の実施
の形態におけるCSPの製造方法について説明する。本
実施の形態におけるCSPの製造方法によって、製造さ
れるCSPは、上述した第1の実施の形態におけるCS
Pと同じ構成のものである。Next, a method of manufacturing the CSP according to the second embodiment of the present invention will be described with reference to FIG. The CSP manufactured by the CSP manufacturing method according to the present embodiment is the CS according to the first embodiment described above.
It has the same configuration as P.
【0013】半導体素子を形成したSiウエハ9の素子
電極10上に無電解メッキ法を用いて高さ数μmのNi
突起11を形成する(a)。次に、ウエハ9全体(パシ
ベーション膜12上)に均一な厚さの第一の樹脂層13
(ポリイミド樹脂層あるいはエポキシ系の樹脂層)を形
成し、さらにNi突起11に相当する位置にビア14
(Ni突起11を露出させる微小穴)を形成する
(b)。第一の樹脂層13の形成は、スピンコート法に
より液状樹脂を均一に塗布し、加熱硬化させることによ
り、またビアの形成にはフォトマスクによるエッチング
法あるいはレーザーを用いる。次にウエハ9全体に蒸着
法あるいは無電界メッキ法を用いてCu等の金属層15
を形成し、さらにエッチングにより必要のない金属を取
り除き、金属配線パターン16を第一の樹脂層13およ
びNi突起11上に形成させる(c)。さらに、第二の
樹脂層17を第一の樹脂層13と同様の方法で形成し、
パッケージ電極18を形成させる位置にビア19(金属
配線パターン16の一部を露出させる微小穴)を形成す
る(d)。金属配線パターン16の形成と同様の方法を
用いて、パッケージ電極18を形成し、要すれば半田ボ
ールを装着する(e)。最後にウエハの裏面研磨とダイ
シングによる個片化により、CSP20が形成される。Ni having a height of several μm is formed on the device electrode 10 of the Si wafer 9 on which the semiconductor device is formed by electroless plating.
The protrusion 11 is formed (a). Next, the first resin layer 13 having a uniform thickness is formed on the entire wafer 9 (on the passivation film 12).
(Polyimide resin layer or epoxy resin layer) is formed, and the via 14 is formed at a position corresponding to the Ni protrusion 11.
(A minute hole exposing the Ni protrusion 11) is formed (b). The first resin layer 13 is formed by uniformly applying a liquid resin by a spin coating method and heating and curing it, and an etching method using a photomask or a laser is used for forming the via. Next, a metal layer 15 of Cu or the like is formed on the entire wafer 9 by vapor deposition or electroless plating.
Then, unnecessary metal is removed by etching to form a metal wiring pattern 16 on the first resin layer 13 and the Ni protrusion 11 (c). Further, the second resin layer 17 is formed in the same manner as the first resin layer 13,
A via 19 (a minute hole exposing a part of the metal wiring pattern 16) is formed at a position where the package electrode 18 is formed (d). The package electrode 18 is formed by using the same method as the method for forming the metal wiring pattern 16, and solder balls are mounted if necessary (e). Finally, the CSP 20 is formed by polishing the back surface of the wafer and dividing the wafer into individual pieces.
【0014】すなわち、上述した第2の実施の形態にお
けるCSPの製造方法は、工法的にも工程数が多くさら
にコストもかさむバリアメタルの形成工程を含んでない
ので、従来に比べて容易に、しかも低いコストでCSP
を製造できる製造方法である。That is, the CSP manufacturing method according to the second embodiment described above does not include a barrier metal forming step, which requires a large number of steps in terms of construction method and is costly. CSP at low cost
It is a manufacturing method capable of manufacturing.
【0015】次に図3を用いて、本発明の第3の実施の
形態におけるCSP製造方法について説明する。本実施
の形態におけるCSPの製造方法によって、製造される
CSPも、上述した第1の実施の形態におけるCSPと
同じ構成のものである。Next, a CSP manufacturing method according to the third embodiment of the present invention will be described with reference to FIG. The CSP manufactured by the CSP manufacturing method according to the present embodiment also has the same configuration as the CSP according to the above-described first embodiment.
【0016】半導体素子を形成したSiウエハ21全体
に、均一な第一の樹脂層22(ポリイミド樹脂層あるい
はエポキシ系の樹脂層)を形成し、素子電極23に相当
する位置にビア24(素子電極23を露出させる微小
穴)を形成する(a)。第一の樹脂層22の形成にはあ
らかじめ均一な厚さに加工された樹脂フィルムを接着剤
或は真空圧着及び加熱により形成する。この時の樹脂フ
ィルムは完全硬化されていないものであれば、そのまま
張り付け加熱圧着させる。また、ビアの形成方法につい
ては、上述した第2の実施の形態におけるCSPの製造
方法と同様である。次に、ウエハ21上の露出した素子
電極23上に無電解メッキ法によりNi突起25を形成
する(b)。以降の工程については、上述した第2の実
施の形態におけるCSPの製造方法と同様である。A uniform first resin layer 22 (polyimide resin layer or epoxy resin layer) is formed on the entire Si wafer 21 on which semiconductor elements are formed, and a via 24 (element electrode) is formed at a position corresponding to the element electrode 23. A micro hole exposing 23 is formed (a). To form the first resin layer 22, a resin film processed to have a uniform thickness in advance is formed by an adhesive or vacuum pressure bonding and heating. If the resin film at this time is not completely cured, the resin film is stuck and heat-pressed as it is. The method of forming the via is the same as the method of manufacturing the CSP in the second embodiment described above. Next, the Ni protrusion 25 is formed on the exposed element electrode 23 on the wafer 21 by electroless plating (b). Subsequent steps are the same as the method for manufacturing the CSP in the second embodiment described above.
【0017】すなわち、上述した第3の実施の形態にお
けるCSPの製造方法は、工法的にも工程数が多くさら
にコストもかさむバリアメタルの形成工程を含んでない
ので、従来に比べて容易に、しかも低いコストでCSP
を製造できる製造方法である。That is, the CSP manufacturing method according to the third embodiment described above does not include a barrier metal forming step, which requires a large number of steps in terms of construction method and is costly. CSP at low cost
It is a manufacturing method capable of manufacturing.
【0018】なお、本発明の金属層は、上述した第1〜
第3の実施の形態においては、Ni突起であるとして説
明したが、これに限らず、無電解メッキ法によって形成
され、素子電極および金属配線の材質と接合性のよい材
質の金属でありさえすればよい。The metal layer of the present invention includes the above-mentioned first to first layers.
In the third embodiment, the Ni protrusion is described, but the present invention is not limited to this, and even a metal that is formed by an electroless plating method and has a good bonding property with the material of the element electrode and the metal wiring may be used. Good.
【0019】また、本発明の半導体装置製造方法は、上
述した第2および第3の実施の形態においては、複数の
小素子の平面集合体を製造して、金属電極形成工程の
後、前記平面集合体をダイシングにより小素子毎に対応
する個片に分割するとして説明したが、個々の小素子を
単独に製造するとしてもよい。Further, in the semiconductor device manufacturing method of the present invention, in the above-described second and third embodiments, a planar aggregate of a plurality of small elements is manufactured, and after the metal electrode forming step, the planar surface is formed. Although the assembly has been described as being divided into individual pieces corresponding to each small element by dicing, each small element may be manufactured independently.
【0020】[0020]
【発明の効果】以上説明したところから明らかなよう
に、本発明は、バリアメタルの形成を行うことなくCS
Pの配線層の形成を行うことによって、従来に比べて容
易に、しかも低いコストで製造される半導体装置及びそ
の製造方法を提供することができる。As is apparent from the above description, according to the present invention, CS is formed without forming a barrier metal.
By forming the P wiring layer, it is possible to provide a semiconductor device that can be manufactured more easily and at a lower cost than a conventional one, and a manufacturing method thereof.
【図1】本発明の第1の実施の形態におけるCSPの平
面図、及び断面図。FIG. 1 is a plan view and a cross-sectional view of a CSP according to a first embodiment of the present invention.
【図2】本発明の第2の実施の形態におけるCSPの製
造方法を示す断面フロー図。FIG. 2 is a sectional flow chart showing a method of manufacturing a CSP according to a second embodiment of the present invention.
【図3】本発明の第3の実施の形態におけるCSP製造
方法を示す断面フロー図。FIG. 3 is a sectional flow chart showing a CSP manufacturing method according to a third embodiment of the present invention.
【図4】従来のCSPを示す構成図。FIG. 4 is a configuration diagram showing a conventional CSP.
1 第二の樹脂層 2 パッケージ電極 3 半田ボール 4 半導体素子 5 素子電極 6 金属配線 7 第一の樹脂層 8 Ni突起 9 Siウエハ 10 素子電極 11 Ni突起 12 パシベーション膜 13 第一の樹脂層 14 ビア 15 金属層 16 金属配線パターン 17 第二の樹脂層 18 パッケージ電極(及び半田ボール) 19 ビア 20 CSP 21 Siウエハ 22 第一の樹脂層 23 素子電極 24 ビア 25 Ni突起 26 金属配線パターン 27 第二の樹脂層 28 パッケージ電極(及び半田ボール) 29 ビア 30 CSP 31 第二の樹脂層 32 パッケージ電極 33 半導体素子 34 素子電極 35 金属配線パターン 36 第一の樹脂層 37 バリアメタル 38 パシベーション膜 39 ポリイミド樹脂層 1 Second resin layer 2 Package electrode 3 solder balls 4 Semiconductor element 5 element electrodes 6 metal wiring 7 First resin layer 8 Ni protrusion 9 Si wafer 10 element electrodes 11 Ni protrusion 12 passivation film 13 First resin layer 14 beer 15 Metal layer 16 metal wiring patterns 17 Second resin layer 18 Package electrodes (and solder balls) 19 beer 20 CSP 21 Si wafer 22 First resin layer 23 Element electrode 24 vias 25 Ni protrusion 26 metal wiring patterns 27 Second resin layer 28 Package electrodes (and solder balls) 29 beer 30 CSP 31 Second resin layer 32 package electrodes 33 Semiconductor element 34 element electrode 35 Metal wiring pattern 36 First resin layer 37 Barrier metal 38 passivation film 39 Polyimide resin layer
Claims (3)
導体素子と、前記素子電極の位置に開口部を有する第一
の樹脂層と、前記第一の樹脂層上に形成されたCuから
なる金属配線と、前記素子電極上に直接形成され、前記
素子電極と前記金属配線とを接続する無電解メッキによ
り形成されたNiからなる金属層と、前記金属配線上と
前記第一の樹脂層上に形成され、前記金属配線上の一部
分に開口部を有する第二の樹脂層と、前記第二の樹脂層
の開ロ部に配置され、前記金属配線と接続する金属電極
とを備えたことを特徴とする半導体装置。 And 1. A semiconductor device having an element electrode made of Al on the surface, a first resin layer having an opening at a position of the device electrodes, from the Cu formed on the first resin layer
And a metal wiring that is directly formed on the element electrode and that connects the element electrode and the metal wiring by electroless plating.
Formed by Ni , a second resin layer formed on the metal wiring and the first resin layer, and having an opening at a part of the metal wiring, and the second resin disposed open portion of the layer, the semiconductor device being characterized in that a metal electrode connected to the metal wiring.
法により金属層を形成する金属層形成工程と、前記金属
層形成工程の後に前記素子電極の位置に開口部を設ける
ように前記半導体素子上に第一の樹脂層を形成する第一
樹脂層形成工程と、前記第一樹脂層形成工程の後に前記
第一の樹脂層上に前記金属層と接続する金属配線を形成
する金属配線形成工程と、前記金属配線形成工程の後に
前記金属配線の一部に開口部を設けるように前記第一の
樹脂層と前記金属配線層上に第二の樹脂層を形成する第
二樹脂層形成工程と、前記第二樹脂層形成工程の後に前
記第二の樹脂層の開口部に金属電極を形成する金属電極
形成工程とを備えることを特徴とする半導体装置の製造
方法。2. A metal layer forming step of forming a metal layer on an element electrode of a semiconductor element by electroless plating, and the metal.
A first resin layer forming step of forming a first resin layer on the semiconductor element so as to provide an opening at the position of the element electrode after the layer forming step, and the first resin layer forming step after the first resin layer forming step . A metal wiring forming step of forming a metal wiring connected to the metal layer on the resin layer, and the first wiring so as to provide an opening in a part of the metal wiring after the metal wiring forming step . A second resin layer forming step of forming a second resin layer on the resin layer and the metal wiring layer, and a metal in the opening of the second resin layer after the second resin layer forming step. manufacturing method of a semiconductor equipment, characterized in that it comprises a metal electrode forming step of forming an electrode.
i、前記金属配線がCuであることを特徴とする請求項
2記載の半導体装置の製造方法。3. The device electrode is A1, and the metal layer is N.
i, the metal wiring is Cu
2. The method for manufacturing a semiconductor device according to 2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28406797A JP3394696B2 (en) | 1997-10-16 | 1997-10-16 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28406797A JP3394696B2 (en) | 1997-10-16 | 1997-10-16 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11121647A JPH11121647A (en) | 1999-04-30 |
| JP3394696B2 true JP3394696B2 (en) | 2003-04-07 |
Family
ID=17673869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28406797A Expired - Fee Related JP3394696B2 (en) | 1997-10-16 | 1997-10-16 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3394696B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3497722B2 (en) | 1998-02-27 | 2004-02-16 | 富士通株式会社 | Semiconductor device, method of manufacturing the same, and transfer tray thereof |
| KR100333383B1 (en) * | 1999-06-28 | 2002-04-18 | 박종섭 | method of strengthening jointing strength of solder ball of semiconductor package |
| KR20010061775A (en) * | 1999-12-29 | 2001-07-07 | 이수남 | wafer level package and method of fabricating the same |
| JP2001196405A (en) * | 2000-01-12 | 2001-07-19 | Toyo Kohan Co Ltd | Semiconductor device and method of manufacturing the same |
| KR100352236B1 (en) | 2001-01-30 | 2002-09-12 | 삼성전자 주식회사 | Wafer level package including ground metal layer |
| KR100452819B1 (en) * | 2002-03-18 | 2004-10-15 | 삼성전기주식회사 | Chip scale package and method of fabricating the same |
| JP2012074487A (en) * | 2010-09-28 | 2012-04-12 | Toppan Printing Co Ltd | Method of manufacturing semiconductor package |
-
1997
- 1997-10-16 JP JP28406797A patent/JP3394696B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11121647A (en) | 1999-04-30 |
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